arch/arm-native/kernel/intr.c

   1 /*
   2     Copyright � 2013-2015, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <inttypes.h>
   7 #include <aros/kernel.h>
   8 #include <aros/libcall.h>
   9 #include <hardware/intbits.h>
  10 #include <stddef.h>
  11 #include <string.h>
  12
  13 #include <proto/exec.h>
  14 #include <proto/kernel.h>
  15
  16 #include "kernel_cpu.h"
  17 #include "kernel_intern.h"
  18 #include "kernel_debug.h"
  19 #include "kernel_interrupts.h"
  20 #include "kernel_intr.h"
  21
  22 #define BOOT_STACK_SIZE         (256 << 2)
  23 #define BOOT_TAGS_SIZE          (128 << 3)
  24
  25 #define DREGS(x)
  26 #define DIRQ(x)
  27 #define D(x)
  28
  29 /* linker exports */
  30 extern void *__intvecs_start, *__intvecs_end;
  31 extern void __arm_halt(void);
  32
  33 void ictl_enable_irq(uint8_t irq, struct KernelBase *KernelBase)
  34 {
  35     if (__arm_arosintern.ARMI_IRQEnable)
  36         __arm_arosintern.ARMI_IRQEnable(irq);
  37 }
  38
  39 void ictl_disable_irq(uint8_t irq, struct KernelBase *KernelBase)
  40 {
  41     if (__arm_arosintern.ARMI_IRQDisable)
  42         __arm_arosintern.ARMI_IRQDisable(irq);
  43 }
  44
  45 asm (
  46     ".globl __arm_halt                         \n"
  47     ".type __arm_halt,%function                \n"
  48     "__arm_halt:                               \n"
  49     "           b       __arm_halt             \n"
  50     );
  51
  52 /*
  53     ** UNDEF INSTRUCTION EXCEPTION
  54     return addr = lr
  55     entered in UND mode.
  56 */
  57
  58 asm (
  59     ".set       MODE_SYSTEM, 0x1f              \n"
  60
  61     ".globl __vectorhand_undef                 \n"
  62     ".type __vectorhand_undef,%function        \n"
  63     "__vectorhand_undef:                       \n"
  64     VECTCOMMON_START
  65     "           cpsid   i, #" STR(MODE_SYSTEM)"\n" // switch to system mode, with interrupts disabled..
  66     "           str     sp, [r0, #13*4]        \n"
  67     "           str     lr, [r0, #14*4]        \n" // store lr in ctx_lr
  68     "           mov     fp, #0                 \n" // clear fp
  69
  70     "           bl      handle_undef           \n"
  71
  72     VECTCOMMON_END
  73     );
  74
  75 void handle_undef(regs_t *regs)
  76 {
  77     bug("[Kernel] Trap ARM Undef Exception\n");
  78     bug("[Kernel]    exception #4 (Illegal instruction)\n");
  79     bug("[Kernel]    at 0x%p\n", regs[14]);
  80
  81     if (krnRunExceptionHandlers(KernelBase, 4, regs))
  82         return;
  83
  84     D(bug("[Kernel] exception handler(s) returned\n"));
  85
  86     if (core_Trap(4, regs))
  87     {
  88         D(bug("[Kernel] trap handler(s) returned\n"));
  89         return;
  90     }
  91
  92     bug("[Kernel] UNHANDLED EXCEPTION #4\n");
  93
  94     cpu_DumpRegs(regs);
  95
  96     __arm_halt();
  97 }
  98
  99 /*
 100     ** RESET HANDLER
 101     no return address,
 102     entered in SVC mode.
 103 */
 104
 105 asm (
 106     ".globl __vectorhand_reset                          \n"
 107     ".type __vectorhand_reset,%function                 \n"
 108     "__vectorhand_reset:                                \n"
 109     "           mov     sp, #0x1000 - 16                \n" // re-use bootstrap tmp stack
 110     "           mov     r0, sp                          \n"
 111     "           sub     r0, r0, #" STR(BOOT_STACK_SIZE)"\n" // get the boottag's
 112     "           sub     r0, r0, #" STR(BOOT_TAGS_SIZE) "\n"
 113     "           mov     fp, #0                          \n" // clear fp
 114
 115     "           ldr     pc, 2f                          \n" // jump into kernel resource
 116     "1:         b       1b                              \n"
 117     "2:         .word   kernel_cstart                   \n"
 118     );
 119
 120
 121 /* ** SWI HANDLER ** */
 122
 123 /** SWI handled in syscall.c */
 124
 125 /*
 126     ** IRQ HANDLER
 127     return address = lr - 4
 128     entered in IRQ mode.
 129 */
 130
 131 asm (
 132     ".set       MODE_IRQ, 0x12                 \n"
 133     ".set       MODE_SUPERVISOR, 0x13          \n"
 134     ".set       MODE_SYSTEM, 0x1f              \n"
 135
 136     ".globl __vectorhand_irq                   \n"
 137     ".type __vectorhand_irq,%function          \n"
 138     "__vectorhand_irq:                         \n"
 139     "           sub     lr, lr, #4             \n" // adjust lr_irq
 140     VECTCOMMON_START
 141     "           cpsid   i, #MODE_SYSTEM        \n" // switch to system mode, with interrupts disabled..
 142     "           str     sp, [r0, #13*4]        \n"
 143     "           str     lr, [r0, #14*4]        \n" // store lr in ctx_lr
 144     "           mov     fp, #0                 \n" // clear fp
 145
 146     "           bl      handle_irq             \n"
 147
 148     "           cpsid   i, #MODE_IRQ           \n" // switch to IRQ mode, with interrupts disabled..
 149     "           mov     r0, sp                 \n"
 150     "           ldr     r1, [r0, #16*4]        \n" // load the spr register
 151     "           and     r1, r1, #31            \n" // mask processor mode
 152     "           cmp     r1, #16                \n" // will we go back to user mode?
 153     "           cmpne   r1, #31                \n" // or maybe system mode which is basically privileged user mode?
 154     "           bne     1f                     \n" // no? don't call core_ExitInterrupt!
 155     "           mov     fp, #0                 \n" // clear fp
 156     "           bl      core_ExitInterrupt     \n"
 157     "1:                                        \n"
 158     VECTCOMMON_END
 159     );
 160
 161 void handle_irq(regs_t *regs)
 162 {
 163     DIRQ(bug("[KRN] ## IRQ ##\n"));
 164
 165     DREGS(cpu_DumpRegs(regs));
 166
 167     if (__arm_arosintern.ARMI_IRQProcess)
 168         __arm_arosintern.ARMI_IRQProcess();
 169
 170     DIRQ(bug("[KRN] IRQ processing finished\n"));
 171
 172     return;
 173 }
 174
 175 /*
 176     ** FIQ HANDLER
 177     return address = lr -4
 178     entered in FIQ mode.
 179 */
 180
 181 __attribute__ ((interrupt ("FIQ"))) void __vectorhand_fiq(void)
 182 {
 183     DIRQ(bug("[KRN] ## FIQ ##\n"));
 184
 185     DIRQ(bug("[KRN] FIQ processing finished\n"));
 186
 187     return;
 188 }
 189
 190 /*
 191     ** DATA ABORT EXCEPTION
 192     return address = lr - 8
 193     entered in ABT mode.
 194 */
 195
 196 asm (
 197     ".set       MODE_SYSTEM, 0x1f              \n"
 198
 199     ".globl __vectorhand_dataabort             \n"
 200     ".type __vectorhand_dataabort,%function    \n"
 201     "__vectorhand_dataabort:                   \n"
 202     "           sub     lr, lr, #8             \n" // adjust lr_irq
 203     VECTCOMMON_START
 204     "           cpsid   i, #MODE_SYSTEM        \n" // switch to system mode, with interrupts disabled..
 205     "           str     sp, [r0, #13*4]        \n"
 206     "           str     lr, [r0, #14*4]        \n" // store lr in ctx_lr
 207     "           mov     fp, #0                 \n" // clear fp
 208
 209     "           bl      handle_dataabort       \n"
 210
 211     VECTCOMMON_END
 212     );
 213
 214 void handle_dataabort(regs_t *regs)
 215 {
 216     register unsigned int far;
 217
 218     // Read fault address register
 219     asm volatile("mrc p15, 0, %[far], c6, c0, 0": [far] "=r" (far) );
 220
 221     bug("[Kernel] Trap ARM Data Abort Exception\n");
 222     bug("[Kernel]    exception #2 (Bus Error)\n");
 223     bug("[Kernel]    attempt to access 0x%p from 0x%p\n", far, regs[14]);
 224
 225     if (krnRunExceptionHandlers(KernelBase, 2, regs))
 226         return;
 227
 228     D(bug("[Kernel] exception handler(s) returned\n"));
 229
 230     if (core_Trap(2, regs))
 231     {
 232         D(bug("[Kernel] trap handler(s) returned\n"));
 233         return;
 234     }
 235
 236     bug("[Kernel] UNHANDLED EXCEPTION #2\n");
 237
 238     cpu_DumpRegs(regs);
 239
 240     __arm_halt();
 241 }
 242
 243 /*
 244     ** PREFETCH ABORT EXCEPTION
 245     return address = lr - 4
 246     entered in ABT mode.
 247 */
 248
 249 asm (
 250     ".set       MODE_SYSTEM, 0x1f              \n"
 251
 252     ".globl __vectorhand_prefetchabort         \n"
 253     ".type __vectorhand_prefetchabort,%function \n"
 254     "__vectorhand_prefetchabort:               \n"
 255     "           sub     lr, lr, #4             \n" // adjust lr_irq
 256     VECTCOMMON_START
 257     "           cpsid   i, #MODE_SYSTEM        \n" // switch to system mode, with interrupts disabled..
 258     "           str     sp, [r0, #13*4]        \n"
 259     "           str     lr, [r0, #14*4]        \n" // store lr in ctx_lr
 260     "           mov     fp, #0                 \n" // clear fp
 261
 262     "           bl      handle_prefetchabort   \n"
 263
 264     VECTCOMMON_END
 265     );
 266
 267 void handle_prefetchabort(regs_t *regs)
 268 {
 269     bug("[Kernel] Trap ARM Prefetch Abort Exception\n");
 270     bug("[Kernel]    exception #3 (Address Error)\n");
 271     bug("[Kernel]    at 0x%p\n", regs[14]);
 272
 273     if (krnRunExceptionHandlers(KernelBase, 3, regs))
 274         return;
 275
 276     D(bug("[Kernel] exception handler(s) returned\n"));
 277
 278     if (core_Trap(3, regs))
 279     {
 280         D(bug("[Kernel] trap handler(s) returned\n"));
 281         return;
 282     }
 283
 284     bug("[Kernel] UNHANDLED EXCEPTION #3\n");
 285
 286     cpu_DumpRegs(regs);
 287
 288     __arm_halt();
 289 }
 290
 291
 292 /* ** SETUP ** */
 293
 294 void arm_flush_cache(uint32_t addr, uint32_t length)
 295 {
 296     while (length)
 297     {
 298         __asm__ __volatile__("mcr p15, 0, %0, c7, c14, 1"::"r"(addr));
 299         addr += 32;
 300         length -= 32;
 301     }
 302     __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(addr));
 303 }
 304
 305 void arm_icache_invalidate(uint32_t addr, uint32_t length)
 306 {
 307     while (length)
 308     {
 309         __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 1"::"r"(addr));
 310         addr += 32;
 311         length -= 32;
 312     }
 313     __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(addr));
 314 }
 315
 316 void core_SetupIntr(void)
 317 {
 318     int irq;
 319     bug("[KRN] Initializing cpu vectors\n");
 320
 321     /* Copy vectors into place */
 322     memcpy(0, &__intvecs_start,
 323             (unsigned int)&__intvecs_end -
 324             (unsigned int)&__intvecs_start);
 325
 326     arm_flush_cache(0, 1024);
 327     arm_icache_invalidate(0, 1024);
 328
 329     D(bug("[KRN] Copied %d bytes from 0x%p to 0x00000000\n", (unsigned int)&__intvecs_end - (unsigned int)&__intvecs_start, &__intvecs_start));
 330
 331     D(
 332         unsigned int x = 0;
 333         bug("[KRN]: Vector dump-:");
 334         for (x=0; x < (unsigned int)&__intvecs_end - (unsigned int)&__intvecs_start; x++) {
 335             if ((x%16) == 0)
 336             {
 337                 bug("\n[KRN]:     %08x:", x);
 338             }
 339             bug(" %02x", *((volatile UBYTE *)x));
 340         }
 341         bug("\n");
 342     )
 343
 344     if (__arm_arosintern.ARMI_IRQInit)
 345         __arm_arosintern.ARMI_IRQInit();
 346 }