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- Fixed timeouts while waiting for an IRQ. The daemon stopped ticking
[AROS.git] / rom / devs / ata / lowlevel.c
blobc8d95e5ee8ca48ce260b951e9418cbf98f696d07
1 /*
2 Copyright © 2004-2014, The AROS Development Team. All rights reserved.
3 $Id$
4
5 Desc:
6 Lang: English
7 */
8
9 /*
10 * TODO:
11 * - put a critical section around DMA transfers (shared dma channels)
12 */
13
14 // use #define xxx(a) D(a) to enable particular sections.
15 #if DEBUG
16 #define DIRQ(a) D(a)
17 #define DIRQ_MORE(a)
18 #define DUMP(a) D(a)
19 #define DUMP_MORE(a)
20 #define DATA(a) D(a)
21 #define DATAPI(a) D(a)
22 #define DINIT(a) D(a)
23 #else
24 #define DIRQ(a) do { } while (0)
25 #define DIRQ_MORE(a) do { } while (0)
26 #define DUMP(a) do { } while (0)
27 #define DUMP_MORE(a) do { } while (0)
28 #define DATA(a) do { } while (0)
29 #define DATAPI(a) do { } while (0)
30 #define DINIT(a)
31 #endif
32 /* Errors that shouldn't happen */
33 #define DERROR(a) a
34
35 #include <aros/debug.h>
36 #include <exec/types.h>
37 #include <exec/exec.h>
38 #include <exec/resident.h>
39 #include <utility/utility.h>
40 #include <oop/oop.h>
41
42 #include <proto/exec.h>
43 #include <devices/timer.h>
44
45 #include "ata.h"
46 #include "ata_bus.h"
47 #include "timer.h"
48
49 static BYTE ata_Identify(struct ata_Unit *unit);
50 static BYTE ata_ReadSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
51 static BYTE ata_ReadSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
52 static BYTE ata_ReadMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
53 static BYTE ata_ReadMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
54 static BYTE ata_ReadDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
55 static BYTE ata_ReadDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
56 static BYTE ata_WriteSector32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
57 static BYTE ata_WriteSector64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
58 static BYTE ata_WriteMultiple32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
59 static BYTE ata_WriteMultiple64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
60 static BYTE ata_WriteDMA32(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
61 static BYTE ata_WriteDMA64(struct ata_Unit *, UQUAD, ULONG, APTR, ULONG *);
62 static void ata_ResetBus(struct ata_Bus *bus);
63 static BYTE ata_Eject(struct ata_Unit *);
64 static BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq,
65 BOOL fake_irq, UBYTE *stout);
66
67 static BYTE atapi_SendPacket(struct ata_Unit *unit, APTR packet, APTR data,
68 LONG datalen, BOOL *dma, BOOL write);
69 static BYTE atapi_DirectSCSI(struct ata_Unit *unit, struct SCSICmd *cmd);
70 static BYTE atapi_Read(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
71 static BYTE atapi_Write(struct ata_Unit *, ULONG, ULONG, APTR, ULONG *);
72 static BYTE atapi_Eject(struct ata_Unit *);
73 static ULONG atapi_RequestSense(struct ata_Unit* unit, UBYTE* sense,
74 ULONG senselen);
75 static BYTE atapi_EndCmd(struct ata_Unit *unit);
76
77 static void common_SetBestXferMode(struct ata_Unit* unit);
78
79 #define DEVHEAD_VAL 0xe0
80
81 #if DEBUG
82 static void dump(APTR mem, ULONG len)
83 {
84 register int i, j = 0;
85
86 DUMP_MORE(for (j=0; j<(len+15)>>4; ++j))
87 {
88 bug("[ATA ] %06lx: ", j<<4);
89
90 for (i=0; i<len-(j<<4); i++)
91 {
92 bug("%02lx ", ((unsigned char*)mem)[(j<<4)|i]);
93 if (i == 15)
94 break;
95 }
96
97 for (i=0; i<len-(j<<4); i++)
98 {
99 unsigned char c = ((unsigned char*)mem)[(j<<4)|i];
100
101 bug("%c", c >= 0x20 ? c<=0x7f ? c : '.' : '.');
102 if (i == 15)
103 break;
104 }
105 bug("\n");
106 }
107 }
108 #endif
109
110 static void ata_strcpy(const UBYTE *str1, UBYTE *str2, ULONG size)
111 {
112 register int i = size;
113
114 while (size--)
115 str2[size ^ 1] = str1[size];
116
117 while (i > 0 && str2[--i] <= ' ')
118 str2[i] = '\0';
119 }
120
121 static inline struct ata_Unit* ata_GetSelectedUnit(struct ata_Bus* bus)
122 {
123 return bus->ab_SelectedUnit;
124 }
125
126 static inline UBYTE ata_ReadStatus(struct ata_Bus *bus)
127 {
128 return PIO_In(bus, ata_Status);
129 }
130
131 static inline UBYTE ata_ReadAltStatus(struct ata_Bus *bus)
132 {
133 return PIO_InAlt(bus, ata_AltStatus);
134 }
135
136 static inline BOOL ata_SelectUnit(struct ata_Unit* unit)
137 {
138 struct ata_Bus *bus = unit->au_Bus;
139
140 if (unit == bus->ab_SelectedUnit)
141 return TRUE;
142
143 PIO_Out(bus, unit->au_DevMask, ata_DevHead);
144
145 do
146 {
147 ata_WaitNano(400, bus->ab_Base);
148 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
149 }
150 while (0 != (ATAF_BUSY & ata_ReadStatus(bus)));
151
152 bus->ab_SelectedUnit = unit;
153
154 return TRUE;
155 }
156
157 /*
158 * handle IRQ; still fast and efficient, supposed to verify if this irq is for us and take adequate steps
159 * part of code moved here from ata.c to reduce containment
160 */
161 static void ata_IRQSignalTask(struct ata_Bus *bus)
162 {
163 bus->ab_IntCnt++;
164 Signal(bus->ab_Task, 1UL << bus->ab_SleepySignal);
165 }
166
167 static void ata_IRQSetHandler(struct ata_Unit *unit,
168 void (*handler)(struct ata_Unit*, UBYTE), APTR piomem, ULONG blklen,
169 ULONG piolen)
170 {
171 if (NULL != handler)
172 unit->au_cmd_error = 0;
173
174 unit->au_cmd_data = piomem;
175 unit->au_cmd_length = (piolen < blklen) ? piolen : blklen;
176 unit->au_cmd_total = piolen;
177 unit->au_Bus->ab_HandleIRQ = handler;
178 }
179
180 static void ata_IRQNoData(struct ata_Unit *unit, UBYTE status)
181 {
182 if (status & ATAF_BUSY)
183 return;
184
185 if ((unit->au_cmd_error == 0) && (status & ATAF_ERROR))
186 unit->au_cmd_error = HFERR_BadStatus;
187
188 DIRQ(bug("[ATA%02ld] IRQ: NoData - done; status %02lx.\n", unit->au_UnitNum, status));
189 ata_IRQSetHandler(unit, NULL, NULL, 0, 0);
190 ata_IRQSignalTask(unit->au_Bus);
191 }
192
193 static void ata_IRQPIORead(struct ata_Unit *unit, UBYTE status)
194 {
195 if (status & ATAF_DATAREQ)
196 {
197 DIRQ(bug("[ATA%02ld] IRQ: PIOReadData - DRQ.\n", unit->au_UnitNum));
198
199 Unit_InS(unit, unit->au_cmd_data, unit->au_cmd_length);
200
201 /*
202 * Adjust data pointer and counter. If there's more data left for
203 * this transfer, keep same handler and wait for next interrupt
204 */
205 unit->au_cmd_data += unit->au_cmd_length;
206 unit->au_cmd_total -= unit->au_cmd_length;
207 if (unit->au_cmd_total != 0)
208 {
209 if (unit->au_cmd_length > unit->au_cmd_total)
210 unit->au_cmd_length = unit->au_cmd_total;
211 return;
212 }
213 DIRQ(bug("[ATA%02ld] IRQ: PIOReadData - transfer completed.\n",
214 unit->au_UnitNum));
215 }
216 else
217 unit->au_cmd_error = HFERR_BadStatus;
218 ata_IRQNoData(unit, status);
219 }
220
221 static void ata_PIOWriteBlk(struct ata_Unit *unit)
222 {
223 Unit_OutS(unit, unit->au_cmd_data, unit->au_cmd_length);
224
225 /*
226 * Adjust data pointer and counter
227 */
228 unit->au_cmd_data += unit->au_cmd_length;
229 unit->au_cmd_total -= unit->au_cmd_length;
230 if (unit->au_cmd_length > unit->au_cmd_total)
231 unit->au_cmd_length = unit->au_cmd_total;
232 }
233
234 static void ata_IRQPIOWrite(struct ata_Unit *unit, UBYTE status)
235 {
236 /*
237 * If there's more data left for this transfer, write it, keep same
238 * handler and wait for next interrupt
239 */
240 if (status & ATAF_DATAREQ) {
241 DIRQ(bug("[ATA%02ld] IRQ: PIOWriteData - DRQ.\n", unit->au_UnitNum));
242 ata_PIOWriteBlk(unit);
243 return;
244 }
245 else if (unit->au_cmd_total != 0)
246 unit->au_cmd_error = HFERR_BadStatus;
247 DIRQ(bug("[ATA%02ld] IRQ: PIOWriteData - done.\n", unit->au_UnitNum));
248 ata_IRQNoData(unit, status);
249 }
250
251 static void ata_IRQDMAReadWrite(struct ata_Unit *unit, UBYTE status)
252 {
253 struct ata_Bus *bus = unit->au_Bus;
254 ULONG stat = DMA_GetResult(bus);
255
256 DIRQ(bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %02lx\n", unit->au_UnitNum, status, stat));
257
258 if ((status & ATAF_ERROR) || stat)
259 {
260 /* This is turned on in order to help Phantom - Pavel Fedin <sonic_amiga@rambler.ru> */
261 DERROR(bug("[ATA%02ld] IRQ: IO status %02lx, DMA status %d\n", unit->au_UnitNum, status, stat));
262 DERROR(bug("[ATA%02ld] IRQ: ERROR %02lx\n", unit->au_UnitNum, PIO_In(bus, atapi_Error)));
263 DERROR(bug("[ATA%02ld] IRQ: DMA Failed.\n", unit->au_UnitNum));
264
265 unit->au_cmd_error = stat;
266 ata_IRQNoData(unit, status);
267 }
268 else if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
269 {
270 DIRQ(bug("[ATA%02ld] IRQ: DMA Done.\n", unit->au_UnitNum));
271 ata_IRQNoData(unit, status);
272 }
273 }
274
275 static void ata_IRQPIOReadAtapi(struct ata_Unit *unit, UBYTE status)
276 {
277 struct ata_Bus *bus = unit->au_Bus;
278 ULONG size = 0;
279 LONG remainder = 0;
280 UBYTE reason = PIO_In(bus, atapi_Reason);
281 DIRQ(bug("[ATAPI] Current status: %ld during READ\n", reason));
282
283 /* have we failed yet? */
284 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
285 ata_IRQNoData(unit, status);
286 if (status & ATAF_ERROR)
287 {
288 ata_IRQNoData(unit, status);
289 return;
290 }
291
292 /* anything for us please? */
293 if (ATAPIF_READ != (reason & ATAPIF_MASK))
294 return;
295
296 size = PIO_In(bus, atapi_ByteCntH) << 8 | PIO_In(bus, atapi_ByteCntL);
297 DIRQ(bug("[ATAPI] IRQ: data available for read (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
298
299 if (size > unit->au_cmd_total)
300 {
301 DERROR(bug("[ATAPI] IRQ: CRITICAL! MORE DATA OFFERED THAN STORAGE CAN TAKE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total));
302 remainder = size - unit->au_cmd_total;
303 size = unit->au_cmd_total;
304 }
305
306 Unit_InS(unit, unit->au_cmd_data, size);
307
308 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
309 unit->au_cmd_total -= size;
310
311 DIRQ(bug("[ATAPI] IRQ: %lu bytes read.\n", size));
312
313 /*
314 * Soak up excess bytes.
315 */
316 for (; remainder > 0; remainder -= 2)
317 Unit_InS(unit, &size, 2);
318
319 if (unit->au_cmd_total == 0)
320 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
321 }
322
323 static void ata_IRQPIOWriteAtapi(struct ata_Unit *unit, UBYTE status)
324 {
325 struct ata_Bus *bus = unit->au_Bus;
326 ULONG size = 0;
327 UBYTE reason = PIO_In(bus, atapi_Reason);
328
329 DIRQ(bug("[ATAPI] IRQ: Current status: %ld during WRITE\n", reason));
330
331 /*
332 * have we failed yet?
333 * CHECKME: This sequence actually can trigger ata_IRQNoData() twice.
334 * Is this correct ?
335 */
336 if (0 == (status & (ATAF_BUSY | ATAF_DATAREQ)))
337 ata_IRQNoData(unit, status);
338 if (status & ATAF_ERROR)
339 {
340 ata_IRQNoData(unit, status);
341 return;
342 }
343
344 /* anything for us please? */
345 if (ATAPIF_WRITE != (reason & ATAPIF_MASK))
346 return;
347
348 size = PIO_In(bus, atapi_ByteCntH) << 8 | PIO_In(bus, atapi_ByteCntL);
349 DIRQ(bug("[ATAPI] IRQ: data requested for write (%ld bytes, max: %ld bytes)\n", size, unit->au_cmd_total));
350
351 if (size > unit->au_cmd_total)
352 {
353 DERROR(bug("[ATAPI] IRQ: CRITICAL! MORE DATA REQUESTED THAN STORAGE CAN GIVE: %ld bytes vs %ld bytes left!\n", size, unit->au_cmd_total));
354 size = unit->au_cmd_total;
355 }
356
357 Unit_OutS(unit, unit->au_cmd_data, size);
358 unit->au_cmd_data = &((UBYTE*)unit->au_cmd_data)[size];
359 unit->au_cmd_total -= size;
360
361 DIRQ(bug("[ATAPI] IRQ: %lu bytes written.\n", size));
362
363 if (unit->au_cmd_total == 0)
364 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
365 }
366
367 /*
368 * wait for timeout or drive ready
369 */
370 static BOOL ata_WaitBusyTO(struct ata_Unit *unit, UWORD tout, BOOL irq,
371 BOOL fake_irq, UBYTE *stout)
372 {
373 struct ata_Bus *bus = unit->au_Bus;
374 UBYTE status;
375 ULONG step = 0;
376 BOOL res = TRUE;
377
378 if (bus->ab_Base->ata_Poll)
379 irq = FALSE;
380
381 status = PIO_InAlt(bus, ata_AltStatus);
382
383 if (irq)
384 {
385 /*
386 * wait for either IRQ or timeout
387 */
388 DIRQ(bug("[ATA%02ld] Waiting (Current status: %02lx)...\n",
389 unit->au_UnitNum, status));
390 step = ata_WaitTO(unit->au_Bus->ab_Timer, tout, 0,
391 1 << bus->ab_SleepySignal);
392
393 if (step == 0)
394 {
395 DERROR(bug("[ATA%02ld] Timeout while waiting for device to complete"
396 " operation\n", unit->au_UnitNum));
397
398 Disable();
399 if (fake_irq)
400 {
401 /* fake the interrupt we expected */
402 status = PIO_In(bus, ata_Status);
403 while (unit->au_Bus->ab_HandleIRQ != NULL)
404 unit->au_Bus->ab_HandleIRQ(unit, status);
405 }
406 else
407 {
408 /* do nothing if the interrupt eventually arrives */
409 ata_IRQSetHandler(unit, NULL, NULL, 0, 0);
410 res = FALSE;
411 }
412 Enable();
413 }
414 }
415 else
416 {
417 while (status & ATAF_BUSY)
418 {
419 ++step;
420
421 /*
422 * every 16n rounds do some extra stuff
423 */
424 if ((step & 15) == 0)
425 {
426 /*
427 * huhm. so it's been 16n rounds already. any timeout yet?
428 */
429 if (step >> 4 > tout * 1000)
430 {
431 DERROR(bug("[ATA%02ld] Device still busy after timeout."
432 " Aborting\n", unit->au_UnitNum));
433 res = FALSE;
434 break;
435 }
436
437 /*
438 * no timeout just yet, but it's not a good idea to keep
439 * spinning like that. let's give the system some time.
440 */
441 ata_WaitNano(1000000, bus->ab_Base);
442 }
443
444 status = PIO_InAlt(bus, ata_AltStatus);
445 }
446 }
447
448 /*
449 * get final status and clear any interrupt (may be neccessary if we
450 * were polling, for example)
451 */
452 status = PIO_In(bus, ata_Status);
453
454 /*
455 * be nice to frustrated developer
456 */
457 DIRQ(bug("[ATA%02ld] WaitBusy status: %lx / %ld\n", unit->au_UnitNum,
458 status, res));
459
460 /*
461 * release old junk
462 */
463 SetSignal(0, 1 << bus->ab_SleepySignal);
464
465 /*
466 * and say it went fine (i mean it)
467 */
468 if (stout)
469 *stout = status;
470 return res;
471 }
472
473 /*
474 * Procedure for sending ATA command blocks
475 * it appears LARGE but there's a lot of COMMENTS here :)
476 * handles *all* ata commands (no data, pio and dma)
477 * naturally could be split at some point in the future
478 * depends if anyone believes that the change for 50 lines
479 * would make slow ATA transfers any faster
480 */
481 static BYTE ata_exec_cmd(struct ata_Unit* unit, ata_CommandBlock *block)
482 {
483 struct ata_Bus *bus = unit->au_Bus;
484 BYTE err = 0;
485 APTR mem = block->buffer;
486 UBYTE status;
487
488 /*
489 * Use a short timeout for Identify commands. This is because some bad
490 * drives make us think that there are two devices on the bus when there
491 * is really only one, so when we send an Identify command to the phantom
492 * drive, we can't rely on getting an IRQ. Additionally, some real drives
493 * don't produce an IRQ when the Identify command is complete, so we call
494 * the interrupt handler "manually" if we time out while waiting for it.
495 */
496 BOOL fake_irq = block->command == ATA_IDENTIFY_DEVICE
497 || block->command == ATA_IDENTIFY_ATAPI;
498 UWORD timeout = fake_irq? 1 : TIMEOUT;
499
500 if (FALSE == ata_SelectUnit(unit))
501 return IOERR_UNITBUSY;
502
503 switch (block->type)
504 {
505 case CT_CHS:
506 case CT_LBA28:
507 if (block->sectors > 256)
508 {
509 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 256 sectors. Aborting.\n", unit->au_UnitNum, block->sectors));
510 return IOERR_BADLENGTH;
511 }
512
513 /* note:
514 * we want the above to fall in here!
515 * we really do (checking for secmul)
516 */
517
518 case CT_LBA48:
519 if (block->sectors > 65536)
520 {
521 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Transfer length (%ld) exceeds 65536 sectors. Aborting.\n", unit->au_UnitNum, block->sectors));
522 return IOERR_BADLENGTH;
523 }
524 if (block->secmul == 0)
525 {
526 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid transfer multiplier. Should be at least set to 1 (correcting)\n", unit->au_UnitNum));
527 block->secmul = 1;
528 }
529 break;
530
531 case CT_NoBlock:
532 break;
533
534 default:
535 DERROR(bug("[ATA%02ld] ata_exec_cmd: ERROR: Invalid command type %lx. Aborting.\n", unit->au_UnitNum, block->type));
536 return IOERR_NOCMD;
537 }
538
539 block->actual = 0;
540 D(bug("[ATA%02ld] ata_exec_cmd: Executing command %02lx\n", unit->au_UnitNum, block->command));
541
542 if (block->feature != 0)
543 PIO_Out(bus, block->feature, ata_Feature);
544
545 /*
546 * - set LBA and sector count
547 */
548 switch (block->type)
549 {
550 case CT_CHS:
551 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses CHS addressing (OLD)\n", unit->au_UnitNum));
552 {
553 ULONG cyl, head, sector;
554 ULONG tmp = unit->au_Heads * unit->au_Sectors;
555 cyl = block->blk / tmp;
556 head = (block->blk % tmp) / unit->au_Sectors;
557 sector = (block->blk % unit->au_Sectors) + 1;
558
559 PIO_Out(bus, ((head) & 0x0f) | unit->au_DevMask, ata_DevHead);
560 PIO_Out(bus, sector, ata_Sector);
561 PIO_Out(bus, cyl & 0xff, ata_CylinderLow);
562 PIO_Out(bus, (cyl >> 8) & 0xff, ata_CylinderHigh);
563 PIO_Out(bus, block->sectors, ata_Count);
564 }
565 break;
566 case CT_LBA28:
567 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 28bit LBA addressing (OLD)\n", unit->au_UnitNum));
568
569 PIO_Out(bus, ((block->blk >> 24) & 0x0f) | DEVHEAD_VAL | unit->au_DevMask, ata_DevHead);
570 PIO_Out(bus, block->blk >> 16, ata_LBAHigh);
571 PIO_Out(bus, block->blk >> 8, ata_LBAMid);
572 PIO_Out(bus, block->blk, ata_LBALow);
573 PIO_Out(bus, block->sectors, ata_Count);
574 break;
575
576 case CT_LBA48:
577 DATA(bug("[ATA%02ld] ata_exec_cmd: Command uses 48bit LBA addressing (NEW)\n", unit->au_UnitNum));
578
579 PIO_Out(bus, DEVHEAD_VAL | unit->au_DevMask, ata_DevHead);
580 PIO_Out(bus, block->blk >> 40, ata_LBAHigh);
581 PIO_Out(bus, block->blk >> 32, ata_LBAMid);
582 PIO_Out(bus, block->blk >> 24, ata_LBALow);
583
584 PIO_Out(bus, block->blk >> 16, ata_LBAHigh);
585 PIO_Out(bus, block->blk >> 8, ata_LBAMid);
586 PIO_Out(bus, block->blk, ata_LBALow);
587
588 PIO_Out(bus, block->sectors >> 8, ata_Count);
589 PIO_Out(bus, block->sectors, ata_Count);
590 break;
591
592 case CT_NoBlock:
593 DATA(bug("[ATA%02ld] ata_exec_cmd: Command does not address any block\n", unit->au_UnitNum));
594 break;
595 }
596
597 switch (block->method)
598 {
599 case CM_PIOWrite:
600 ata_IRQSetHandler(unit, &ata_IRQPIOWrite, mem, block->secmul << unit->au_SectorShift, block->length);
601 break;
602
603 case CM_PIORead:
604 ata_IRQSetHandler(unit, &ata_IRQPIORead, mem, block->secmul << unit->au_SectorShift, block->length);
605 break;
606
607 case CM_DMARead:
608 if (FALSE == DMA_Setup(bus, mem, block->length, TRUE))
609 return IOERR_ABORTED;
610
611 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
612 DMA_Start(bus);
613 break;
614
615 case CM_DMAWrite:
616 if (FALSE == DMA_Setup(bus, mem, block->length, FALSE))
617 return IOERR_ABORTED;
618
619 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
620 DMA_Start(bus);
621 break;
622
623 case CM_NoData:
624 ata_IRQSetHandler(unit, &ata_IRQNoData, NULL, 0, 0);
625 break;
626
627 default:
628 return IOERR_NOCMD;
629 break;
630 };
631
632 /*
633 * send command now
634 * let drive propagate its signals
635 */
636 DATA(bug("[ATA%02ld] ata_exec_cmd: Sending command\n", unit->au_UnitNum));
637
638 PIO_Out(bus, block->command, ata_Command);
639 ata_WaitNano(400, bus->ab_Base);
640 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
641
642 /*
643 * In case of PIO write the drive won't issue an IRQ before first
644 * data transfer, so we should poll the status and send the first
645 * block upon request.
646 */
647 if (block->method == CM_PIOWrite)
648 {
649 if (FALSE == ata_WaitBusyTO(unit, TIMEOUT, FALSE, FALSE, &status)) {
650 DERROR(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - no response from device. Status %02X\n", unit->au_UnitNum, status));
651 return IOERR_UNITBUSY;
652 }
653 if (status & ATAF_DATAREQ) {
654 DATA(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - DRQ.\n", unit->au_UnitNum));
655 ata_PIOWriteBlk(unit);
656 }
657 else
658 {
659 DERROR(bug("[ATA%02ld] ata_exec_cmd: PIOWrite - bad status: %02X\n", status));
660 return HFERR_BadStatus;
661 }
662 }
663
664 /*
665 * wait for drive to complete what it has to do
666 */
667 if (FALSE == ata_WaitBusyTO(unit, timeout, TRUE, fake_irq, &status))
668 {
669 DERROR(bug("[ATA%02ld] ata_exec_cmd: Device is late - no response\n", unit->au_UnitNum));
670 err = IOERR_UNITBUSY;
671 }
672 else
673 err = unit->au_cmd_error;
674
675 DATA(bug("[ATA%02ld] ata_exec_cmd: Command done\n", unit->au_UnitNum));
676
677 /*
678 * clean up DMA
679 * don't use 'mem' pointer here as it's already invalid.
680 */
681 switch (block->method)
682 {
683 case CM_DMARead:
684 DMA_End(bus, block->buffer, block->length, TRUE);
685 break;
686
687 case CM_DMAWrite:
688 DMA_End(bus, block->buffer, block->length, FALSE);
689 break;
690
691 default:
692 break; /* Shut up the compiler */
693 }
694
695 D(bug("[ATA%02ld] ata_exec_cmd: return code %ld\n", unit->au_UnitNum, err));
696 return err;
697 }
698
699 /*
700 * atapi packet iface
701 */
702 static BYTE atapi_SendPacket(struct ata_Unit *unit, APTR packet, APTR data,
703 LONG datalen, BOOL *dma, BOOL write)
704 {
705 struct ata_Bus *bus = unit->au_Bus;
706 *dma = *dma && (unit->au_Flags & AF_DMA) ? TRUE : FALSE;
707 LONG err = 0;
708
709 UBYTE cmd[12] = {
710 0
711 };
712 register int t=5,l=0;
713
714 if (((UBYTE*)packet)[0] > 0x1f)
715 t+= 4;
716 if (((UBYTE*)packet)[0] > 0x5f)
717 t+= 2;
718
719 switch (((UBYTE*)packet)[0])
720 {
721 case 0x28: // read10
722 case 0xa8: // read12
723 case 0xbe: // readcd
724 case 0xb9: // readcdmsf
725 case 0x2f: // verify
726 case 0x2a: // write
727 case 0xaa: // write12
728 case 0x2e: // writeverify
729 case 0xad: // readdvdstructure
730 case 0xa4: // reportkey
731 case 0xa3: // sendkey
732 break;
733 default:
734 *dma = FALSE;
735 }
736
737 while (l<=t)
738 {
739 cmd[l] = ((UBYTE*)packet)[l];
740 ++l;
741 }
742
743 DATAPI({
744 bug("[ATA%02lx] Sending %s ATA packet: ", unit->au_UnitNum, (*dma) ? "DMA" : "PIO");
745 l=0;
746 while (l<=t)
747 {
748 bug("%02lx ", ((UBYTE*)cmd)[l]);
749 ++l;
750 }
751 bug("\n");
752
753 if (datalen & 1)
754 bug("[ATAPI] ERROR: DATA LENGTH NOT EVEN! Rounding Up! (%ld bytes requested)\n", datalen);
755 });
756
757 datalen = (datalen+1)&~1;
758
759 if (FALSE == ata_SelectUnit(unit))
760 {
761 DATAPI(bug("[ATAPI] WaitBusy failed at first check\n"));
762 return IOERR_UNITBUSY;
763 }
764
765 /*
766 * tell device whether we want to read or write and if we want a dma transfer
767 */
768 PIO_Out(bus,
769 ((*dma) ? 1 : 0) | (((unit->au_Drive->id_DMADir & 0x8000) && !write) ? 4 : 0),
770 atapi_Features);
771 PIO_Out(bus, (datalen & 0xff), atapi_ByteCntL);
772 PIO_Out(bus, (datalen >> 8) & 0xff, atapi_ByteCntH);
773
774 /*
775 * once we're done with that, we can go ahead and inform device that we're about to send atapi packet
776 * after command is dispatched, we are obliged to give 400ns for the unit to parse command and set status
777 */
778 DATAPI(bug("[ATAPI] Issuing ATA_PACKET command.\n"));
779 ata_IRQSetHandler(unit, &ata_IRQNoData, 0, 0, 0);
780 PIO_Out(bus, ATA_PACKET, atapi_Command);
781 ata_WaitNano(400, bus->ab_Base);
782 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
783
784 ata_WaitBusyTO(unit, TIMEOUT, (unit->au_Drive->id_General & 0x60) == 0x20,
785 FALSE, NULL);
786 if (0 == (ata_ReadStatus(bus) & ATAF_DATAREQ))
787 return HFERR_BadStatus;
788
789 /*
790 * setup appropriate hooks
791 */
792 if (datalen == 0)
793 ata_IRQSetHandler(unit, &ata_IRQNoData, 0, 0, 0);
794 else if (*dma)
795 ata_IRQSetHandler(unit, &ata_IRQDMAReadWrite, NULL, 0, 0);
796 else if (write)
797 ata_IRQSetHandler(unit, &ata_IRQPIOWriteAtapi, data, 0, datalen);
798 else
799 ata_IRQSetHandler(unit, &ata_IRQPIOReadAtapi, data, 0, datalen);
800
801 if (*dma)
802 {
803 DATAPI(bug("[ATAPI] Starting DMA\n"));
804 DMA_Start(bus);
805 }
806
807 DATAPI(bug("[ATAPI] Sending packet\n"));
808 Unit_OutS(unit, cmd, 12);
809 ata_WaitNano(400, bus->ab_Base);
810
811 DATAPI(bug("[ATAPI] Status after packet: %lx\n", ata_ReadAltStatus(bus)));
812
813 /*
814 * Wait for command to complete. Note that two interrupts will occur
815 * before we wake up if this is a PIO data transfer
816 */
817 if (ata_WaitTO(unit->au_Bus->ab_Timer, TIMEOUT, 0,
818 1 << unit->au_Bus->ab_SleepySignal) == 0)
819 {
820 DATAPI(bug("[DSCSI] Command timed out.\n"));
821 err = IOERR_UNITBUSY;
822 }
823 else
824 err = atapi_EndCmd(unit);
825
826 if (*dma)
827 {
828 DMA_End(bus, data, datalen, !write);
829 }
830
831 DATAPI(bug("[ATAPI] IO error code %ld\n", err));
832 return err;
833 }
834
835 static BYTE atapi_DirectSCSI(struct ata_Unit *unit, struct SCSICmd *cmd)
836 {
837 APTR buffer = cmd->scsi_Data;
838 ULONG length = cmd->scsi_Length;
839 BYTE err = 0;
840 BOOL dma = FALSE;
841
842 cmd->scsi_Actual = 0;
843
844 DATAPI(bug("[DSCSI] Sending packet!\n"));
845
846 /*
847 * setup DMA & push command
848 * it does not really mean we will use dma here btw
849 */
850 if ((unit->au_Flags & AF_DMA) && (length !=0) && (buffer != 0))
851 {
852 dma = DMA_Setup(unit->au_Bus, buffer, length,
853 cmd->scsi_Flags & SCSIF_READ);
854 }
855
856 err = atapi_SendPacket(unit, cmd->scsi_Command, cmd->scsi_Data, cmd->scsi_Length, &dma, (cmd->scsi_Flags & SCSIF_READ) == 0);
857
858 DUMP({ if (cmd->scsi_Data != 0) dump(cmd->scsi_Data, cmd->scsi_Length); });
859
860 /*
861 * on check condition - grab sense data
862 */
863 DATAPI(bug("[ATA%02lx] atapi_DirectSCSI: SCSI Flags: %02lx / Error: %ld\n", unit->au_UnitNum, cmd->scsi_Flags, err));
864 if ((err != 0) && (cmd->scsi_Flags & SCSIF_AUTOSENSE))
865 {
866 DATAPI(bug("[DSCSI] atapi_DirectSCSI: Packet Failed. Calling atapi_RequestSense\n"));
867 atapi_RequestSense(unit, cmd->scsi_SenseData, cmd->scsi_SenseLength);
868 DUMP(dump(cmd->scsi_SenseData, cmd->scsi_SenseLength));
869 }
870
871 return err;
872 }
873
874 /*
875 * chops the large transfers into set of smaller transfers
876 * specifically useful when requested transfer size is >256 sectors for 28bit commands
877 */
878 static BYTE ata_exec_blk(struct ata_Unit *unit, ata_CommandBlock *blk)
879 {
880 BYTE err = 0;
881 ULONG part;
882 ULONG max=256;
883 ULONG count=blk->sectors;
884
885 if (blk->type == CT_LBA48)
886 max <<= 8;
887
888 DATA(bug("[ATA%02ld] ata_exec_blk: Accessing %ld sectors starting from %x%08x\n", unit->au_UnitNum, count, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
889 while ((count > 0) && (err == 0))
890 {
891 part = (count > max) ? max : count;
892 blk->sectors = part;
893 blk->length = part << unit->au_SectorShift;
894
895 DATA(bug("[ATA%02ld] Transfer of %ld sectors from %x%08x\n", unit->au_UnitNum, part, (ULONG)(blk->blk >> 32), (ULONG)blk->blk));
896 err = ata_exec_cmd(unit, blk);
897 DATA(bug("[ATA%02ld] ata_exec_blk: ata_exec_cmd returned %lx\n", unit->au_UnitNum, err));
898
899 blk->blk += part;
900 blk->buffer = &((char*)blk->buffer)[part << unit->au_SectorShift];
901 count -= part;
902 }
903 return err;
904 }
905
906 /*
907 * Initial device configuration that suits *all* cases
908 */
909 void ata_init_unit(struct ata_Bus *bus, struct ata_Unit *unit, UBYTE u)
910 {
911 struct ataBase *ATABase = bus->ab_Base;
912 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
913
914 unit->au_Bus = bus;
915 unit->pioInterface = bus->pioInterface;
916 unit->au_UnitNum = bus->ab_BusNum << 1 | u; // b << 8 | u
917 unit->au_DevMask = 0xa0 | (u << 4);
918
919 DINIT(bug("[ATA%02u] ata_init_unit: bus %u unit %d\n", unit->au_UnitNum, bus->ab_BusNum, u));
920
921 /* Set PIO transfer functions, either 16 or 32 bits */
922 if (ATABase->ata_32bit && OOP_GET(obj, aHidd_ATABus_Use32Bit))
923 Unit_Enable32Bit(unit);
924 else
925 Unit_Disable32Bit(unit);
926 }
927
928 BOOL ata_setup_unit(struct ata_Bus *bus, struct ata_Unit *unit)
929 {
930 /*
931 * this stuff always goes along the same way
932 * WARNING: NO INTERRUPTS AT THIS POINT!
933 */
934 UBYTE u;
935
936 DINIT(bug("[ATA ] ata_setup_unit(%d)\n", unit->au_UnitNum));
937 ata_SelectUnit(unit);
938
939 if (FALSE == ata_WaitBusyTO(unit, 1, FALSE, FALSE, NULL))
940 {
941 DINIT(bug("[ATA%02ld] ata_setup_unit: ERROR: Drive not ready for use. Keeping functions stubbed\n", unit->au_UnitNum));
942 return FALSE;
943 }
944
945 u = unit->au_UnitNum & 1;
946 switch (bus->ab_Dev[u])
947 {
948 /*
949 * safe fallback settings
950 */
951 case DEV_SATAPI:
952 case DEV_ATAPI:
953 case DEV_SATA:
954 case DEV_ATA:
955 unit->au_Identify = ata_Identify;
956 break;
957
958 default:
959 DINIT(bug("[ATA%02ld] ata_setup_unit: Unsupported device %lx. All functions will remain stubbed.\n", unit->au_UnitNum, bus->ab_Dev[u]));
960 return FALSE;
961 }
962
963 DINIT(bug("[ATA ] ata_setup_unit: Enabling IRQs\n"));
964 PIO_OutAlt(bus, 0x0, ata_AltControl);
965
966 /*
967 * now make unit self diagnose
968 */
969 if (unit->au_Identify(unit) != 0)
970 {
971 return FALSE;
972 }
973
974 return TRUE;
975 }
976
977 /*
978 * ata[pi] identify
979 */
980 static void common_SetXferMode(struct ata_Unit* unit, ata_XferMode mode)
981 {
982 struct ata_Bus *bus = unit->au_Bus;
983 BOOL dma = FALSE;
984 /*
985 * We can't set drive modes unless we also set the controller's timing registers
986 * FIXME: Implement aoHodd_ATABus_CanSetXferMode and moHidd_ATABus_SetXferMode
987 support.
988 * CHECKME: Current code lives with what machine's firmware has set for us. Looks
989 * like all firmwares set up the best DMA mode. But what if the firmware
990 * didn't set it up for some reason (the add-on controller which has been
991 * ignored by it
992 * for example) ? Shouldn't we check unit->au_UseModes here ?
993 */
994 #if 0
995 struct ataBase *ATABase = bus->ab_Base;
996 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
997 UBYTE type=0;
998 ata_CommandBlock acb =
999 {
1000 ATA_SET_FEATURES,
1001 0x03,
1002 0x01,
1003 0x00,
1004 0x00,
1005 0x00,
1006 0x00,
1007 0x00,
1008 0x00,
1009 CM_NoData,
1010 CT_LBA28
1011 };
1012 #endif
1013 DINIT(bug("[ATA%02ld] common_SetXferMode: Trying to set mode %d\n", unit->au_UnitNum, mode));
1014
1015 /* CHECKME: This condition should be not needed. */
1016 if ((!bus->dmaVectors) && (mode >= AB_XFER_MDMA0))
1017 {
1018 DINIT(bug("[ATA%02ld] common_SetXferMode: This controller does not own DMA port! Will set best PIO\n", unit->au_UnitNum));
1019 common_SetBestXferMode(unit);
1020 return;
1021 }
1022
1023 /*
1024 * first, ONLY for ATA devices, set new commands
1025 */
1026 if (0 == (unit->au_XferModes & AF_XFER_PACKET))
1027 {
1028 if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_UDMA6))
1029 {
1030 /* DMA, both multiword and Ultra */
1031 unit->au_Read32 = ata_ReadDMA32;
1032 unit->au_Write32 = ata_WriteDMA32;
1033 if (unit->au_XferModes & AF_XFER_48BIT)
1034 {
1035 unit->au_UseModes |= AF_XFER_48BIT;
1036 unit->au_Read64 = ata_ReadDMA64;
1037 unit->au_Write64 = ata_WriteDMA64;
1038 }
1039 }
1040 else if ((!unit->au_Bus->ab_Base->ata_NoMulti) && (unit->au_XferModes & AF_XFER_RWMULTI))
1041 {
1042 /* Multisector PIO */
1043 ata_IRQSetHandler(unit, ata_IRQNoData, NULL, 0, 0);
1044 PIO_Out(bus, unit->au_Drive->id_RWMultipleSize & 0xFF, ata_Count);
1045 PIO_Out(bus, ATA_SET_MULTIPLE, ata_Command);
1046 ata_WaitBusyTO(unit, -1, TRUE, FALSE, NULL);
1047
1048 unit->au_UseModes |= AF_XFER_RWMULTI;
1049 unit->au_Read32 = ata_ReadMultiple32;
1050 unit->au_Write32 = ata_WriteMultiple32;
1051 if (unit->au_XferModes & AF_XFER_48BIT)
1052 {
1053 unit->au_UseModes |= AF_XFER_48BIT;
1054 unit->au_Read64 = ata_ReadMultiple64;
1055 unit->au_Write64 = ata_WriteMultiple64;
1056 }
1057 }
1058 else
1059 {
1060 /* 1-sector PIO */
1061 unit->au_Read32 = ata_ReadSector32;
1062 unit->au_Write32 = ata_WriteSector32;
1063 if (unit->au_XferModes & AF_XFER_48BIT)
1064 {
1065 unit->au_UseModes |= AF_XFER_48BIT;
1066 unit->au_Read64 = ata_ReadSector64;
1067 unit->au_Write64 = ata_WriteSector64;
1068 }
1069 }
1070 }
1071
1072 #if 0 // We can't set drive modes unless we also set the controller's timing registers
1073 if ((mode >= AB_XFER_PIO0) && (mode <= AB_XFER_PIO4))
1074 {
1075 type = 8 + (mode - AB_XFER_PIO0);
1076 }
1077 else if ((mode >= AB_XFER_MDMA0) && (mode <= AB_XFER_MDMA2))
1078 {
1079 type = 32 + (mode - AB_XFER_MDMA0);
1080 dma=TRUE;
1081 }
1082 else if ((mode >= AB_XFER_UDMA0) && (mode <= AB_XFER_UDMA6))
1083 {
1084 type = 64 + (mode - AB_XFER_UDMA0);
1085 dma=TRUE;
1086 }
1087 else
1088 {
1089 type = 0;
1090 }
1091
1092 acb.sectors = type;
1093 if (0 != ata_exec_cmd(unit, &acb))
1094 {
1095 DINIT(bug("[ATA%02ld] common_SetXferMode: ERROR: Failed to apply new xfer mode.\n", unit->au_UnitNum));
1096 }
1097
1098 if (!HIDD_ATABus_SetXferMode(obj, mode))
1099 {
1100 /*
1101 * DMA mode setup failed.
1102 * FIXME: Should completely revert back to PIO protocol, or try lower mode.
1103 */
1104 dma = FALSE;
1105 }
1106 #else
1107 if (mode >= AB_XFER_MDMA0)
1108 dma = TRUE;
1109 #endif
1110
1111 if (dma)
1112 {
1113 unit->au_Flags |= AF_DMA; /* This flag is used by ATAPI protocol */
1114 }
1115 else
1116 {
1117 unit->au_UseModes &= ~AF_XFER_DMA_MASK;
1118 unit->au_Flags &= ~AF_DMA;
1119 }
1120 }
1121
1122 static void common_SetBestXferMode(struct ata_Unit* unit)
1123 {
1124 struct ata_Bus *bus = unit->au_Bus;
1125 struct ataBase *ATABase = bus->ab_Base;
1126 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
1127 int iter;
1128 int max = AB_XFER_UDMA6;
1129
1130 if ((!bus->dmaInterface)
1131 || ( !(unit->au_Drive->id_MWDMASupport & 0x0700)
1132 && !(unit->au_Drive->id_UDMASupport & 0x7f00)))
1133 {
1134 /*
1135 * make sure you reduce scan search to pio here!
1136 * otherwise this and above function will fall into infinite loop
1137 */
1138 DINIT(bug("[ATA%02ld] common_SetBestXferMode: DMA is disabled for"
1139 " this drive.\n", unit->au_UnitNum));
1140 max = AB_XFER_PIO4;
1141 }
1142 else if (!OOP_GET(obj, aHidd_ATABus_Use80Wire))
1143 {
1144 DINIT(bug("[ATA%02ld] common_SetBestXferMode: "
1145 "An 80-wire cable has not been detected for this drive. "
1146 "Disabling modes above UDMA2.\n", unit->au_UnitNum));
1147 max = AB_XFER_UDMA2;
1148 }
1149
1150 for (iter=max; iter>=AB_XFER_PIO0; --iter)
1151 {
1152 if (unit->au_XferModes & (1<<iter))
1153 {
1154 common_SetXferMode(unit, iter);
1155 return;
1156 }
1157 }
1158 bug("[ATA%02ld] common_SetBestXferMode: ERROR: device never reported any valid xfer modes. will continue at default\n", unit->au_UnitNum);
1159 common_SetXferMode(unit, AB_XFER_PIO0);
1160 }
1161
1162 static void common_DetectXferModes(struct ata_Unit* unit)
1163 {
1164 int iter;
1165
1166 DINIT(bug("[ATA%02ld] common_DetectXferModes: Supports\n", unit->au_UnitNum));
1167
1168 if (unit->au_Drive->id_Commands4 & (1 << 4))
1169 {
1170 DINIT(bug("[ATA%02ld] common_DetectXferModes: - Packet interface\n", unit->au_UnitNum));
1171 unit->au_XferModes |= AF_XFER_PACKET;
1172 unit->au_DirectSCSI = atapi_DirectSCSI;
1173 }
1174 else if (unit->au_Drive->id_Commands5 & (1 << 10))
1175 {
1176 /* ATAPI devices do not use this bit. */
1177 DINIT(bug("[ATA%02ld] common_DetectXferModes: - 48bit I/O\n", unit->au_UnitNum));
1178 unit->au_XferModes |= AF_XFER_48BIT;
1179 }
1180
1181 if ((unit->au_XferModes & AF_XFER_PACKET) || (unit->au_Drive->id_Capabilities & (1<< 9)))
1182 {
1183 DINIT(bug("[ATA%02ld] common_DetectXferModes: - LBA Addressing\n", unit->au_UnitNum));
1184 unit->au_XferModes |= AF_XFER_LBA;
1185 unit->au_UseModes |= AF_XFER_LBA;
1186 }
1187 else
1188 {
1189 DINIT(bug("[ATA%02ld] common_DetectXferModes: - DEVICE DOES NOT SUPPORT LBA ADDRESSING >> THIS IS A POTENTIAL PROBLEM <<\n", unit->au_UnitNum));
1190 unit->au_Flags |= AF_CHSOnly;
1191 }
1192
1193 if (unit->au_Drive->id_RWMultipleSize & 0xff)
1194 {
1195 DINIT(bug("[ATA%02ld] common_DetectXferModes: - R/W Multiple (%ld sectors per xfer)\n", unit->au_UnitNum, unit->au_Drive->id_RWMultipleSize & 0xff));
1196 unit->au_XferModes |= AF_XFER_RWMULTI;
1197 }
1198
1199 DINIT(bug("[ATA%02ld] common_DetectXferModes: - PIO0 PIO1 PIO2 ",
1200 unit->au_UnitNum));
1201 unit->au_XferModes |= AF_XFER_PIO(0) | AF_XFER_PIO(1) | AF_XFER_PIO(2);
1202 if (unit->au_Drive->id_ConfigAvailable & (1 << 1))
1203 {
1204 for (iter = 0; iter < 2; iter++)
1205 {
1206 if (unit->au_Drive->id_PIOSupport & (1 << iter))
1207 {
1208 DINIT(bug("PIO%ld ", 3 + iter));
1209 unit->au_XferModes |= AF_XFER_PIO(3 + iter);
1210 }
1211 }
1212 DINIT(bug("\n"));
1213 }
1214
1215 if ((unit->au_Drive->id_ConfigAvailable & (1 << 1)) &&
1216 (unit->au_Drive->id_Capabilities & (1<<8)))
1217 {
1218 DINIT(bug("[ATA%02ld] common_DetectXferModes: DMA:\n", unit->au_UnitNum));
1219 if (unit->au_Drive->id_MWDMASupport & 0xff)
1220 {
1221 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1222 for (iter = 0; iter < 3; iter++)
1223 {
1224 if (unit->au_Drive->id_MWDMASupport & (1 << iter))
1225 {
1226 unit->au_XferModes |= AF_XFER_MDMA(iter);
1227 if (unit->au_Drive->id_MWDMASupport & (256 << iter))
1228 {
1229 unit->au_UseModes |= AF_XFER_MDMA(iter);
1230 DINIT(bug("[MDMA%ld] ", iter));
1231 }
1232 DINIT(else bug("MDMA%ld ", iter);)
1233 }
1234 }
1235 DINIT(bug("\n"));
1236 }
1237
1238 if (unit->au_Drive->id_UDMASupport & 0xff)
1239 {
1240 DINIT(bug("[ATA%02ld] common_DetectXferModes: - ", unit->au_UnitNum));
1241 for (iter = 0; iter < 7; iter++)
1242 {
1243 if (unit->au_Drive->id_UDMASupport & (1 << iter))
1244 {
1245 unit->au_XferModes |= AF_XFER_UDMA(iter);
1246 if (unit->au_Drive->id_UDMASupport & (256 << iter))
1247 {
1248 unit->au_UseModes |= AF_XFER_UDMA(iter);
1249 DINIT(bug("[UDMA%ld] ", iter));
1250 }
1251 DINIT(else bug("UDMA%ld ", iter);)
1252 }
1253 }
1254 DINIT(bug("\n"));
1255 }
1256 }
1257 }
1258
1259 #define SWAP_LE_WORD(x) (x) = AROS_LE2WORD((x))
1260 #define SWAP_LE_LONG(x) (x) = AROS_LE2LONG((x))
1261 #define SWAP_LE_QUAD(x) (x) = AROS_LE2LONG((x) >> 32) | (((QUAD)(AROS_LE2LONG((x) & 0xffffffff))) << 32)
1262
1263 static BYTE ata_Identify(struct ata_Unit *unit)
1264 {
1265 BOOL atapi = unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] & 0x80;
1266 ata_CommandBlock acb =
1267 {
1268 atapi ? ATA_IDENTIFY_ATAPI : ATA_IDENTIFY_DEVICE,
1269 0,
1270 1,
1271 0,
1272 0,
1273 0,
1274 unit->au_Drive,
1275 sizeof(struct DriveIdent),
1276 0,
1277 CM_PIORead,
1278 CT_NoBlock
1279 };
1280 UWORD n = 0, *p, *limit;
1281
1282 /* If the right command fails, try the wrong one. If both fail, abort */
1283 DINIT(bug("[ATA%02ld] ata_Identify: Executing ATA_IDENTIFY_%s command\n",
1284 unit->au_UnitNum, atapi ? "ATAPI" : "DEVICE"));
1285 if (ata_exec_cmd(unit, &acb))
1286 {
1287 acb.command = atapi ? ATA_IDENTIFY_DEVICE : ATA_IDENTIFY_ATAPI;
1288 DINIT(bug("[ATA%02ld] ata_Identify: Executing ATA_IDENTIFY_%s command"
1289 " instead\n", unit->au_UnitNum, atapi ? "DEVICE" : "ATAPI"));
1290 if (ata_exec_cmd(unit, &acb))
1291 {
1292 DINIT(bug("[ATA%02ld] ata_Identify: Both command variants failed."
1293 " Discarding drive.\n",
1294 unit->au_UnitNum));
1295 return IOERR_OPENFAIL;
1296 }
1297 unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] ^= 0x82;
1298 atapi = unit->au_Bus->ab_Dev[unit->au_UnitNum & 1] & 0x80;
1299 DINIT(bug("[ATA%02ld] ata_Identify:"
1300 " Incorrect device signature detected."
1301 " Switching device type to %lx.\n", unit->au_UnitNum,
1302 unit->au_Bus->ab_Dev[unit->au_UnitNum & 1]));
1303 }
1304
1305 /*
1306 * If every second word is zero with 32-bit reads, switch to 16-bit
1307 * accesses for this drive and try again
1308 */
1309 if (unit->au_Bus->ab_Base->ata_32bit)
1310 {
1311 for (p = (UWORD *)unit->au_Drive, limit = p + 256; p < limit; p++)
1312 n |= *++p;
1313
1314 if (n == 0)
1315 {
1316 DINIT(bug("[ATA%02ld] Identify data was invalid with 32-bit reads."
1317 " Switching to 16-bit mode.\n", unit->au_UnitNum));
1318
1319 Unit_Disable32Bit(unit);
1320
1321 if (ata_exec_cmd(unit, &acb))
1322 return IOERR_OPENFAIL;
1323 }
1324 }
1325
1326 #if (AROS_BIG_ENDIAN != 0)
1327 SWAP_LE_WORD(unit->au_Drive->id_General);
1328 SWAP_LE_WORD(unit->au_Drive->id_OldCylinders);
1329 SWAP_LE_WORD(unit->au_Drive->id_SpecificConfig);
1330 SWAP_LE_WORD(unit->au_Drive->id_OldHeads);
1331 SWAP_LE_WORD(unit->au_Drive->id_OldSectors);
1332 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleSize);
1333 SWAP_LE_WORD(unit->au_Drive->id_Capabilities);
1334 SWAP_LE_WORD(unit->au_Drive->id_OldCaps);
1335 SWAP_LE_WORD(unit->au_Drive->id_OldPIO);
1336 SWAP_LE_WORD(unit->au_Drive->id_ConfigAvailable);
1337 SWAP_LE_WORD(unit->au_Drive->id_OldLCylinders);
1338 SWAP_LE_WORD(unit->au_Drive->id_OldLHeads);
1339 SWAP_LE_WORD(unit->au_Drive->id_OldLSectors);
1340 SWAP_LE_WORD(unit->au_Drive->id_RWMultipleTrans);
1341 SWAP_LE_WORD(unit->au_Drive->id_DMADir);
1342 SWAP_LE_WORD(unit->au_Drive->id_MWDMASupport);
1343 SWAP_LE_WORD(unit->au_Drive->id_PIOSupport);
1344 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_MinCycleTime);
1345 SWAP_LE_WORD(unit->au_Drive->id_MWDMA_DefCycleTime);
1346 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTime);
1347 SWAP_LE_WORD(unit->au_Drive->id_PIO_MinCycleTimeIORDY);
1348 SWAP_LE_WORD(unit->au_Drive->id_QueueDepth);
1349 SWAP_LE_WORD(unit->au_Drive->id_ATAVersion);
1350 SWAP_LE_WORD(unit->au_Drive->id_ATARevision);
1351 SWAP_LE_WORD(unit->au_Drive->id_Commands1);
1352 SWAP_LE_WORD(unit->au_Drive->id_Commands2);
1353 SWAP_LE_WORD(unit->au_Drive->id_Commands3);
1354 SWAP_LE_WORD(unit->au_Drive->id_Commands4);
1355 SWAP_LE_WORD(unit->au_Drive->id_Commands5);
1356 SWAP_LE_WORD(unit->au_Drive->id_Commands6);
1357 SWAP_LE_WORD(unit->au_Drive->id_UDMASupport);
1358 SWAP_LE_WORD(unit->au_Drive->id_SecurityEraseTime);
1359 SWAP_LE_WORD(unit->au_Drive->id_ESecurityEraseTime);
1360 SWAP_LE_WORD(unit->au_Drive->id_CurrentAdvPowerMode);
1361 SWAP_LE_WORD(unit->au_Drive->id_MasterPwdRevision);
1362 SWAP_LE_WORD(unit->au_Drive->id_HWResetResult);
1363 SWAP_LE_WORD(unit->au_Drive->id_AcousticManagement);
1364 SWAP_LE_WORD(unit->au_Drive->id_StreamMinimunReqSize);
1365 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimeDMA);
1366 SWAP_LE_WORD(unit->au_Drive->id_StreamingLatency);
1367 SWAP_LE_WORD(unit->au_Drive->id_StreamingTimePIO);
1368 SWAP_LE_WORD(unit->au_Drive->id_PhysSectorSize);
1369 SWAP_LE_WORD(unit->au_Drive->id_RemMediaStatusNotificationFeatures);
1370 SWAP_LE_WORD(unit->au_Drive->id_SecurityStatus);
1371
1372 SWAP_LE_LONG(unit->au_Drive->id_WordsPerLogicalSector);
1373 SWAP_LE_LONG(unit->au_Drive->id_LBASectors);
1374 SWAP_LE_LONG(unit->au_Drive->id_StreamingGranularity);
1375
1376 SWAP_LE_QUAD(unit->au_Drive->id_LBA48Sectors);
1377 #endif
1378
1379 DUMP(dump(unit->au_Drive, sizeof(struct DriveIdent)));
1380
1381 if (atapi)
1382 {
1383 unit->au_SectorShift = 11;
1384 unit->au_Read32 = atapi_Read;
1385 unit->au_Write32 = atapi_Write;
1386 unit->au_DirectSCSI = atapi_DirectSCSI;
1387 unit->au_Eject = atapi_Eject;
1388 unit->au_Flags |= AF_DiscChanged;
1389 unit->au_DevType = (unit->au_Drive->id_General >>8) & 0x1f;
1390 unit->au_XferModes = AF_XFER_PACKET;
1391 unit->au_UseModes |= AF_XFER_PACKET; /* OR because this field may already contain AF_XFER_PIO32 */
1392 }
1393 else
1394 {
1395 unit->au_SectorShift = 9;
1396 unit->au_DevType = DG_DIRECT_ACCESS;
1397 unit->au_Read32 = ata_ReadSector32;
1398 unit->au_Write32 = ata_WriteSector32;
1399 unit->au_Eject = ata_Eject;
1400 unit->au_XferModes = 0;
1401 unit->au_Flags |= AF_DiscPresent | AF_DiscChanged;
1402 }
1403
1404 ata_strcpy(unit->au_Drive->id_Model, unit->au_Model, 40);
1405 ata_strcpy(unit->au_Drive->id_SerialNumber, unit->au_SerialNumber, 20);
1406 ata_strcpy(unit->au_Drive->id_FirmwareRev, unit->au_FirmwareRev, 8);
1407
1408 bug("[ATA%02ld] ata_Identify: Unit info: %s / %s / %s\n", unit->au_UnitNum, unit->au_Model, unit->au_SerialNumber, unit->au_FirmwareRev);
1409 common_DetectXferModes(unit);
1410 common_SetBestXferMode(unit);
1411
1412 if (unit->au_Drive->id_General & 0x80)
1413 {
1414 DINIT(bug("[ATA%02ld] ata_Identify: Device is removable.\n", unit->au_UnitNum));
1415 unit->au_Flags |= AF_Removable;
1416 }
1417
1418 unit->au_Capacity = unit->au_Drive->id_LBASectors;
1419 unit->au_Capacity48 = unit->au_Drive->id_LBA48Sectors;
1420 DINIT(bug("[ATA%02ld] ata_Identify: Unit LBA: %07lx 28bit / %04lx:%08lx 48bit addressable blocks\n", unit->au_UnitNum, unit->au_Capacity, (ULONG)(unit->au_Capacity48 >> 32), (ULONG)(unit->au_Capacity48 & 0xfffffffful)));
1421
1422 if (atapi)
1423 {
1424 /*
1425 * ok, this is not very original, but quite compatible :P
1426 */
1427 switch (unit->au_DevType)
1428 {
1429 case DG_CDROM:
1430 case DG_WORM:
1431 case DG_OPTICAL_DISK:
1432 unit->au_SectorShift = 11;
1433 unit->au_Heads = 1;
1434 unit->au_Sectors = 75;
1435 unit->au_Cylinders = 4440;
1436 break;
1437
1438 case DG_DIRECT_ACCESS:
1439 unit->au_SectorShift = 9;
1440 if (!strcmp("LS-120", &unit->au_Model[0]))
1441 {
1442 unit->au_Heads = 2;
1443 unit->au_Sectors = 18;
1444 unit->au_Cylinders = 6848;
1445 }
1446 else if (!strcmp("ZIP 100 ", &unit->au_Model[8]))
1447 {
1448 unit->au_Heads = 1;
1449 unit->au_Sectors = 64;
1450 unit->au_Cylinders = 3072;
1451 }
1452 break;
1453 }
1454
1455 atapi_TestUnitOK(unit);
1456 }
1457 else
1458 {
1459 /*
1460 For drive capacities > 8.3GB assume maximal possible layout.
1461 It really doesn't matter here, as BIOS will not handle them in
1462 CHS way anyway :)
1463 i guess this just solves that weirdo div-by-zero crash, if nothing
1464 else...
1465 */
1466 if ((unit->au_Drive->id_LBA48Sectors > (63 * 255 * 1024)) ||
1467 (unit->au_Drive->id_LBASectors > (63 * 255 * 1024)))
1468 {
1469 ULONG div = 1;
1470 /*
1471 * TODO: this shouldn't be casted down here.
1472 */
1473 ULONG sec = unit->au_Capacity48;
1474
1475 if (sec < unit->au_Capacity48)
1476 sec = ~((ULONG)0);
1477
1478 if (sec < unit->au_Capacity)
1479 sec = unit->au_Capacity;
1480
1481 unit->au_Sectors = 63;
1482 sec /= 63;
1483 /*
1484 * keep dividing by 2
1485 */
1486 do
1487 {
1488 if (((sec >> 1) << 1) != sec)
1489 break;
1490 if ((div << 1) > 255)
1491 break;
1492 div <<= 1;
1493 sec >>= 1;
1494 } while (1);
1495
1496 do
1497 {
1498 if (((sec / 3) * 3) != sec)
1499 break;
1500 if ((div * 3) > 255)
1501 break;
1502 div *= 3;
1503 sec /= 3;
1504 } while (1);
1505
1506 unit->au_Cylinders = sec;
1507 unit->au_Heads = div;
1508 }
1509 else
1510 {
1511 unit->au_Cylinders = unit->au_Drive->id_OldLCylinders;
1512 unit->au_Heads = unit->au_Drive->id_OldLHeads;
1513 unit->au_Sectors = unit->au_Drive->id_OldLSectors;
1514 unit->au_Capacity = unit->au_Cylinders * unit->au_Heads * unit->au_Sectors;
1515 }
1516 }
1517
1518 DINIT(bug("[ATA%02ld] ata_Identify: Unit CHS: %d/%d/%d\n", unit->au_UnitNum, unit->au_Cylinders, unit->au_Heads, unit->au_Sectors));
1519
1520 return 0;
1521 }
1522
1523 /*
1524 * ata read32 commands
1525 */
1526 static BYTE ata_ReadSector32(struct ata_Unit *unit, ULONG block,
1527 ULONG count, APTR buffer, ULONG *act)
1528 {
1529 ata_CommandBlock acb =
1530 {
1531 ATA_READ,
1532 0,
1533 1,
1534 0,
1535 block,
1536 count,
1537 buffer,
1538 count << unit->au_SectorShift,
1539 0,
1540 CM_PIORead,
1541 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1542 };
1543 BYTE err;
1544
1545 D(bug("[ATA%02ld] ata_ReadSector32()\n", unit->au_UnitNum));
1546
1547 *act = 0;
1548 if (0 != (err = ata_exec_blk(unit, &acb)))
1549 return err;
1550
1551 *act = count << unit->au_SectorShift;
1552 return 0;
1553 }
1554
1555 static BYTE ata_ReadMultiple32(struct ata_Unit *unit, ULONG block,
1556 ULONG count, APTR buffer, ULONG *act)
1557 {
1558 ata_CommandBlock acb =
1559 {
1560 ATA_READ_MULTIPLE,
1561 0,
1562 unit->au_Drive->id_RWMultipleSize & 0xff,
1563 0,
1564 block,
1565 count,
1566 buffer,
1567 count << unit->au_SectorShift,
1568 0,
1569 CM_PIORead,
1570 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1571 };
1572 BYTE err;
1573
1574 D(bug("[ATA%02ld] ata_ReadMultiple32()\n", unit->au_UnitNum));
1575
1576 *act = 0;
1577 if (0 != (err = ata_exec_blk(unit, &acb)))
1578 return err;
1579
1580 *act = count << unit->au_SectorShift;
1581 return 0;
1582 }
1583
1584 static BYTE ata_ReadDMA32(struct ata_Unit *unit, ULONG block,
1585 ULONG count, APTR buffer, ULONG *act)
1586 {
1587 BYTE err;
1588 ata_CommandBlock acb =
1589 {
1590 ATA_READ_DMA,
1591 0,
1592 1,
1593 0,
1594 block,
1595 count,
1596 buffer,
1597 count << unit->au_SectorShift,
1598 0,
1599 CM_DMARead,
1600 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1601 };
1602
1603 D(bug("[ATA%02ld] ata_ReadDMA32()\n", unit->au_UnitNum));
1604
1605 *act = 0;
1606 if (0 != (err = ata_exec_blk(unit, &acb)))
1607 return err;
1608
1609 *act = count << unit->au_SectorShift;
1610 return 0;
1611 }
1612
1613 /*
1614 * ata read64 commands
1615 */
1616 static BYTE ata_ReadSector64(struct ata_Unit *unit, UQUAD block,
1617 ULONG count, APTR buffer, ULONG *act)
1618 {
1619 ata_CommandBlock acb =
1620 {
1621 ATA_READ64,
1622 0,
1623 1,
1624 0,
1625 block,
1626 count,
1627 buffer,
1628 count << unit->au_SectorShift,
1629 0,
1630 CM_PIORead,
1631 CT_LBA48
1632 };
1633 BYTE err = 0;
1634
1635 D(bug("[ATA%02ld] ata_ReadSector64()\n", unit->au_UnitNum));
1636
1637 *act = 0;
1638 if (0 != (err = ata_exec_blk(unit, &acb)))
1639 return err;
1640
1641 *act = count << unit->au_SectorShift;
1642 return 0;
1643 }
1644
1645 static BYTE ata_ReadMultiple64(struct ata_Unit *unit, UQUAD block,
1646 ULONG count, APTR buffer, ULONG *act)
1647 {
1648 ata_CommandBlock acb =
1649 {
1650 ATA_READ_MULTIPLE64,
1651 0,
1652 unit->au_Drive->id_RWMultipleSize & 0xff,
1653 0,
1654 block,
1655 count,
1656 buffer,
1657 count << unit->au_SectorShift,
1658 0,
1659 CM_PIORead,
1660 CT_LBA48
1661 };
1662 BYTE err;
1663
1664 D(bug("[ATA%02ld] ata_ReadMultiple64()\n", unit->au_UnitNum));
1665
1666 *act = 0;
1667 if (0 != (err = ata_exec_blk(unit, &acb)))
1668 return err;
1669
1670 *act = count << unit->au_SectorShift;
1671 return 0;
1672 }
1673
1674 static BYTE ata_ReadDMA64(struct ata_Unit *unit, UQUAD block,
1675 ULONG count, APTR buffer, ULONG *act)
1676 {
1677 ata_CommandBlock acb =
1678 {
1679 ATA_READ_DMA64,
1680 0,
1681 1,
1682 0,
1683 block,
1684 count,
1685 buffer,
1686 count << unit->au_SectorShift,
1687 0,
1688 CM_DMARead,
1689 CT_LBA48
1690 };
1691 BYTE err;
1692
1693 D(bug("[ATA%02ld] ata_ReadDMA64()\n", unit->au_UnitNum));
1694
1695 *act = 0;
1696 if (0 != (err = ata_exec_blk(unit, &acb)))
1697 return err;
1698
1699 *act = count << unit->au_SectorShift;
1700 return 0;
1701 }
1702
1703 /*
1704 * ata write32 commands
1705 */
1706 static BYTE ata_WriteSector32(struct ata_Unit *unit, ULONG block,
1707 ULONG count, APTR buffer, ULONG *act)
1708 {
1709 ata_CommandBlock acb =
1710 {
1711 ATA_WRITE,
1712 0,
1713 1,
1714 0,
1715 block,
1716 count,
1717 buffer,
1718 count << unit->au_SectorShift,
1719 0,
1720 CM_PIOWrite,
1721 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1722 };
1723 BYTE err;
1724
1725 D(bug("[ATA%02ld] ata_WriteSector32()\n", unit->au_UnitNum));
1726
1727 *act = 0;
1728 if (0 != (err = ata_exec_blk(unit, &acb)))
1729 return err;
1730
1731 *act = count << unit->au_SectorShift;
1732 return 0;
1733 }
1734
1735 static BYTE ata_WriteMultiple32(struct ata_Unit *unit, ULONG block,
1736 ULONG count, APTR buffer, ULONG *act)
1737 {
1738 ata_CommandBlock acb =
1739 {
1740 ATA_WRITE_MULTIPLE,
1741 0,
1742 unit->au_Drive->id_RWMultipleSize & 0xff,
1743 0,
1744 block,
1745 count,
1746 buffer,
1747 count << unit->au_SectorShift,
1748 0,
1749 CM_PIOWrite,
1750 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1751 };
1752 BYTE err;
1753
1754 D(bug("[ATA%02ld] ata_WriteMultiple32()\n", unit->au_UnitNum));
1755
1756 *act = 0;
1757 if (0 != (err = ata_exec_blk(unit, &acb)))
1758 return err;
1759
1760 *act = count << unit->au_SectorShift;
1761 return 0;
1762 }
1763
1764 static BYTE ata_WriteDMA32(struct ata_Unit *unit, ULONG block,
1765 ULONG count, APTR buffer, ULONG *act)
1766 {
1767 ata_CommandBlock acb =
1768 {
1769 ATA_WRITE_DMA,
1770 0,
1771 1,
1772 0,
1773 block,
1774 count,
1775 buffer,
1776 count << unit->au_SectorShift,
1777 0,
1778 CM_DMAWrite,
1779 (unit->au_Flags & AF_CHSOnly) ? CT_CHS : CT_LBA28,
1780 };
1781 BYTE err;
1782
1783 D(bug("[ATA%02ld] ata_WriteDMA32()\n", unit->au_UnitNum));
1784
1785 *act = 0;
1786 if (0 != (err = ata_exec_blk(unit, &acb)))
1787 return err;
1788
1789 *act = count << unit->au_SectorShift;
1790 return 0;
1791 }
1792
1793 /*
1794 * ata write64 commands
1795 */
1796 static BYTE ata_WriteSector64(struct ata_Unit *unit, UQUAD block,
1797 ULONG count, APTR buffer, ULONG *act)
1798 {
1799 ata_CommandBlock acb =
1800 {
1801 ATA_WRITE64,
1802 0,
1803 1,
1804 0,
1805 block,
1806 count,
1807 buffer,
1808 count << unit->au_SectorShift,
1809 0,
1810 CM_PIOWrite,
1811 CT_LBA48
1812 };
1813 BYTE err;
1814
1815 D(bug("[ATA%02ld] ata_WriteSector64()\n", unit->au_UnitNum));
1816
1817 *act = 0;
1818 if (0 != (err = ata_exec_blk(unit, &acb)))
1819 return err;
1820
1821 *act = count << unit->au_SectorShift;
1822 return 0;
1823 }
1824
1825 static BYTE ata_WriteMultiple64(struct ata_Unit *unit, UQUAD block,
1826 ULONG count, APTR buffer, ULONG *act)
1827 {
1828 ata_CommandBlock acb =
1829 {
1830 ATA_WRITE_MULTIPLE64,
1831 0,
1832 unit->au_Drive->id_RWMultipleSize & 0xff,
1833 0,
1834 block,
1835 count,
1836 buffer,
1837 count << unit->au_SectorShift,
1838 0,
1839 CM_PIOWrite,
1840 CT_LBA48
1841 };
1842 BYTE err;
1843
1844 D(bug("[ATA%02ld] ata_WriteMultiple64()\n", unit->au_UnitNum));
1845
1846 *act = 0;
1847 if (0 != (err = ata_exec_blk(unit, &acb)))
1848 return err;
1849
1850 *act = count << unit->au_SectorShift;
1851 return 0;
1852 }
1853
1854 static BYTE ata_WriteDMA64(struct ata_Unit *unit, UQUAD block,
1855 ULONG count, APTR buffer, ULONG *act)
1856 {
1857 ata_CommandBlock acb =
1858 {
1859 ATA_WRITE_DMA64,
1860 0,
1861 1,
1862 0,
1863 block,
1864 count,
1865 buffer,
1866 count << unit->au_SectorShift,
1867 0,
1868 CM_DMAWrite,
1869 CT_LBA48
1870 };
1871 BYTE err;
1872
1873 D(bug("[ATA%02ld] ata_WriteDMA64()\n", unit->au_UnitNum));
1874
1875 *act = 0;
1876 if (0 != (err = ata_exec_blk(unit, &acb)))
1877 return err;
1878
1879 *act = count << unit->au_SectorShift;
1880 return 0;
1881 }
1882
1883 /*
1884 * ata miscellaneous commands
1885 */
1886 static BYTE ata_Eject(struct ata_Unit *unit)
1887 {
1888 ata_CommandBlock acb =
1889 {
1890 ATA_MEDIA_EJECT,
1891 0,
1892 0,
1893 0,
1894 0,
1895 0,
1896 0,
1897 0,
1898 0,
1899 CM_NoData,
1900 CT_NoBlock
1901 };
1902
1903 D(bug("[ATA%02ld] ata_Eject()\n", unit->au_UnitNum));
1904
1905 return ata_exec_cmd(unit, &acb);
1906 }
1907
1908 /*
1909 * atapi commands
1910 */
1911 int atapi_TestUnitOK(struct ata_Unit *unit)
1912 {
1913 UBYTE cmd[6] = {
1914 0
1915 };
1916 UBYTE sense[16] = {
1917 0
1918 };
1919 struct SCSICmd sc = {
1920 0
1921 };
1922
1923 D(bug("[ATA%02ld] atapi_TestUnitOK()\n", unit->au_UnitNum));
1924
1925 sc.scsi_Command = (void*) &cmd;
1926 sc.scsi_CmdLength = sizeof(cmd);
1927 sc.scsi_SenseData = (void*)&sense;
1928 sc.scsi_SenseLength = sizeof(sense);
1929 sc.scsi_Flags = SCSIF_AUTOSENSE;
1930
1931 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Testing Unit Ready sense...\n", unit->au_UnitNum));
1932 unit->au_DirectSCSI(unit, &sc);
1933 unit->au_SenseKey = sense[2];
1934
1935 /*
1936 * we may have just lost the disc...?
1937 */
1938 /*
1939 * per MMC, drives are expected to return 02-3a-0# status, when disc is not present
1940 * that would translate into following code:
1941 * int p1 = ((sense[2] == 2) && (sense[12] == 0x3a)) ? 1 : 0;
1942 * unfortunately, it's what MMC says, not what vendors code.
1943 */
1944 int p1 = (sense[2] == 2) ? 1 : 0;
1945 int p2 = (0 != (AF_DiscPresent & unit->au_Flags)) ? 1 : 0;
1946
1947 if (p1 == p2)
1948 {
1949 //unit->au_Flags ^= AF_DiscPresent;
1950 if (p1 == 0)
1951 unit->au_Flags |= AF_DiscPresent;
1952 else
1953 unit->au_Flags &= ~AF_DiscPresent;
1954
1955 unit->au_Flags |= AF_DiscChanged;
1956 }
1957
1958 DATAPI(bug("[ATA%02ld] atapi_TestUnitOK: Test Unit Ready sense: %02lx, Media %s\n", unit->au_UnitNum, sense[2], unit->au_Flags & AF_DiscPresent ? "PRESENT" : "ABSENT"));
1959 return sense[2];
1960 }
1961
1962 static BYTE atapi_Read(struct ata_Unit *unit, ULONG block, ULONG count,
1963 APTR buffer, ULONG *act)
1964 {
1965 UBYTE cmd[] = {
1966 SCSI_READ10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
1967 };
1968 struct SCSICmd sc = {
1969 0
1970 };
1971
1972 D(bug("[ATA%02ld] atapi_Read()\n", unit->au_UnitNum));
1973
1974 sc.scsi_Command = (void*) &cmd;
1975 sc.scsi_CmdLength = sizeof(cmd);
1976 sc.scsi_Data = buffer;
1977 sc.scsi_Length = count << unit->au_SectorShift;
1978 sc.scsi_Flags = SCSIF_READ;
1979
1980 return unit->au_DirectSCSI(unit, &sc);
1981 }
1982
1983 static BYTE atapi_Write(struct ata_Unit *unit, ULONG block, ULONG count,
1984 APTR buffer, ULONG *act)
1985 {
1986 UBYTE cmd[] = {
1987 SCSI_WRITE10, 0, block>>24, block>>16, block>>8, block, 0, count>>8, count, 0
1988 };
1989 struct SCSICmd sc = {
1990 0
1991 };
1992
1993 D(bug("[ATA%02ld] atapi_Write()\n", unit->au_UnitNum));
1994
1995 sc.scsi_Command = (void*) &cmd;
1996 sc.scsi_CmdLength = sizeof(cmd);
1997 sc.scsi_Data = buffer;
1998 sc.scsi_Length = count << unit->au_SectorShift;
1999 sc.scsi_Flags = SCSIF_WRITE;
2000
2001 return unit->au_DirectSCSI(unit, &sc);
2002 }
2003
2004 static BYTE atapi_Eject(struct ata_Unit *unit)
2005 {
2006 struct atapi_StartStop cmd = {
2007 command: SCSI_STARTSTOP,
2008 immediate: 1,
2009 flags: ATAPI_SS_EJECT,
2010 };
2011
2012 struct SCSICmd sc = {
2013 0
2014 };
2015
2016 D(bug("[ATA%02ld] atapi_Eject()\n", unit->au_UnitNum));
2017
2018 sc.scsi_Command = (void*) &cmd;
2019 sc.scsi_CmdLength = sizeof(cmd);
2020 sc.scsi_Flags = SCSIF_READ;
2021
2022 return unit->au_DirectSCSI(unit, &sc);
2023 }
2024
2025 static ULONG atapi_RequestSense(struct ata_Unit* unit, UBYTE* sense,
2026 ULONG senselen)
2027 {
2028 UBYTE cmd[] = {
2029 3, 0, 0, 0, senselen & 0xfe, 0
2030 };
2031 struct SCSICmd sc = {
2032 0
2033 };
2034
2035 D(bug("[ATA%02ld] atapi_RequestSense()\n", unit->au_UnitNum));
2036
2037 if ((senselen == 0) || (sense == 0))
2038 {
2039 return 0;
2040 }
2041 sc.scsi_Data = (void*)sense;
2042 sc.scsi_Length = senselen & 0xfe;
2043 sc.scsi_Command = (void*)&cmd;
2044 sc.scsi_CmdLength = 6;
2045 sc.scsi_Flags = SCSIF_READ;
2046
2047 unit->au_DirectSCSI(unit, &sc);
2048
2049 DATAPI(dump(sense, senselen));
2050 DATAPI(bug("[SENSE] atapi_RequestSense: sensed data: %lx %lx %lx\n", sense[2]&0xf, sense[12], sense[13]));
2051 return ((sense[2]&0xf)<<16) | (sense[12]<<8) | (sense[13]);
2052 }
2053
2054 static ULONG ata_ReadSignature(struct ata_Bus *bus, int unit,
2055 BOOL *DiagExecuted)
2056 {
2057 UBYTE tmp1, tmp2;
2058
2059 D(bug("[ATA ] ata_ReadSignature(%02ld)\n", unit));
2060
2061 PIO_Out(bus, DEVHEAD_VAL | (unit << 4), ata_DevHead);
2062 ata_WaitNano(400, bus->ab_Base);
2063 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2064
2065 DINIT(bug("[ATA ] ata_ReadSignature: Status %02lx Device %02lx\n",
2066 ata_ReadStatus(bus), PIO_In(bus, ata_DevHead)));
2067
2068 /* Ok, ATA/ATAPI device. Get detailed signature */
2069 DINIT(bug("[ATA ] ata_ReadSignature: ATA[PI] device present. Attempting to detect specific subtype\n"));
2070
2071 tmp1 = PIO_In(bus, ata_LBAMid);
2072 tmp2 = PIO_In(bus, ata_LBAHigh);
2073
2074 DINIT(bug("[ATA ] ata_ReadSignature: Subtype check returned %02lx:%02lx (%04lx)\n", tmp1, tmp2, (tmp1 << 8) | tmp2));
2075
2076 switch ((tmp1 << 8) | tmp2)
2077 {
2078 case 0x14eb:
2079 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for ATAPI device\n"));
2080 return DEV_ATAPI;
2081
2082 case 0x3cc3:
2083 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATA device\n"));
2084 return DEV_SATA;
2085
2086 case 0x6996:
2087 DINIT(bug("[ATA ] ata_ReadSignature: Found signature for SATAPI device\n"));
2088 return DEV_SATAPI;
2089
2090 default:
2091 if (0 == (ata_ReadStatus(bus) & 0xfe)) {
2092 DINIT(bug("[ATA ] ata_ReadSignature: Found NONE\n"));
2093 return DEV_NONE;
2094 }
2095
2096 /* ATA_EXECUTE_DIAG is executed by both devices, do it only once */
2097 if (!*DiagExecuted)
2098 {
2099 DINIT(bug("[ATA ] ata_ReadSignature: ATA_EXECUTE_DIAG\n"));
2100 PIO_Out(bus, ATA_EXECUTE_DIAG, ata_Command);
2101 *DiagExecuted = TRUE;
2102 }
2103
2104 ata_WaitTO(bus->ab_Timer, 0, 2000, 0);
2105 while (ata_ReadStatus(bus) & ATAF_BUSY)
2106 ata_WaitNano(400, bus->ab_Base);
2107 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2108
2109 DINIT(bug("[ATA ] ata_ReadSignature: ATAF_BUSY wait finished\n"));
2110
2111 PIO_Out(bus, DEVHEAD_VAL | (unit << 4), ata_DevHead);
2112 do
2113 {
2114 ata_WaitNano(400, bus->ab_Base);
2115 //ata_WaitTO(unit->au_Bus->ab_Timer, 0, 1, 0);
2116 }
2117 while (0 != (ATAF_BUSY & ata_ReadStatus(bus)));
2118 DINIT(bug("[ATA ] ata_ReadSignature: Further validating ATA signature: %lx & 0x7f = 1, %lx & 0x10 = unit\n",
2119 PIO_In(bus, ata_Error), PIO_In(bus, ata_DevHead)));
2120
2121 if ((PIO_In(bus, ata_Error) & 0x7f) == 1)
2122 {
2123 DINIT(bug("[ATA ] ata_ReadSignature: Found *valid* signature for ATA device\n"));
2124 /* this might still be an (S)ATAPI device, but we correct that in ata_Identify */
2125 return DEV_ATA;
2126 }
2127 DERROR(bug("[ATA ] ata_ReadSignature: Found signature for ATA "
2128 "device, but further validation failed\n"));
2129 return DEV_NONE;
2130 }
2131 }
2132
2133 static void ata_ResetBus(struct ata_Bus *bus)
2134 {
2135 struct ataBase *ATABase = bus->ab_Base;
2136 OOP_Object *obj = OOP_OBJECT(ATABase->busClass, bus);
2137 ULONG TimeOut;
2138 BOOL DiagExecuted = FALSE;
2139 IPTR haveAltIO;
2140
2141 /*
2142 * Set and then reset the soft reset bit in the Device Control
2143 * register. This causes device 0 to be selected.
2144 */
2145 DINIT(bug("[ATA ] ata_ResetBus()\n"));
2146
2147 PIO_Out(bus, DEVHEAD_VAL, ata_DevHead); /* Select it never the less */
2148 ata_WaitNano(400, ATABase);
2149 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2150
2151 OOP_GetAttr(obj, aHidd_ATABus_UseIOAlt, &haveAltIO);
2152 if (haveAltIO)
2153 {
2154 PIO_OutAlt(bus, ATACTLF_RESET | ATACTLF_INT_DISABLE, ata_AltControl);
2155 ata_WaitTO(bus->ab_Timer, 0, 10, 0); /* sleep 10us; min: 5us */
2156
2157 PIO_OutAlt(bus, ATACTLF_INT_DISABLE, ata_AltControl);
2158 }
2159 else
2160 {
2161 PIO_Out(bus, ATA_EXECUTE_DIAG, ata_Command);
2162 }
2163 ata_WaitTO(bus->ab_Timer, 0, 20000, 0); /* sleep 20ms; min: 2ms */
2164
2165 /* If there is a device 0, wait for device 0 to clear BSY */
2166 if (DEV_NONE != bus->ab_Dev[0])
2167 {
2168 DINIT(bug("[ATA ] ata_ResetBus: Wait for master to clear BSY\n"));
2169 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2170
2171 while ( 1 )
2172 {
2173 if ((ata_ReadStatus(bus) & ATAF_BUSY) == 0)
2174 break;
2175 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2176 if (!(--TimeOut)) {
2177 DINIT(bug("[ATA%02ld] ata_ResetBus: Master device Timed Out!\n"));
2178 bus->ab_Dev[0] = DEV_NONE;
2179 break;
2180 }
2181 }
2182 DINIT(bug("[ATA ] ata_ResetBus: Wait left after %d ms\n", 1000 - TimeOut));
2183 }
2184
2185 /* If there is a device 1, wait some time until device 1 allows
2186 * register access, but fail only if BSY isn't cleared */
2187 if (DEV_NONE != bus->ab_Dev[1])
2188 {
2189 DINIT(bug("[ATA ] ata_ResetBus: Wait DEV1 to allow access\n"));
2190 PIO_Out(bus, DEVHEAD_VAL | (1 << 4), ata_DevHead);
2191 ata_WaitNano(400, bus->ab_Base);
2192 //ata_WaitTO(bus->ab_Timer, 0, 1, 0);
2193
2194 TimeOut = 50; /* Timeout 50ms (1ms x 50) */
2195 while ( 1 )
2196 {
2197 if ((PIO_In(bus, ata_Count) == 0x01) && (PIO_In(bus, ata_LBALow) == 0x01))
2198 break;
2199 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2200 if (!(--TimeOut))
2201 {
2202 DINIT(bug("[ATA ] ata_ResetBus: DEV1 1/2 TimeOut!\n"));
2203 break;
2204 }
2205 }
2206 DINIT(bug("[ATA ] ata_ResetBus: DEV1 1/2 Wait left after %d ms\n", 1000 - TimeOut));
2207
2208 DINIT(bug("[ATA ] ata_ResetBus: Wait for slave to clear BSY\n"));
2209 TimeOut = 1000; /* Timeout 1s (1ms x 1000) */
2210 while ( 1 )
2211 {
2212 if ((ata_ReadStatus(bus) & ATAF_BUSY) == 0)
2213 break;
2214 ata_WaitTO(bus->ab_Timer, 0, 1000, 0);
2215 if (!(--TimeOut)) {
2216 DINIT(bug("[ATA ] ata_ResetBus: Slave device Timed Out!\n"));
2217 bus->ab_Dev[1] = DEV_NONE;
2218 break;
2219 }
2220 }
2221 DINIT(bug("[ATA ] ata_ResetBus: Wait left after %d ms\n", 1000 - TimeOut));
2222 }
2223
2224 if (DEV_NONE != bus->ab_Dev[0])
2225 bus->ab_Dev[0] = ata_ReadSignature(bus, 0, &DiagExecuted);
2226 if (DEV_NONE != bus->ab_Dev[1])
2227 bus->ab_Dev[1] = ata_ReadSignature(bus, 1, &DiagExecuted);
2228 }
2229
2230 void ata_InitBus(struct ata_Bus *bus)
2231 {
2232 UBYTE tmp1, tmp2;
2233 UWORD i;
2234
2235 /*
2236 * initialize timer for the sake of scanning
2237 */
2238 bus->ab_Timer = ata_OpenTimer(bus->ab_Base);
2239
2240 DINIT(bug("[ATA ] ata_InitBus(%p)\n", bus));
2241
2242 bus->ab_Dev[0] = DEV_NONE;
2243 bus->ab_Dev[1] = DEV_NONE;
2244
2245 for (i = 0; i < MAX_BUSUNITS; i++)
2246 {
2247 /* Select device and disable IRQs */
2248 PIO_Out(bus, DEVHEAD_VAL | (i << 4), ata_DevHead);
2249 ata_WaitTO(bus->ab_Timer, 0, 400, 0);
2250 PIO_OutAlt(bus, ATACTLF_INT_DISABLE, ata_AltControl);
2251
2252 /* Write some pattern to registers */
2253 PIO_Out(bus, 0x55, ata_Count);
2254 PIO_Out(bus, 0xaa, ata_LBALow);
2255 PIO_Out(bus, 0xaa, ata_Count);
2256 PIO_Out(bus, 0x55, ata_LBALow);
2257 PIO_Out(bus, 0x55, ata_Count);
2258 PIO_Out(bus, 0xaa, ata_LBALow);
2259
2260 tmp1 = PIO_In(bus, ata_Count);
2261 tmp2 = PIO_In(bus, ata_LBALow);
2262 DB2(bug("[ATA ] ata_InitBus: Reply 0x%02X 0x%02X\n", tmp1, tmp2));
2263
2264 if ((tmp1 == 0x55) && (tmp2 == 0xaa))
2265 bus->ab_Dev[i] = DEV_UNKNOWN;
2266 DINIT(bug("[ATA ] ata_InitBus: Device type = 0x%02X\n", bus->ab_Dev[i]));
2267 }
2268
2269 ata_ResetBus(bus);
2270 ata_CloseTimer(bus->ab_Timer);
2271 DINIT(bug("[ATA ] ata_InitBus: Finished\n"));
2272 }
2273
2274 /*
2275 * not really sure what this is meant to be - TO BE REPLACED
2276 */
2277 static const ULONG ErrorMap[] = {
2278 CDERR_NotSpecified,
2279 CDERR_NoSecHdr,
2280 CDERR_NoDisk,
2281 CDERR_NoSecHdr,
2282 CDERR_NoSecHdr,
2283 CDERR_NOCMD,
2284 CDERR_NoDisk,
2285 CDERR_WriteProt,
2286 CDERR_NotSpecified,
2287 CDERR_NotSpecified,
2288 CDERR_NotSpecified,
2289 CDERR_ABORTED,
2290 CDERR_NotSpecified,
2291 CDERR_NotSpecified,
2292 CDERR_NoSecHdr,
2293 CDERR_NotSpecified,
2294 };
2295
2296 static BYTE atapi_EndCmd(struct ata_Unit *unit)
2297 {
2298 struct ata_Bus *bus = unit->au_Bus;
2299 UBYTE status;
2300
2301 DATAPI(bug("[ATA%02ld] atapi_EndCmd()\n", unit->au_UnitNum));
2302
2303 /*
2304 * read alternate status register (per specs)
2305 */
2306 status = PIO_InAlt(bus, ata_AltStatus);
2307 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Alternate status: %lx\n", unit->au_UnitNum, status));
2308
2309 status = PIO_In(bus, atapi_Status);
2310
2311 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Command complete. Status: %lx\n",
2312 unit->au_UnitNum, status));
2313
2314 if (!(status & ATAPIF_CHECK))
2315 {
2316 return 0;
2317 }
2318 else
2319 {
2320 status = PIO_In(bus, atapi_Error);
2321 DATAPI(bug("[ATA%02ld] atapi_EndCmd: Error code 0x%lx\n", unit->au_UnitNum, status >> 4));
2322 return ErrorMap[status >> 4];
2323 }
2324 }
Mirror of AROS' svn.