arch/arm-native/kernel/intr.c

   1 /*
   2     Copyright � 2013-2015, The AROS Development Team. All rights reserved.
   3     $Id$
   4 */
   5
   6 #include <inttypes.h>
   7 #include <aros/kernel.h>
   8 #include <aros/libcall.h>
   9 #include <hardware/intbits.h>
  10 #include <stddef.h>
  11 #include <string.h>
  12
  13 #include <proto/exec.h>
  14 #include <proto/kernel.h>
  15
  16 #include "kernel_cpu.h"
  17 #include "kernel_intern.h"
  18 #include "kernel_debug.h"
  19 #include "kernel_interrupts.h"
  20 #include "kernel_intr.h"
  21
  22 #define BOOT_STACK_SIZE         (256 << 2)
  23 #define BOOT_TAGS_SIZE          (128 << 3)
  24
  25 #define DREGS(x)
  26 #define DIRQ(x)
  27 #define D(x)
  28
  29 /* linker exports */
  30 extern void *__intvecs_start, *__intvecs_end;
  31 extern void __arm_halt(void);
  32
  33 void ictl_enable_irq(uint8_t irq, struct KernelBase *KernelBase)
  34 {
  35     if (__arm_arosintern.ARMI_IRQEnable)
  36         __arm_arosintern.ARMI_IRQEnable(irq);
  37 }
  38
  39 void ictl_disable_irq(uint8_t irq, struct KernelBase *KernelBase)
  40 {
  41     if (__arm_arosintern.ARMI_IRQDisable)
  42         __arm_arosintern.ARMI_IRQDisable(irq);
  43 }
  44
  45 asm (
  46     ".globl __arm_halt                         \n"
  47     ".type __arm_halt,%function                \n"
  48     "__arm_halt:                               \n"
  49     "           b       __arm_halt             \n"
  50     );
  51
  52 /*
  53     ** UNDEF INSTRUCTION EXCEPTION
  54     return addr = lr
  55     entered in UND mode.
  56 */
  57
  58 asm (
  59     ".set       MODE_SYSTEM, 0x1f              \n"
  60
  61     ".globl __vectorhand_undef                 \n"
  62     ".type __vectorhand_undef,%function        \n"
  63     "__vectorhand_undef:                       \n"
  64     VECTCOMMON_START
  65     "           bl      handle_undef           \n"
  66     VECTCOMMON_END
  67     );
  68
  69 void handle_undef(regs_t *regs)
  70 {
  71     bug("[Kernel] Trap ARM Undef Exception\n");
  72     bug("[Kernel]    exception #4 (Illegal instruction)\n");
  73     bug("[Kernel]    at 0x%p\n", regs[14]);
  74
  75     if (krnRunExceptionHandlers(KernelBase, 4, regs))
  76         return;
  77
  78     D(bug("[Kernel] exception handler(s) returned\n"));
  79
  80     if (core_Trap(4, regs))
  81     {
  82         D(bug("[Kernel] trap handler(s) returned\n"));
  83         return;
  84     }
  85
  86     bug("[Kernel] UNHANDLED EXCEPTION #4\n");
  87
  88     cpu_DumpRegs(regs);
  89
  90     __arm_halt();
  91 }
  92
  93 /*
  94     ** RESET HANDLER
  95     no return address,
  96     entered in SVC mode.
  97 */
  98
  99 asm (
 100     ".globl __vectorhand_reset                          \n"
 101     ".type __vectorhand_reset,%function                 \n"
 102     "__vectorhand_reset:                                \n"
 103     "           mov     sp, #0x1000 - 16                \n" // re-use bootstrap tmp stack
 104     "           sub     r0, sp, #" STR(BOOT_STACK_SIZE)"\n" // get the boottag's
 105     "           sub     r0, r0, #" STR(BOOT_TAGS_SIZE) "\n"
 106     "           mov     fp, #0                          \n" // clear fp
 107
 108     "           ldr     pc, 2f                          \n" // jump into kernel resource
 109     "1:         b       1b                              \n"
 110     "2:         .word   kernel_cstart                   \n"
 111     );
 112
 113
 114 /* ** SWI HANDLER ** */
 115
 116 /** SWI handled in syscall.c */
 117
 118 /*
 119     ** IRQ HANDLER
 120     return address = lr - 4
 121     entered in IRQ mode.
 122 */
 123
 124 asm (
 125     ".set       MODE_IRQ, 0x12                 \n"
 126     ".set       MODE_SUPERVISOR, 0x13          \n"
 127     ".set       MODE_SYSTEM, 0x1f              \n"
 128
 129     ".globl __vectorhand_irq                   \n"
 130     ".type __vectorhand_irq,%function          \n"
 131     "__vectorhand_irq:                         \n"
 132     "           sub     lr, lr, #4             \n" // adjust lr_irq
 133     VECTCOMMON_START
 134     "           bl      handle_irq             \n"
 135     "           mov     r0, sp                 \n"
 136     "           ldr     r1, [r0, #16*4]        \n" // load the spr register
 137     "           and     r1, r1, #31            \n" // mask processor mode
 138     "           cmp     r1, #0x10              \n" // will we go back to user mode?
 139     "           cmpne   r1, #0x1f              \n" // or system mode (falls we use it)
 140     "           bne     1f                     \n" // no? don't call core_ExitInterrupt!
 141     "           mov     fp, #0                 \n" // clear fp
 142     "           bl      core_ExitInterrupt     \n"
 143     "1:                                        \n"
 144     VECTCOMMON_END
 145     );
 146
 147 void handle_irq(regs_t *regs)
 148 {
 149     DIRQ(bug("[KRN] ## IRQ ##\n"));
 150
 151     DREGS(cpu_DumpRegs(regs));
 152
 153     if (__arm_arosintern.ARMI_IRQProcess)
 154         __arm_arosintern.ARMI_IRQProcess();
 155
 156     DIRQ(bug("[KRN] IRQ processing finished\n"));
 157
 158     return;
 159 }
 160
 161 /*
 162     ** FIQ HANDLER
 163     return address = lr -4
 164     entered in FIQ mode.
 165 */
 166
 167 __attribute__ ((interrupt ("FIQ"))) void __vectorhand_fiq(void)
 168 {
 169     DIRQ(bug("[KRN] ## FIQ ##\n"));
 170
 171     DIRQ(bug("[KRN] FIQ processing finished\n"));
 172
 173     return;
 174 }
 175
 176 /*
 177     ** DATA ABORT EXCEPTION
 178     return address = lr - 8
 179     entered in ABT mode.
 180 */
 181
 182 asm (
 183     ".set       MODE_SYSTEM, 0x1f              \n"
 184
 185     ".globl __vectorhand_dataabort             \n"
 186     ".type __vectorhand_dataabort,%function    \n"
 187     "__vectorhand_dataabort:                   \n"
 188     "           sub     lr, lr, #8             \n" // adjust lr_irq
 189     VECTCOMMON_START
 190     "           bl      handle_dataabort       \n"
 191     VECTCOMMON_END
 192     );
 193
 194 void handle_dataabort(regs_t *regs)
 195 {
 196     register unsigned int far;
 197
 198     // Read fault address register
 199     asm volatile("mrc p15, 0, %[far], c6, c0, 0": [far] "=r" (far) );
 200
 201     bug("[Kernel] Trap ARM Data Abort Exception\n");
 202     bug("[Kernel]    exception #2 (Bus Error)\n");
 203     bug("[Kernel]    attempt to access 0x%p from 0x%p\n", far, regs->lr);
 204
 205     cpu_DumpRegs(regs);
 206
 207     if (krnRunExceptionHandlers(KernelBase, 2, regs))
 208         return;
 209
 210     D(bug("[Kernel] exception handler(s) returned\n"));
 211
 212     if (core_Trap(2, regs))
 213     {
 214         D(bug("[Kernel] trap handler(s) returned\n"));
 215         return;
 216     }
 217
 218     bug("[Kernel] UNHANDLED EXCEPTION #2\n");
 219
 220     cpu_DumpRegs(regs);
 221
 222     __arm_halt();
 223 }
 224
 225 /*
 226     ** PREFETCH ABORT EXCEPTION
 227     return address = lr - 4
 228     entered in ABT mode.
 229 */
 230
 231 asm (
 232     ".set       MODE_SYSTEM, 0x1f              \n"
 233
 234     ".globl __vectorhand_prefetchabort         \n"
 235     ".type __vectorhand_prefetchabort,%function \n"
 236     "__vectorhand_prefetchabort:               \n"
 237     "           sub     lr, lr, #4             \n" // adjust lr_irq
 238     VECTCOMMON_START
 239
 240     "           bl      handle_prefetchabort   \n"
 241
 242     VECTCOMMON_END
 243     );
 244
 245 void handle_prefetchabort(regs_t *regs)
 246 {
 247     bug("[Kernel] Trap ARM Prefetch Abort Exception\n");
 248     bug("[Kernel]    exception #3 (Address Error)\n");
 249     bug("[Kernel]    at 0x%p\n", regs->lr);
 250
 251     cpu_DumpRegs(regs);
 252
 253     if (krnRunExceptionHandlers(KernelBase, 3, regs))
 254         return;
 255
 256     D(bug("[Kernel] exception handler(s) returned\n"));
 257
 258     if (core_Trap(3, regs))
 259     {
 260         D(bug("[Kernel] trap handler(s) returned\n"));
 261         return;
 262     }
 263
 264     bug("[Kernel] UNHANDLED EXCEPTION #3\n");
 265
 266     cpu_DumpRegs(regs);
 267
 268     __arm_halt();
 269 }
 270
 271
 272 /* ** SETUP ** */
 273
 274 void arm_flush_cache(uint32_t addr, uint32_t length)
 275 {
 276     while (length)
 277     {
 278         __asm__ __volatile__("mcr p15, 0, %0, c7, c14, 1"::"r"(addr));
 279         addr += 32;
 280         length -= 32;
 281     }
 282     __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(addr));
 283 }
 284
 285 void arm_icache_invalidate(uint32_t addr, uint32_t length)
 286 {
 287     while (length)
 288     {
 289         __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 1"::"r"(addr));
 290         addr += 32;
 291         length -= 32;
 292     }
 293     __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4"::"r"(addr));
 294 }
 295
 296 void core_SetupIntr(void)
 297 {
 298     int irq;
 299     bug("[KRN] Initializing cpu vectors\n");
 300
 301     /* Copy vectors into place */
 302     memcpy(0, &__intvecs_start,
 303             (unsigned int)&__intvecs_end -
 304             (unsigned int)&__intvecs_start);
 305
 306     arm_flush_cache(0, 1024);
 307     arm_icache_invalidate(0, 1024);
 308
 309     D(bug("[KRN] Copied %d bytes from 0x%p to 0x00000000\n", (unsigned int)&__intvecs_end - (unsigned int)&__intvecs_start, &__intvecs_start));
 310
 311     D(
 312         unsigned int x = 0;
 313         bug("[KRN]: Vector dump-:");
 314         for (x=0; x < (unsigned int)&__intvecs_end - (unsigned int)&__intvecs_start; x++) {
 315             if ((x%16) == 0)
 316             {
 317                 bug("\n[KRN]:     %08x:", x);
 318             }
 319             bug(" %02x", *((volatile UBYTE *)x));
 320         }
 321         bug("\n");
 322     )
 323
 324     if (__arm_arosintern.ARMI_IRQInit)
 325         __arm_arosintern.ARMI_IRQInit();
 326 }