tests/soc_simple_display/test.v

   1 `default_nettype none
   2 `timescale 1ns/1ns
   3
   4 `include "messages.vh"
   5
   6 `ifndef SIMULATION
   7  `error_SIMULATION_not_defined
   8 ; /* Cause syntax error */
   9 `endif
  10
  11 `ifndef ROM_WORDS_COUNT
  12  `error_ROM_WORDS_COUNT_must_be_defined
  13 ; /* Cause syntax error */
  14 `endif
  15
  16 module soc_test();
  17    wire [9:0] image_writes;
  18
  19    reg        clock_100mhz;
  20    reg        reset;
  21
  22    wire       led1;
  23    wire       led2;
  24
  25    soc_with_peripherals
  26      #(
  27        .FONT_FILE("../../design/font.mem"),
  28        .EMBEDDED_ROM_WORDS_COUNT(`ROM_WORDS_COUNT),
  29        .EMBEDDED_ROM_FILE("instructions.mem")
  30        ) soc
  31        (
  32         .clock_100mhz(clock_100mhz),
  33
  34         .button1(!reset),
  35         .button2(1'b1),
  36
  37         .led1(led1),
  38         .led2(led2),
  39
  40         .image_writes(image_writes)
  41         );
  42
  43    integer     i;
  44
  45    initial begin
  46       reset <= 1;
  47       clock_100mhz <= 0;
  48
  49       for (i = 0; i < 5_000_000; i++) begin
  50          #5;
  51
  52          if (clock_100mhz)
  53            reset <= 0;
  54
  55          clock_100mhz <= ~clock_100mhz;
  56       end
  57
  58       if (led1)
  59         `MSG(("error: stack machine in soc hasn't finished working in 25ms"));
  60       else
  61         `MSG(("error: nothing got displayed in 25ms"));
  62    end
  63
  64    always @ (image_writes) begin
  65       if (image_writes)
  66         $finish;
  67    end
  68 endmodule // soc_test