sdram_master.v

   1 `include "sdram_master_defines.v"
   2 /*
   3 hl.ren.pub@gmail.com
   4 */
   5
   6
   7 module sdram_master(
   8         // signals to connect to an Avalon clock source interface
   9         clk,
  10         reset,
  11
  12         // signals to connect to an Avalon-MM slave interface
  13         avs_s1_chipselect,
  14         avs_s1_address,
  15         avs_s1_read,
  16         avs_s1_write,
  17         avs_s1_readdata,
  18         avs_s1_writedata,
  19         avs_s1_byteenable,
  20         avs_s1_waitrequest,
  21
  22         // read master port interface
  23         avm_read_address,
  24         avm_read_read,
  25         //avm_read_byteenable,
  26         avm_read_readdata,
  27         avm_read_waitrequest,
  28
  29         // write master port interface
  30         avm_write_address,
  31         avm_write_write,
  32         //avm_write_byteenable,
  33         avm_write_writedata,
  34         avm_write_waitrequest
  35
  36         );
  37
  38 input   clk;
  39 input   reset;
  40 input   avs_s1_chipselect;
  41 input   [2:0]   avs_s1_address;
  42 input   avs_s1_read;
  43 output  reg [31:0]      avs_s1_readdata;
  44 input   avs_s1_write;
  45 input   [31:0]  avs_s1_writedata;
  46 input   [3:0]   avs_s1_byteenable;
  47 output  avs_s1_waitrequest;
  48
  49         // read master port interface
  50 output  reg     [31:0]  avm_read_address;
  51 output  reg     avm_read_read;
  52 //output        reg     [3:0]   avm_read_byteenable;
  53 //input [31:0]  avm_read_readdata;
  54 input   [15:0]  avm_read_readdata;
  55 input   avm_read_waitrequest;
  56
  57         // write master port interface
  58 output  reg     [31:0]  avm_write_address;
  59 output  reg     avm_write_write;
  60 //output        reg     [3:0]   avm_write_byteenable;
  61 //output        reg     [31:0]  avm_write_writedata;
  62 output  reg     [15:0]  avm_write_writedata;
  63 input   avm_write_waitrequest;
  64
  65 reg     [31:0]  S_addr;//source address
  66 reg     [31:0]  D_addr;//destination  address
  67 reg     [31:0]  Longth;
  68
  69 reg     Status;
  70
  71 //reg   [31:0]  DMA_DATA;
  72 reg     [15:0]  DMA_DATA;
  73
  74 reg     [31:0]  DMA_Cont;
  75
  76 reg     avs_s1_read_last;
  77 always@(posedge clk)
  78 begin
  79         avs_s1_read_last <= avs_s1_read;
  80 end
  81
  82 wire    avs_s1_waitrequest;
  83 assign  avs_s1_waitrequest = ~(avs_s1_read_last | avs_s1_write);
  84
  85 //read and write regs
  86 always@(posedge clk or posedge reset)
  87 begin
  88                 if(reset) begin
  89                         S_addr          <= 32'h0;
  90                         D_addr          <= 32'h0;
  91                         Longth          <= 32'h0;
  92                 end
  93                 else    begin
  94                         if((avs_s1_chipselect==1'b1) && (avs_s1_write==1'b1)) begin
  95                                 case(avs_s1_address)
  96                                         `S_ADDR:                        S_addr          <= avs_s1_writedata;
  97                                         `D_ADDR:                        D_addr          <= avs_s1_writedata;
  98                                         `LONGTH:                        Longth          <= avs_s1_writedata;
  99                                 endcase
 100                         end
 101                         else    begin
 102                                 if((avs_s1_chipselect==1'b1) && (avs_s1_read==1'b1)) begin
 103                                         case(avs_s1_address)
 104                                                 `S_ADDR:                        avs_s1_readdata <= S_addr;
 105                                                 `D_ADDR:                        avs_s1_readdata <= D_addr;
 106                                                 `LONGTH:                        avs_s1_readdata <= Longth;
 107                                                 `STATUS_ADDR:   avs_s1_readdata <= {31'h0,Status};
 108                                                 default:                        avs_s1_readdata <= 32'h0;
 109                                         endcase
 110                                 end
 111                         end
 112                 end
 113 end
 114
 115
 116 //start signal
 117 reg     start;
 118 always@(posedge clk or posedge reset)
 119 begin
 120         if(reset)
 121                 start           <= 1'b0;
 122         else    if((avs_s1_chipselect==1'b1) & (avs_s1_write==1'b1) & (avs_s1_address == `START_ADDR))
 123                                 start   <= 1'b1;
 124                         else start      <= 1'b0;
 125 end
 126
 127 //status signal
 128 reg     done;
 129 reg done_last;
 130 always@(posedge clk)
 131 begin
 132         if(reset)       done_last               <= 1'b0;
 133         else            done_last               <= done;
 134 end
 135
 136
 137 always@(posedge clk)
 138 begin
 139         if(reset)
 140         begin
 141                 Status <= 1'b0;
 142         end
 143         else    if((avs_s1_chipselect==1'b1) &  (avs_s1_write==1'b1)  & (avs_s1_address == `START_ADDR) )
 144                         begin
 145                                 Status <= 1'b0;
 146                         end
 147                         else    if( (done_last == 1'b0 )&( done == 1'b1) )
 148                                         begin
 149                                                 Status <= 1'b1;
 150                                         end
 151 end
 152
 153 //FSM
 154
 155 reg     [5:0]   DMA_state;
 156
 157 parameter       DMA_IDLE                                =       0;
 158 parameter       READ                                    =       1;
 159 parameter       WAIT_READ                               =       2;
 160 parameter       WRITE                           =       3;
 161 parameter       WAIT_WRITE                      =       4;
 162 parameter       CALC_NEXT                               =       5;
 163 parameter       DMA_DONE                                =       6;
 164
 165 always@(posedge clk)
 166 begin
 167         if(reset) begin
 168                 DMA_state <= DMA_IDLE;
 169                 DMA_Cont        <= 32'h0;
 170         end
 171         else begin
 172                 case(DMA_state)
 173                         DMA_IDLE: begin
 174                                 DMA_Cont <= 32'h0;
 175                                 done                            <= 1'b0;
 176                                 if(start)
 177                                         DMA_state               <= READ;
 178                         end
 179                         READ: begin
 180                                 avm_read_address <= S_addr + DMA_Cont;
 181                                 //avm_read_byteenable <= 4'b0001;
 182                                 avm_read_read <= 1'b1;
 183                                 DMA_state       <= WAIT_READ;
 184                         end
 185                         WAIT_READ: begin
 186                                 if(avm_read_waitrequest == 1'b0 )
 187                                 begin
 188                                         avm_read_read <= 1'b0;
 189                                         DMA_DATA <= avm_read_readdata;
 190                                         DMA_state <= WRITE;
 191                                 end
 192                         end
 193                         WRITE: begin
 194                                 avm_write_address <= D_addr + DMA_Cont;
 195                                 //avm_write_byteenable <= 4'b0001;
 196                                 avm_write_write <= 1'b1;
 197                                 avm_write_writedata <= DMA_DATA;
 198                                 //avm_write_writedata <= DMA_Cont;//temp test
 199                                 DMA_state <= WAIT_WRITE;
 200                         end
 201                         WAIT_WRITE: begin
 202                                 if(avm_write_waitrequest == 1'b0 )
 203                                         begin
 204                                                 DMA_Cont <= DMA_Cont + 32'h2;
 205                                                 //avm_write_address <= 0;
 206                                                 avm_write_write <= 1'b0;
 207                                                 if(DMA_Cont < Longth)
 208                                                         DMA_state <= READ;
 209                                                 else
 210                                                         DMA_state <= DMA_DONE;
 211
 212                                         end
 213                         end
 214                         DMA_DONE: begin
 215                                 done <= 1'b1;
 216                                 DMA_state <= DMA_IDLE;
 217                         end
 218                         default: begin
 219                                 DMA_state <= DMA_IDLE;
 220                         end
 221                 endcase
 222         end
 223 end
 224 endmodule