pal.h

   1 /* Common definitions for QEMU Emulation PALcode
   2
   3    Copyright (C) 2011 Richard Henderson
   4
   5    This file is part of QEMU PALcode.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
  15    of the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef PAL_H
  22 #define PAL_H 1
  23
  24 /* General Purpose Registers.  */
  25 #define v0      $0
  26 #define t0      $1
  27 #define t1      $2
  28 #define t2      $3
  29 #define t3      $4
  30 #define t4      $5
  31 #define t5      $6
  32 #define a0      $16
  33 #define a1      $17
  34 #define a2      $18
  35 #define a3      $19
  36 #define a4      $20
  37 #define a5      $21
  38 #define t8      $22
  39 #define t9      $23
  40 #define t10     $24
  41
  42 /* PALcode Shadow Registers.  These registers are swapped out when
  43    QEMU is in PALmode.  Unlike real hardware, there is no enable bit.
  44    However, also unlike real hardware, the originals can be accessed
  45    via MTPR/MFPR.  */
  46 #define p0      $8
  47 #define p1      $9
  48 #define p2      $10
  49 #define p3      $11
  50 #define p4      $12
  51 #define p5      $13
  52 #define p6      $14             // Used to save exc_addr for machine check
  53 #define p7      $25
  54
  55 /* QEMU Processor Registers.  */
  56 #define qemu_ps         0
  57 #define qemu_fen        1
  58 #define qemu_pcc_ofs    2
  59 #define qemu_trap_arg0  3
  60 #define qemu_trap_arg1  4
  61 #define qemu_trap_arg2  5
  62 #define qemu_exc_addr   6
  63 #define qemu_palbr      7
  64 #define qemu_ptbr       8
  65 #define qemu_vptptr     9
  66 #define qemu_unique     10
  67 #define qemu_sysval     11
  68 #define qemu_usp        12
  69
  70 #define qemu_shadow0    32
  71 #define qemu_shadow1    33
  72 #define qemu_shadow2    34
  73 #define qemu_shadow3    35
  74 #define qemu_shadow4    36
  75 #define qemu_shadow5    37
  76 #define qemu_shadow6    38
  77 #define qemu_shadow7    39
  78
  79 /* PALcode Processor Register Private Storage.  */
  80 #define pt0             40
  81 #define pt1             41
  82 #define pt2             42
  83 #define pt3             43
  84 #define pt4             44
  85 #define pt5             45
  86 #define pt6             46
  87 #define pt7             47
  88 #define pt8             48
  89 #define pt9             49
  90 #define pt10            50
  91 #define pt11            51
  92 #define pt12            52
  93 #define pt13            53
  94 #define pt14            54
  95 #define pt15            55
  96 #define pt16            56
  97 #define pt17            57
  98 #define pt18            58
  99 #define pt19            59
 100 #define pt20            60
 101 #define pt21            61
 102 #define pt22            62
 103 #define pt23            63
 104
 105 /* QEMU function calls, via mtpr.  */
 106 #define qemu_tbia       255
 107 #define qemu_tbis       254
 108 #define qemu_wait       253
 109 #define qemu_halt       252
 110 #define qemu_alarm      251
 111 #define qemu_walltime   250
 112 #define qemu_vmtime     249
 113
 114 /* PALcode uses of the private storage slots.  */
 115 #define ptEntUna        pt0
 116 #define ptEntIF         pt1
 117 #define ptEntSys        pt2
 118 #define ptEntInt        pt3
 119 #define ptEntArith      pt4
 120 #define ptEntMM         pt5
 121 #define ptMces          pt6
 122 #define ptKsp           pt7
 123 #define ptKgp           pt8
 124 #define ptPcbb          pt9
 125 #define ptPgp           pt10
 126 #define ptMisc          pt11
 127 #define ptMchk0         pt12
 128 #define ptMchk1         pt13
 129 #define ptMchk2         pt14
 130 #define ptMchk3         pt15
 131 #define ptMchk4         pt16
 132 #define ptMchk5         pt17
 133 #define ptSys0          pt18
 134 #define ptSys1          pt19
 135
 136 /*
 137  * Shortcuts for various PALmode instructions.
 138  */
 139 #define mtpr    hw_mtpr
 140 #define mfpr    hw_mfpr
 141 #define stq_p   hw_stq/p
 142 #define stl_p   hw_stl/p
 143 #define ldl_p   hw_ldl/p
 144 #define ldq_p   hw_ldq/p
 145
 146 /* QEMU recognizes the EV4/EV5 HW_REI instruction as a special case of
 147    the EV6 HW_RET instruction.  This pulls the destination address from
 148    the EXC_ADDR processor register.  */
 149 #define hw_rei  hw_ret ($31)
 150
 151
 152 .macro  ENDFN   function
 153         .type   \function, @function
 154         .size   \function, . - \function
 155 .endm
 156
 157 #endif /* PAL_H */