core-cia.h

   1 /* Memory layout and register descriptions for the CIA/PYXIS chipset.
   2
   3    Copyright (C) 2011 Richard Henderson
   4
   5    This file is part of QEMU PALcode.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 2 of the License or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the text
  15    of the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING.  If not see
  19    <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef CIA_H
  22 #define CIA_H
  23
  24 #define IDENT_ADDR 0xfffffc0000000000UL
  25
  26 #define CIA_MEM_R1_MASK 0x1fffffff  /* SPARSE Mem region 1 mask is 29 bits */
  27 #define CIA_MEM_R2_MASK 0x07ffffff  /* SPARSE Mem region 2 mask is 27 bits */
  28 #define CIA_MEM_R3_MASK 0x03ffffff  /* SPARSE Mem region 3 mask is 26 bits */
  29
  30 /*
  31  * 21171-CA Control and Status Registers
  32  */
  33 #define CIA_IOC_CIA_REV                 (IDENT_ADDR + 0x8740000080UL)
  34 #  define CIA_REV_MASK                  0xff
  35 #define CIA_IOC_PCI_LAT                 (IDENT_ADDR + 0x87400000C0UL)
  36 #define CIA_IOC_CIA_CTRL                (IDENT_ADDR + 0x8740000100UL)
  37 #  define CIA_CTRL_PCI_EN               (1 << 0)
  38 #  define CIA_CTRL_PCI_LOCK_EN          (1 << 1)
  39 #  define CIA_CTRL_PCI_LOOP_EN          (1 << 2)
  40 #  define CIA_CTRL_FST_BB_EN            (1 << 3)
  41 #  define CIA_CTRL_PCI_MST_EN           (1 << 4)
  42 #  define CIA_CTRL_PCI_MEM_EN           (1 << 5)
  43 #  define CIA_CTRL_PCI_REQ64_EN         (1 << 6)
  44 #  define CIA_CTRL_PCI_ACK64_EN         (1 << 7)
  45 #  define CIA_CTRL_ADDR_PE_EN           (1 << 8)
  46 #  define CIA_CTRL_PERR_EN              (1 << 9)
  47 #  define CIA_CTRL_FILL_ERR_EN          (1 << 10)
  48 #  define CIA_CTRL_MCHK_ERR_EN          (1 << 11)
  49 #  define CIA_CTRL_ECC_CHK_EN           (1 << 12)
  50 #  define CIA_CTRL_ASSERT_IDLE_BC       (1 << 13)
  51 #  define CIA_CTRL_COM_IDLE_BC          (1 << 14)
  52 #  define CIA_CTRL_CSR_IOA_BYPASS       (1 << 15)
  53 #  define CIA_CTRL_IO_FLUSHREQ_EN       (1 << 16)
  54 #  define CIA_CTRL_CPU_FLUSHREQ_EN      (1 << 17)
  55 #  define CIA_CTRL_ARB_CPU_EN           (1 << 18)
  56 #  define CIA_CTRL_EN_ARB_LINK          (1 << 19)
  57 #  define CIA_CTRL_RD_TYPE_SHIFT        20
  58 #  define CIA_CTRL_RL_TYPE_SHIFT        24
  59 #  define CIA_CTRL_RM_TYPE_SHIFT        28
  60 #  define CIA_CTRL_EN_DMA_RD_PERF       (1 << 31)
  61 #define CIA_IOC_CIA_CNFG                (IDENT_ADDR + 0x8740000140UL)
  62 #  define CIA_CNFG_IOA_BWEN             (1 << 0)
  63 #  define CIA_CNFG_PCI_MWEN             (1 << 4)
  64 #  define CIA_CNFG_PCI_DWEN             (1 << 5)
  65 #  define CIA_CNFG_PCI_WLEN             (1 << 8)
  66 #define CIA_IOC_FLASH_CTRL              (IDENT_ADDR + 0x8740000200UL)
  67 #define CIA_IOC_HAE_MEM                 (IDENT_ADDR + 0x8740000400UL)
  68 #define CIA_IOC_HAE_IO                  (IDENT_ADDR + 0x8740000440UL)
  69 #define CIA_IOC_CFG                     (IDENT_ADDR + 0x8740000480UL)
  70 #define CIA_IOC_CACK_EN                 (IDENT_ADDR + 0x8740000600UL)
  71 #  define CIA_CACK_EN_LOCK_EN           (1 << 0)
  72 #  define CIA_CACK_EN_MB_EN             (1 << 1)
  73 #  define CIA_CACK_EN_SET_DIRTY_EN      (1 << 2)
  74 #  define CIA_CACK_EN_BC_VICTIM_EN      (1 << 3)
  75
  76
  77 /*
  78  * 21171-CA Diagnostic Registers
  79  */
  80 #define CIA_IOC_CIA_DIAG                (IDENT_ADDR + 0x8740002000UL)
  81 #define CIA_IOC_DIAG_CHECK              (IDENT_ADDR + 0x8740003000UL)
  82
  83 /*
  84  * 21171-CA Performance Monitor registers
  85  */
  86 #define CIA_IOC_PERF_MONITOR            (IDENT_ADDR + 0x8740004000UL)
  87 #define CIA_IOC_PERF_CONTROL            (IDENT_ADDR + 0x8740004040UL)
  88
  89 /*
  90  * 21171-CA Error registers
  91  */
  92 #define CIA_IOC_CPU_ERR0                (IDENT_ADDR + 0x8740008000UL)
  93 #define CIA_IOC_CPU_ERR1                (IDENT_ADDR + 0x8740008040UL)
  94 #define CIA_IOC_CIA_ERR                 (IDENT_ADDR + 0x8740008200UL)
  95 #  define CIA_ERR_COR_ERR               (1 << 0)
  96 #  define CIA_ERR_UN_COR_ERR            (1 << 1)
  97 #  define CIA_ERR_CPU_PE                (1 << 2)
  98 #  define CIA_ERR_MEM_NEM               (1 << 3)
  99 #  define CIA_ERR_PCI_SERR              (1 << 4)
 100 #  define CIA_ERR_PERR                  (1 << 5)
 101 #  define CIA_ERR_PCI_ADDR_PE           (1 << 6)
 102 #  define CIA_ERR_RCVD_MAS_ABT          (1 << 7)
 103 #  define CIA_ERR_RCVD_TAR_ABT          (1 << 8)
 104 #  define CIA_ERR_PA_PTE_INV            (1 << 9)
 105 #  define CIA_ERR_FROM_WRT_ERR          (1 << 10)
 106 #  define CIA_ERR_IOA_TIMEOUT           (1 << 11)
 107 #  define CIA_ERR_LOST_CORR_ERR         (1 << 16)
 108 #  define CIA_ERR_LOST_UN_CORR_ERR      (1 << 17)
 109 #  define CIA_ERR_LOST_CPU_PE           (1 << 18)
 110 #  define CIA_ERR_LOST_MEM_NEM          (1 << 19)
 111 #  define CIA_ERR_LOST_PERR             (1 << 21)
 112 #  define CIA_ERR_LOST_PCI_ADDR_PE      (1 << 22)
 113 #  define CIA_ERR_LOST_RCVD_MAS_ABT     (1 << 23)
 114 #  define CIA_ERR_LOST_RCVD_TAR_ABT     (1 << 24)
 115 #  define CIA_ERR_LOST_PA_PTE_INV       (1 << 25)
 116 #  define CIA_ERR_LOST_FROM_WRT_ERR     (1 << 26)
 117 #  define CIA_ERR_LOST_IOA_TIMEOUT      (1 << 27)
 118 #  define CIA_ERR_VALID                 (1 << 31)
 119 #define CIA_IOC_CIA_STAT                (IDENT_ADDR + 0x8740008240UL)
 120 #define CIA_IOC_ERR_MASK                (IDENT_ADDR + 0x8740008280UL)
 121 #define CIA_IOC_CIA_SYN                 (IDENT_ADDR + 0x8740008300UL)
 122 #define CIA_IOC_MEM_ERR0                (IDENT_ADDR + 0x8740008400UL)
 123 #define CIA_IOC_MEM_ERR1                (IDENT_ADDR + 0x8740008440UL)
 124 #define CIA_IOC_PCI_ERR0                (IDENT_ADDR + 0x8740008800UL)
 125 #define CIA_IOC_PCI_ERR1                (IDENT_ADDR + 0x8740008840UL)
 126 #define CIA_IOC_PCI_ERR3                (IDENT_ADDR + 0x8740008880UL)
 127
 128 /*
 129  * 21171-CA System configuration registers
 130  */
 131 #define CIA_IOC_MCR                     (IDENT_ADDR + 0x8750000000UL)
 132 #define CIA_IOC_MBA0                    (IDENT_ADDR + 0x8750000600UL)
 133 #define CIA_IOC_MBA2                    (IDENT_ADDR + 0x8750000680UL)
 134 #define CIA_IOC_MBA4                    (IDENT_ADDR + 0x8750000700UL)
 135 #define CIA_IOC_MBA6                    (IDENT_ADDR + 0x8750000780UL)
 136 #define CIA_IOC_MBA8                    (IDENT_ADDR + 0x8750000800UL)
 137 #define CIA_IOC_MBAA                    (IDENT_ADDR + 0x8750000880UL)
 138 #define CIA_IOC_MBAC                    (IDENT_ADDR + 0x8750000900UL)
 139 #define CIA_IOC_MBAE                    (IDENT_ADDR + 0x8750000980UL)
 140 #define CIA_IOC_TMG0                    (IDENT_ADDR + 0x8750000B00UL)
 141 #define CIA_IOC_TMG1                    (IDENT_ADDR + 0x8750000B40UL)
 142 #define CIA_IOC_TMG2                    (IDENT_ADDR + 0x8750000B80UL)
 143
 144 /*
 145  * 2117A-CA PCI Address and Scatter-Gather Registers.
 146  */
 147 #define CIA_IOC_PCI_TBIA                (IDENT_ADDR + 0x8760000100UL)
 148
 149 #define CIA_IOC_PCI_W0_BASE             (IDENT_ADDR + 0x8760000400UL)
 150 #define CIA_IOC_PCI_W0_MASK             (IDENT_ADDR + 0x8760000440UL)
 151 #define CIA_IOC_PCI_T0_BASE             (IDENT_ADDR + 0x8760000480UL)
 152
 153 #define CIA_IOC_PCI_W1_BASE             (IDENT_ADDR + 0x8760000500UL)
 154 #define CIA_IOC_PCI_W1_MASK             (IDENT_ADDR + 0x8760000540UL)
 155 #define CIA_IOC_PCI_T1_BASE             (IDENT_ADDR + 0x8760000580UL)
 156
 157 #define CIA_IOC_PCI_W2_BASE             (IDENT_ADDR + 0x8760000600UL)
 158 #define CIA_IOC_PCI_W2_MASK             (IDENT_ADDR + 0x8760000640UL)
 159 #define CIA_IOC_PCI_T2_BASE             (IDENT_ADDR + 0x8760000680UL)
 160
 161 #define CIA_IOC_PCI_W3_BASE             (IDENT_ADDR + 0x8760000700UL)
 162 #define CIA_IOC_PCI_W3_MASK             (IDENT_ADDR + 0x8760000740UL)
 163 #define CIA_IOC_PCI_T3_BASE             (IDENT_ADDR + 0x8760000780UL)
 164
 165 #define CIA_IOC_PCI_Wn_BASE(N)  (IDENT_ADDR + 0x8760000400UL + (N)*0x100)
 166 #define CIA_IOC_PCI_Wn_MASK(N)  (IDENT_ADDR + 0x8760000440UL + (N)*0x100)
 167 #define CIA_IOC_PCI_Tn_BASE(N)  (IDENT_ADDR + 0x8760000480UL + (N)*0x100)
 168
 169 #define CIA_IOC_PCI_W_DAC               (IDENT_ADDR + 0x87600007C0UL)
 170
 171 /*
 172  * 2117A-CA Address Translation Registers.
 173  */
 174
 175 /* 8 tag registers, the first 4 of which are lockable.  */
 176 #define CIA_IOC_TB_TAGn(n) \
 177         (IDENT_ADDR + 0x8760000800UL + (n)*0x40)
 178
 179 /* 4 page registers per tag register.  */
 180 #define CIA_IOC_TBn_PAGEm(n,m) \
 181         (IDENT_ADDR + 0x8760001000UL + (n)*0x100 + (m)*0x40)
 182
 183 /*
 184  * Memory spaces:
 185  */
 186 #define CIA_IACK_SC                     (IDENT_ADDR + 0x8720000000UL)
 187 #define CIA_CONF                        (IDENT_ADDR + 0x8700000000UL)
 188 #define CIA_IO                          (IDENT_ADDR + 0x8580000000UL)
 189 #define CIA_SPARSE_MEM                  (IDENT_ADDR + 0x8000000000UL)
 190 #define CIA_SPARSE_MEM_R2               (IDENT_ADDR + 0x8400000000UL)
 191 #define CIA_SPARSE_MEM_R3               (IDENT_ADDR + 0x8500000000UL)
 192 #define CIA_DENSE_MEM                   (IDENT_ADDR + 0x8600000000UL)
 193 #define CIA_BW_MEM                      (IDENT_ADDR + 0x8800000000UL)
 194 #define CIA_BW_IO                       (IDENT_ADDR + 0x8900000000UL)
 195 #define CIA_BW_CFG_0                    (IDENT_ADDR + 0x8a00000000UL)
 196 #define CIA_BW_CFG_1                    (IDENT_ADDR + 0x8b00000000UL)
 197
 198 /*
 199  * ALCOR's GRU ASIC registers
 200  */
 201 #define GRU_INT_REQ                     (IDENT_ADDR + 0x8780000000UL)
 202 #define GRU_INT_MASK                    (IDENT_ADDR + 0x8780000040UL)
 203 #define GRU_INT_EDGE                    (IDENT_ADDR + 0x8780000080UL)
 204 #define GRU_INT_HILO                    (IDENT_ADDR + 0x87800000C0UL)
 205 #define GRU_INT_CLEAR                   (IDENT_ADDR + 0x8780000100UL)
 206
 207 #define GRU_CACHE_CNFG                  (IDENT_ADDR + 0x8780000200UL)
 208 #define GRU_SCR                         (IDENT_ADDR + 0x8780000300UL)
 209 #define GRU_LED                         (IDENT_ADDR + 0x8780000800UL)
 210 #define GRU_RESET                       (IDENT_ADDR + 0x8780000900UL)
 211
 212 #define ALCOR_GRU_INT_REQ_BITS          0x800fffffUL
 213 #define XLT_GRU_INT_REQ_BITS            0x80003fffUL
 214 #define GRU_INT_REQ_BITS                (alpha_mv.sys.cia.gru_int_req_bits+0)
 215
 216 /*
 217  * PYXIS interrupt control registers
 218  */
 219 #define PYXIS_INT_REQ                   (IDENT_ADDR + 0x87A0000000UL)
 220 #define PYXIS_INT_MASK                  (IDENT_ADDR + 0x87A0000040UL)
 221 #define PYXIS_INT_HILO                  (IDENT_ADDR + 0x87A00000C0UL)
 222 #define PYXIS_INT_ROUTE                 (IDENT_ADDR + 0x87A0000140UL)
 223 #define PYXIS_GPO                       (IDENT_ADDR + 0x87A0000180UL)
 224 #define PYXIS_INT_CNFG                  (IDENT_ADDR + 0x87A00001C0UL)
 225 #define PYXIS_RT_COUNT                  (IDENT_ADDR + 0x87A0000200UL)
 226 #define PYXIS_INT_TIME                  (IDENT_ADDR + 0x87A0000240UL)
 227 #define PYXIS_IIC_CTRL                  (IDENT_ADDR + 0x87A00002C0UL)
 228 #define PYXIS_RESET                     (IDENT_ADDR + 0x8780000900UL)
 229
 230 /* Offset between ram physical addresses and pci64 DAC bus addresses.  */
 231 #define PYXIS_DAC_OFFSET                (1UL << 40)
 232
 233 #ifdef __ASSEMBLER__
 234
 235 /* Unfortunately, GAS doesn't attempt any interesting constructions of
 236    64-bit constants, dropping them all into the .lit8 section.  It is
 237    better for us to build these by hand.  */
 238 .macro  LOAD_PHYS_PYXIS_INT ret
 239         lda     \ret, 0x87a
 240         sll     \ret, 28, \ret
 241 .endm
 242
 243 .macro  LOAD_KSEG_PCI_IO ret
 244         lda     \ret, -887
 245         sll     \ret, 32, \ret
 246 .endm
 247
 248 .macro  SYS_WHAMI       ret
 249         mov     0, \ret
 250 .endm
 251
 252 .macro  SYS_ACK_SMP     t0, t1, t2
 253         br      MchkBugCheck
 254 .endm
 255
 256 #else
 257
 258 static inline unsigned long inb(unsigned long port)
 259 {
 260   return *(volatile unsigned char *)(CIA_BW_IO + port);
 261 }
 262
 263 static inline void outb(unsigned long port, unsigned char val)
 264 {
 265   *(volatile unsigned char *)(CIA_BW_IO + port) = val;
 266 }
 267
 268
 269 #endif
 270
 271 #endif /* CIA_H */