| blob | dfc8661ecc91ab250772774316d6796eb92d2b0e |
1 From 95b0363f57ca13c9421204b735926f4a99e2d844 Mon Sep 17 00:00:00 2001
2 From: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
3 Date: Fri, 15 Aug 2008 01:55:54 +0300
4 Subject: [PATCH 05/10] TI DSP BRIDGE: Hardware Interfaces
6 Initial port from omapzoom
7 http://omapzoom.org/gf/project/omapbridge
9 For details,
10 http://omapzoom.org/gf/project/omapbridge/docman/?subdir=3
12 Signed-off-by: Hiroshi DOYU <Hiroshi.DOYU@nokia.com>
13 ---
14 drivers/dsp/bridge/hw/EasiBase.h | 179 +++++++++
15 drivers/dsp/bridge/hw/EasiGlobal.h | 42 +++
16 drivers/dsp/bridge/hw/GlobalTypes.h | 328 +++++++++++++++++
17 drivers/dsp/bridge/hw/IPIAccInt.h | 41 ++
18 drivers/dsp/bridge/hw/IVA2RegAcM.h | 28 ++
19 drivers/dsp/bridge/hw/MLBAccInt.h | 132 +++++++
20 drivers/dsp/bridge/hw/MLBRegAcM.h | 200 ++++++++++
21 drivers/dsp/bridge/hw/MMUAccInt.h | 79 ++++
22 drivers/dsp/bridge/hw/MMURegAcM.h | 267 ++++++++++++++
23 drivers/dsp/bridge/hw/PRCMAccInt.h | 300 +++++++++++++++
24 drivers/dsp/bridge/hw/PRCMRegAcM.h | 669 ++++++++++++++++++++++++++++++++++
25 drivers/dsp/bridge/hw/hw_defs.h | 73 ++++
26 drivers/dsp/bridge/hw/hw_dspssC64P.c | 55 +++
27 drivers/dsp/bridge/hw/hw_dspssC64P.h | 48 +++
28 drivers/dsp/bridge/hw/hw_mbox.c | 255 +++++++++++++
29 drivers/dsp/bridge/hw/hw_mbox.h | 358 ++++++++++++++++++
30 drivers/dsp/bridge/hw/hw_mmu.c | 607 ++++++++++++++++++++++++++++++
31 drivers/dsp/bridge/hw/hw_mmu.h | 178 +++++++++
32 drivers/dsp/bridge/hw/hw_prcm.c | 167 +++++++++
33 drivers/dsp/bridge/hw/hw_prcm.h | 168 +++++++++
34 20 files changed, 4174 insertions(+), 0 deletions(-)
35 create mode 100644 drivers/dsp/bridge/hw/EasiBase.h
36 create mode 100644 drivers/dsp/bridge/hw/EasiGlobal.h
37 create mode 100644 drivers/dsp/bridge/hw/GlobalTypes.h
38 create mode 100644 drivers/dsp/bridge/hw/IPIAccInt.h
39 create mode 100644 drivers/dsp/bridge/hw/IVA2RegAcM.h
40 create mode 100644 drivers/dsp/bridge/hw/MLBAccInt.h
41 create mode 100644 drivers/dsp/bridge/hw/MLBRegAcM.h
42 create mode 100644 drivers/dsp/bridge/hw/MMUAccInt.h
43 create mode 100644 drivers/dsp/bridge/hw/MMURegAcM.h
44 create mode 100644 drivers/dsp/bridge/hw/PRCMAccInt.h
45 create mode 100644 drivers/dsp/bridge/hw/PRCMRegAcM.h
46 create mode 100644 drivers/dsp/bridge/hw/hw_defs.h
47 create mode 100644 drivers/dsp/bridge/hw/hw_dspssC64P.c
48 create mode 100644 drivers/dsp/bridge/hw/hw_dspssC64P.h
49 create mode 100644 drivers/dsp/bridge/hw/hw_mbox.c
50 create mode 100644 drivers/dsp/bridge/hw/hw_mbox.h
51 create mode 100644 drivers/dsp/bridge/hw/hw_mmu.c
52 create mode 100644 drivers/dsp/bridge/hw/hw_mmu.h
53 create mode 100644 drivers/dsp/bridge/hw/hw_prcm.c
54 create mode 100644 drivers/dsp/bridge/hw/hw_prcm.h
56 Index: lk/drivers/dsp/bridge/hw/EasiBase.h
57 ===================================================================
58 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
59 +++ lk/drivers/dsp/bridge/hw/EasiBase.h 2008-08-18 10:38:36.000000000 +0300
60 @@ -0,0 +1,179 @@
61 +/*
62 + * linux/drivers/dsp/bridge/hw/omap3/inc/EasiBase.h
63 + *
64 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
65 + *
66 + * Copyright (C) 2007 Texas Instruments, Inc.
67 + *
68 + * This package is free software; you can redistribute it and/or modify
69 + * it under the terms of the GNU General Public License version 2 as
70 + * published by the Free Software Foundation.
71 + *
72 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
73 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
74 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
75 + */
76 +
77 +#ifndef __EASIBASE_H
78 +#define __EASIBASE_H
79 +
80 +/* ----------------------------------------------------------------------------
81 +* DEFINE: ****_BASE_ID
82 +*
83 +* DESCRIPTION: These are registser BASE IDs that will be used to identify
84 +* errors when doing the EASI-Checker register tests
85 +*
86 +* NOTE: The values of these defines will be defined at a later stage.
87 +* TBD
88 +*
89 +* -----------------------------------------------------------------------------
90 +*/
91 +
92 +#define OSPL1_BASE_ID 0
93 +#define D3D1_BASE_ID 0
94 +#define MBSP1_BASE_ID 0
95 +#define MBSP2_BASE_ID 0
96 +#define MSDI1_BASE_ID 0
97 +#define RNG1_BASE_ID 0
98 +#define SHAM1_BASE_ID 0
99 +#define RFBI1_BASE_ID 0
100 +#define DISC1_BASE_ID 0
101 +#define DSS1_BASE_ID 0
102 +#define MLB1_BASE_ID 0
103 +#define IPI1_BASE_ID 0
104 +#define PDMA1_BASE_ID 0
105 +#define PRCM_BASE_ID 0
106 +#define SDMA1_BASE_ID 0
107 +#define SDRC1_BASE_ID 0
108 +#define ST1_BASE_ID 0
109 +#define SMS1_BASE_ID 0
110 +#define WDT1_BASE_ID 0
111 +#define WDT2_BASE_ID 0
112 +#define WDT3_BASE_ID 0
113 +#define WDT4_BASE_ID 0
114 +#define INTC1_BASE_ID 0
115 +#define INTC2_BASE_ID 0
116 +#define MMU1_BASE_ID 0
117 +#define GPMC1_BASE_ID 0
118 +#define GPT1_BASE_ID 0
119 +#define GPT2_BASE_ID 0
120 +#define GPT3_BASE_ID 0
121 +#define GPT4_BASE_ID 0
122 +#define GPT5_BASE_ID 0
123 +#define GPT6_BASE_ID 0
124 +#define GPT7_BASE_ID 0
125 +#define GPT8_BASE_ID 0
126 +#define GPT9_BASE_ID 0
127 +#define GPT10_BASE_ID 0
128 +#define GPT11_BASE_ID 0
129 +#define GPT12_BASE_ID 0
130 +#define WTR1_BASE_ID 0
131 +#define WTR2_BASE_ID 0
132 +#define WTR3_BASE_ID 0
133 +#define WTR4_BASE_ID 0
134 +#define I2C1_BASE_ID 0
135 +#define I2C2_BASE_ID 0
136 +#define T32K1_BASE_ID 0
137 +#define PRCM1_BASE_ID 0
138 +
139 +#define AES1_BASE_ID 0
140 +#define C2CF1_BASE_ID 0
141 +#define DSPF1_BASE_ID 0
142 +#define FAC1_BASE_ID 0
143 +#define GPMF1_BASE_ID 0
144 +#define GPIO1_BASE_ID 0
145 +#define GPIO2_BASE_ID 0
146 +#define GPIO3_BASE_ID 0
147 +#define GPIO4_BASE_ID 0
148 +#define HDQW1_BASE_ID 0
149 +#define PKA1_BASE_ID 0
150 +
151 +#define IM1_BASE_ID 0
152 +#define IM2_BASE_ID 0
153 +#define IM3_BASE_ID 0
154 +#define IM4_BASE_ID 0
155 +#define IM5_BASE_ID 0
156 +#define IM6_BASE_ID 0
157 +#define IM7_BASE_ID 0
158 +#define IM8_BASE_ID 0
159 +#define IMA1_BASE_ID 0
160 +#define IMTM1_BASE_ID 0
161 +#define IVAF1_BASE_ID 0
162 +#define LRCR1_BASE_ID 0
163 +#define LRCR2_BASE_ID 0
164 +#define LRCS1_BASE_ID 0
165 +#define LRCS2_BASE_ID 0
166 +#define RAMF1_BASE_ID 0
167 +#define ROMF1_BASE_ID 0
168 +#define TM1_BASE_ID 0
169 +#define TML1_BASE_ID 0
170 +#define TML2_BASE_ID 0
171 +#define TML3_BASE_ID 0
172 +#define TML4_BASE_ID 0
173 +#define TML5_BASE_ID 0
174 +#define TML6_BASE_ID 0
175 +
176 +
177 +
178 +/* ----------------------------------------------------------------------------
179 +* DEFINE: ***_BASE_EASIL1
180 +*
181 +* DESCRIPTION: These are registser BASE EASIl1 numbers that can be used to
182 +* identify what EASI C functions have been called.
183 +*
184 +* NOTE: The values of these defines will be defined at a later stage.
185 +* TBD
186 +*
187 +* -----------------------------------------------------------------------------
188 +*/
189 +
190 +#define OSPL1_BASE_EASIL1 0
191 +#define D3D_BASE_EASIL1 0
192 +#define MBSP_BASE_EASIL1 0
193 +#define MSDI_BASE_EASIL1 0
194 +#define RNG_BASE_EASIL1 0
195 +#define SHAM_BASE_EASIL1 0
196 +#define RFBI_BASE_EASIL1 0
197 +#define DISC_BASE_EASIL1 0
198 +#define DSS_BASE_EASIL1 0
199 +#define MLB_BASE_EASIL1 0
200 +#define IPI_BASE_EASIL1 0
201 +#define PDMA_BASE_EASIL1 0
202 +#define SDMA_BASE_EASIL1 0
203 +#define SDRC_BASE_EASIL1 0
204 +#define ST_BASE_EASIL1 0
205 +#define SMS_BASE_EASIL1 0
206 +#define WDT1_BASE_EASIL1 0
207 +#define INTC1_BASE_EASIL1 0
208 +#define INTC2_BASE_EASIL1 0
209 +#define MMU1_BASE_EASIL1 0
210 +#define GPMC_BASE_EASIL1 0
211 +#define GPT_BASE_EASIL1 0
212 +#define WTR_BASE_EASIL1 0
213 +#define MBSP2_BASE_EASIL1 0
214 +#define I2C1_BASE_EASIL1 0
215 +#define I2C2_BASE_EASIL1 0
216 +#define T32K1_BASE_EASIL1 0
217 +#define PRCM1_BASE_EASIL1 0
218 +
219 +#define AES1_BASE_EASIL1 0
220 +#define C2CF1_BASE_EASIL1 0
221 +#define DSPF1_BASE_EASIL1 0
222 +#define FAC1_BASE_EASIL1 0
223 +#define GPMF1_BASE_EASIL1 0
224 +#define GPIO1_BASE_EASIL1 0
225 +#define HDQW1_BASE_EASIL1 0
226 +#define PKA1_BASE_EASIL1 0
227 +
228 +#define IMA_BASE_EASIL1 0
229 +#define IM_BASE_EASIL1 0
230 +#define IMTM_BASE_EASIL1 0
231 +#define IVAF_BASE_EASIL1 0
232 +#define LRCR_BASE_EASIL1 0
233 +#define LRCS_BASE_EASIL1 0
234 +#define RAMF_BASE_EASIL1 0
235 +#define ROMF_BASE_EASIL1 0
236 +#define TML_BASE_EASIL1 0
237 +#define TM_BASE_EASIL1 0
238 +
239 +#endif /* __EASIBASE_H */
240 Index: lk/drivers/dsp/bridge/hw/EasiGlobal.h
241 ===================================================================
242 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
243 +++ lk/drivers/dsp/bridge/hw/EasiGlobal.h 2008-08-18 10:38:36.000000000 +0300
244 @@ -0,0 +1,42 @@
245 +/*
246 + * linux/drivers/dsp/bridge/hw/omap3/inc/EasiGlobal.h
247 + *
248 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
249 + *
250 + * Copyright (C) 2007 Texas Instruments, Inc.
251 + *
252 + * This package is free software; you can redistribute it and/or modify
253 + * it under the terms of the GNU General Public License version 2 as
254 + * published by the Free Software Foundation.
255 + *
256 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
257 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
258 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
259 + */
260 +
261 +#ifndef __EASIGLOBAL_H
262 +#define __EASIGLOBAL_H
263 +#include <linux/types.h>
264 +
265 +/*
266 + * DEFINE: READ_ONLY, WRITE_ONLY & READ_WRITE
267 + *
268 + * DESCRIPTION: Defines used to describe register types for EASI-checker tests.
269 + */
270 +
271 +#define READ_ONLY 1
272 +#define WRITE_ONLY 2
273 +#define READ_WRITE 3
274 +
275 +/*
276 + * MACRO: _DEBUG_LEVEL_1_EASI
277 + *
278 + * DESCRIPTION: A MACRO which can be used to indicate that a particular beach
279 + * register access function was called.
280 + *
281 + * NOTE: We currently dont use this functionality.
282 + */
283 +#define _DEBUG_LEVEL_1_EASI(easiNum) ((void)0)
284 +
285 +#endif /* __EASIGLOBAL_H */
286 +
287 Index: lk/drivers/dsp/bridge/hw/GlobalTypes.h
288 ===================================================================
289 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
290 +++ lk/drivers/dsp/bridge/hw/GlobalTypes.h 2008-08-18 10:38:36.000000000 +0300
291 @@ -0,0 +1,328 @@
292 +/*
293 + * linux/drivers/dsp/bridge/hw/omap3/inc/GlobalTypes.h
294 + *
295 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
296 + *
297 + * Copyright (C) 2007 Texas Instruments, Inc.
298 + *
299 + * This package is free software; you can redistribute it and/or modify
300 + * it under the terms of the GNU General Public License version 2 as
301 + * published by the Free Software Foundation.
302 + *
303 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
304 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
305 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
306 + */
307 +
308 +
309 +/*
310 + * ======== GlobalTypes.h ========
311 + * Description:
312 + * Global HW definitions
313 + *
314 + *! Revision History:
315 + *! ================
316 + *! 16 Feb 2003 sb: Initial version
317 + */
318 +#ifndef __GLOBALTYPES_H
319 +#define __GLOBALTYPES_H
320 +
321 +/*
322 + * Definition: TRUE, FALSE
323 + *
324 + * DESCRIPTION: Boolean Definitions
325 + */
326 +#ifndef TRUE
327 +#define FALSE 0
328 +#define TRUE (!(FALSE))
329 +#endif
330 +
331 +/*
332 + * Definition: NULL
333 + *
334 + * DESCRIPTION: Invalid pointer
335 + */
336 +#ifndef NULL
337 +#define NULL (void *)0
338 +#endif
339 +
340 +/*
341 + * Definition: RET_CODE_BASE
342 + *
343 + * DESCRIPTION: Base value for return code offsets
344 + */
345 +#define RET_CODE_BASE 0
346 +
347 +/*
348 + * Definition: *BIT_OFFSET
349 + *
350 + * DESCRIPTION: offset in bytes from start of 32-bit word.
351 + */
352 +#define LOWER_16BIT_OFFSET 0
353 +#define UPPER_16BIT_OFFSET 2
354 +
355 +#define LOWER_8BIT_OFFSET 0
356 +#define LOWER_MIDDLE_8BIT_OFFSET 1
357 +#define UPPER_MIDDLE_8BIT_OFFSET 2
358 +#define UPPER_8BIT_OFFSET 3
359 +
360 +#define LOWER_8BIT_OF16_OFFSET 0
361 +#define UPPER_8BIT_OF16_OFFSET 1
362 +
363 +/*
364 + * Definition: *BIT_SHIFT
365 + *
366 + * DESCRIPTION: offset in bits from start of 32-bit word.
367 + */
368 +#define LOWER_16BIT_SHIFT 0
369 +#define UPPER_16BIT_SHIFT 16
370 +
371 +#define LOWER_8BIT_SHIFT 0
372 +#define LOWER_MIDDLE_8BIT_SHIFT 8
373 +#define UPPER_MIDDLE_8BIT_SHIFT 16
374 +#define UPPER_8BIT_SHIFT 24
375 +
376 +#define LOWER_8BIT_OF16_SHIFT 0
377 +#define UPPER_8BIT_OF16_SHIFT 8
378 +
379 +
380 +/*
381 + * Definition: LOWER_16BIT_MASK
382 + *
383 + * DESCRIPTION: 16 bit mask used for inclusion of lower 16 bits i.e. mask out
384 + * the upper 16 bits
385 + */
386 +#define LOWER_16BIT_MASK 0x0000FFFF
387 +
388 +
389 +/*
390 + * Definition: LOWER_8BIT_MASK
391 + *
392 + * DESCRIPTION: 8 bit masks used for inclusion of 8 bits i.e. mask out
393 + * the upper 16 bits
394 + */
395 +#define LOWER_8BIT_MASK 0x000000FF
396 +
397 +/*
398 + * Definition: RETURN_32BITS_FROM_16LOWER_AND_16UPPER(lower16Bits, upper16Bits)
399 + *
400 + * DESCRIPTION: Returns a 32 bit value given a 16 bit lower value and a 16
401 + * bit upper value
402 + */
403 +#define RETURN_32BITS_FROM_16LOWER_AND_16UPPER(lower16Bits,upper16Bits)\
404 + (((((u32)lower16Bits) & LOWER_16BIT_MASK)) | \
405 + (((((u32)upper16Bits) & LOWER_16BIT_MASK) << UPPER_16BIT_SHIFT)))
406 +
407 +/*
408 + * Definition: RETURN_16BITS_FROM_8LOWER_AND_8UPPER(lower16Bits, upper16Bits)
409 + *
410 + * DESCRIPTION: Returns a 16 bit value given a 8 bit lower value and a 8
411 + * bit upper value
412 + */
413 +#define RETURN_16BITS_FROM_8LOWER_AND_8UPPER(lower8Bits,upper8Bits)\
414 + (((((u32)lower8Bits) & LOWER_8BIT_MASK)) | \
415 + (((((u32)upper8Bits) & LOWER_8BIT_MASK) << UPPER_8BIT_OF16_SHIFT)))
416 +
417 +/*
418 + * Definition: RETURN_32BITS_FROM_4_8BIT_VALUES(lower8Bits, lowerMiddle8Bits,
419 + * lowerUpper8Bits, upper8Bits)
420 + *
421 + * DESCRIPTION: Returns a 32 bit value given four 8 bit values
422 + */
423 +#define RETURN_32BITS_FROM_4_8BIT_VALUES(lower8Bits, lowerMiddle8Bits,\
424 + lowerUpper8Bits, upper8Bits)\
425 + (((((u32)lower8Bits) & LOWER_8BIT_MASK)) | \
426 + (((((u32)lowerMiddle8Bits) & LOWER_8BIT_MASK) <<\
427 + LOWER_MIDDLE_8BIT_SHIFT)) | \
428 + (((((u32)lowerUpper8Bits) & LOWER_8BIT_MASK) <<\
429 + UPPER_MIDDLE_8BIT_SHIFT)) | \
430 + (((((u32)upper8Bits) & LOWER_8BIT_MASK) <<\
431 + UPPER_8BIT_SHIFT)))
432 +
433 +/*
434 + * Definition: READ_LOWER_16BITS_OF_32(value32bits)
435 + *
436 + * DESCRIPTION: Returns a 16 lower bits of 32bit value
437 + */
438 +#define READ_LOWER_16BITS_OF_32(value32bits)\
439 + ((u16)((u32)(value32bits) & LOWER_16BIT_MASK))
440 +
441 +/*
442 + * Definition: READ_UPPER_16BITS_OF_32(value32bits)
443 + *
444 + * DESCRIPTION: Returns a 16 lower bits of 32bit value
445 + */
446 +#define READ_UPPER_16BITS_OF_32(value32bits)\
447 + (((u16)((u32)(value32bits) >> UPPER_16BIT_SHIFT)) &\
448 + LOWER_16BIT_MASK)
449 +
450 +
451 +/*
452 + * Definition: READ_LOWER_8BITS_OF_32(value32bits)
453 + *
454 + * DESCRIPTION: Returns a 8 lower bits of 32bit value
455 + */
456 +#define READ_LOWER_8BITS_OF_32(value32bits)\
457 + ((u8)((u32)(value32bits) & LOWER_8BIT_MASK))
458 +
459 +/*
460 + * Definition: READ_LOWER_MIDDLE_8BITS_OF_32(value32bits)
461 + *
462 + * DESCRIPTION: Returns a 8 lower middle bits of 32bit value
463 + */
464 +#define READ_LOWER_MIDDLE_8BITS_OF_32(value32bits)\
465 + (((u8)((u32)(value32bits) >> LOWER_MIDDLE_8BIT_SHIFT)) &\
466 + LOWER_8BIT_MASK)
467 +
468 +/*
469 + * Definition: READ_LOWER_MIDDLE_8BITS_OF_32(value32bits)
470 + *
471 + * DESCRIPTION: Returns a 8 lower middle bits of 32bit value
472 + */
473 +#define READ_UPPER_MIDDLE_8BITS_OF_32(value32bits)\
474 + (((u8)((u32)(value32bits) >> LOWER_MIDDLE_8BIT_SHIFT)) &\
475 + LOWER_8BIT_MASK)
476 +
477 +/*
478 + * Definition: READ_UPPER_8BITS_OF_32(value32bits)
479 + *
480 + * DESCRIPTION: Returns a 8 upper bits of 32bit value
481 + */
482 +#define READ_UPPER_8BITS_OF_32(value32bits)\
483 + (((u8)((u32)(value32bits) >> UPPER_8BIT_SHIFT)) & LOWER_8BIT_MASK)
484 +
485 +
486 +/*
487 + * Definition: READ_LOWER_8BITS_OF_16(value16bits)
488 + *
489 + * DESCRIPTION: Returns a 8 lower bits of 16bit value
490 + */
491 +#define READ_LOWER_8BITS_OF_16(value16bits)\
492 + ((u8)((u16)(value16bits) & LOWER_8BIT_MASK))
493 +
494 +/*
495 + * Definition: READ_UPPER_8BITS_OF_16(value32bits)
496 + *
497 + * DESCRIPTION: Returns a 8 upper bits of 16bit value
498 + */
499 +#define READ_UPPER_8BITS_OF_16(value16bits)\
500 + (((u8)((u32)(value16bits) >> UPPER_8BIT_SHIFT)) & LOWER_8BIT_MASK)
501 +
502 +/* 8 bit tpyes */
503 +typedef signed char WORD8;
504 +
505 +/* UWORD16: 16 bit tpyes */
506 +
507 +
508 +/* REG_UWORD8, REG_WORD8: 8 bit register types */
509 +typedef volatile unsigned char REG_UWORD8;
510 +typedef volatile signed char REG_WORD8;
511 +
512 +/* REG_UWORD16, REG_WORD16: 16 bit register types */
513 +#ifndef OMAPBRIDGE_TYPES
514 +typedef volatile unsigned short REG_UWORD16;
515 +#endif
516 +typedef volatile short REG_WORD16;
517 +
518 +/* REG_UWORD32, REG_WORD32: 32 bit register types */
519 +typedef volatile unsigned long REG_UWORD32;
520 +
521 +/* FLOAT
522 + *
523 + * Type to be used for floating point calculation. Note that floating point
524 + * calculation is very CPU expensive, and you should only use if you
525 + * absolutely need this. */
526 +#ifndef OMAPBRIDGE_TYPES
527 +typedef float FLOAT;
528 +#endif
529 +
530 +/* boolean_t: Boolean Type True, False */
531 +/* ReturnCode_t: Return codes to be returned by all library functions */
532 +typedef enum ReturnCode_label {
533 + RET_OK = 0,
534 + RET_FAIL = -1,
535 + RET_BAD_NULL_PARAM = -2,
536 + RET_PARAM_OUT_OF_RANGE = -3,
537 + RET_INVALID_ID = -4,
538 + RET_EMPTY = -5,
539 + RET_FULL = -6,
540 + RET_TIMEOUT = -7,
541 + RET_INVALID_OPERATION = -8,
542 +
543 + /* Add new error codes at end of above list */
544 +
545 + RET_NUM_RET_CODES /* this should ALWAYS be LAST entry */
546 +} ReturnCode_t, *pReturnCode_t;
547 +
548 +/* MACRO: RD_MEM_8, WR_MEM_8
549 + *
550 + * DESCRIPTION: 32 bit memory access macros
551 + */
552 +#define RD_MEM_8(addr) ((u8)(*((u8 *)(addr))))
553 +#define WR_MEM_8(addr, data) (*((u8 *)(addr)) = (u8)(data))
554 +
555 +/* MACRO: RD_MEM_8_VOLATILE, WR_MEM_8_VOLATILE
556 + *
557 + * DESCRIPTION: 8 bit register access macros
558 + */
559 +#define RD_MEM_8_VOLATILE(addr) ((u8)(*((REG_UWORD8 *)(addr))))
560 +#define WR_MEM_8_VOLATILE(addr, data) (*((REG_UWORD8 *)(addr)) = (u8)(data))
561 +
562 +
563 +/*
564 + * MACRO: RD_MEM_16, WR_MEM_16
565 + *
566 + * DESCRIPTION: 16 bit memory access macros
567 + */
568 +#define RD_MEM_16(addr) ((u16)(*((u16 *)(addr))))
569 +#define WR_MEM_16(addr, data) (*((u16 *)(addr)) = (u16)(data))
570 +
571 +/*
572 + * MACRO: RD_MEM_16_VOLATILE, WR_MEM_16_VOLATILE
573 + *
574 + * DESCRIPTION: 16 bit register access macros
575 + */
576 +#define RD_MEM_16_VOLATILE(addr) ((u16)(*((REG_UWORD16 *)(addr))))
577 +#define WR_MEM_16_VOLATILE(addr, data) (*((REG_UWORD16 *)(addr)) =\
578 + (u16)(data))
579 +
580 +/*
581 + * MACRO: RD_MEM_32, WR_MEM_32
582 + *
583 + * DESCRIPTION: 32 bit memory access macros
584 + */
585 +#define RD_MEM_32(addr) ((u32)(*((u32 *)(addr))))
586 +#define WR_MEM_32(addr, data) (*((u32 *)(addr)) = (u32)(data))
587 +
588 +/*
589 + * MACRO: RD_MEM_32_VOLATILE, WR_MEM_32_VOLATILE
590 + *
591 + * DESCRIPTION: 32 bit register access macros
592 + */
593 +#define RD_MEM_32_VOLATILE(addr) ((u32)(*((REG_UWORD32 *)(addr))))
594 +#define WR_MEM_32_VOLATILE(addr, data) (*((REG_UWORD32 *)(addr)) =\
595 + (u32)(data))
596 +
597 +/* Not sure if this all belongs here */
598 +
599 +#define CHECK_RETURN_VALUE(actualValue, expectedValue, returnCodeIfMismatch,\
600 + spyCodeIfMisMatch)
601 +#define CHECK_RETURN_VALUE_RET(actualValue, expectedValue, returnCodeIfMismatch)
602 +#define CHECK_RETURN_VALUE_RES(actualValue, expectedValue, spyCodeIfMisMatch)
603 +#define CHECK_RETURN_VALUE_RET_VOID(actualValue, expectedValue,\
604 + spyCodeIfMisMatch)
605 +
606 +#define CHECK_INPUT_PARAM(actualValue, invalidValue, returnCodeIfMismatch,\
607 + spyCodeIfMisMatch)
608 +#define CHECK_INPUT_PARAM_NO_SPY(actualValue, invalidValue,\
609 + returnCodeIfMismatch)
610 +#define CHECK_INPUT_RANGE(actualValue, minValidValue, maxValidValue,\
611 + returnCodeIfMismatch, spyCodeIfMisMatch)
612 +#define CHECK_INPUT_RANGE_NO_SPY(actualValue, minValidValue, maxValidValue,\
613 + returnCodeIfMismatch)
614 +#define CHECK_INPUT_RANGE_MIN0(actualValue, maxValidValue,\
615 + returnCodeIfMismatch, spyCodeIfMisMatch)
616 +#define CHECK_INPUT_RANGE_NO_SPY_MIN0(actualValue, maxValidValue,\
617 + returnCodeIfMismatch)
618 +
619 +#endif /* __GLOBALTYPES_H */
620 Index: lk/drivers/dsp/bridge/hw/IPIAccInt.h
621 ===================================================================
622 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
623 +++ lk/drivers/dsp/bridge/hw/IPIAccInt.h 2008-08-18 10:38:36.000000000 +0300
624 @@ -0,0 +1,41 @@
625 +/*
626 + * linux/drivers/dsp/bridge/hw/omap3/inc/IPIAccInt.h
627 + *
628 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
629 + *
630 + * Copyright (C) 2005-2006 Texas Instruments, Inc.
631 + *
632 + * This package is free software; you can redistribute it and/or modify
633 + * it under the terms of the GNU General Public License version 2 as
634 + * published by the Free Software Foundation.
635 + *
636 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
637 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
638 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
639 + */
640 +
641 +#ifndef _IPI_ACC_INT_H
642 +#define _IPI_ACC_INT_H
643 +
644 +/* Bitfield mask and offset declarations */
645 +#define SYSC_IVA2BOOTMOD_OFFSET 0x404
646 +#define SYSC_IVA2BOOTADDR_OFFSET 0x400
647 +#define SYSC_IVA2BOOTADDR_MASK 0xfffffc00
648 +
649 +
650 +/* The following represent the enumerated values for each bitfield */
651 +
652 +enum IPIIPI_SYSCONFIGAutoIdleE {
653 + IPIIPI_SYSCONFIGAutoIdleclkfree = 0x0000,
654 + IPIIPI_SYSCONFIGAutoIdleautoclkgate = 0x0001
655 +} ;
656 +
657 +enum IPIIPI_ENTRYElemSizeValueE {
658 + IPIIPI_ENTRYElemSizeValueElemSz8b = 0x0000,
659 + IPIIPI_ENTRYElemSizeValueElemSz16b = 0x0001,
660 + IPIIPI_ENTRYElemSizeValueElemSz32b = 0x0002,
661 + IPIIPI_ENTRYElemSizeValueReserved = 0x0003
662 +} ;
663 +
664 +#endif /* _IPI_ACC_INT_H */
665 +/* EOF */
666 Index: lk/drivers/dsp/bridge/hw/IVA2RegAcM.h
667 ===================================================================
668 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
669 +++ lk/drivers/dsp/bridge/hw/IVA2RegAcM.h 2008-08-18 10:38:36.000000000 +0300
670 @@ -0,0 +1,28 @@
671 +/*
672 + * linux/drivers/dsp/bridge/hw/omap3/dspss/IVA1RegAcM.h
673 + *
674 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
675 + *
676 + * Copyright (C) 2005-2006 Texas Instruments, Inc.
677 + *
678 + * This package is free software; you can redistribute it and/or modify
679 + * it under the terms of the GNU General Public License version 2 as
680 + * published by the Free Software Foundation.
681 + *
682 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
683 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
684 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
685 + */
686 +
687 +
688 +
689 +#ifndef _IVA2_REG_ACM_H
690 +#define _IVA2_REG_ACM_H
691 +
692 +#include <GlobalTypes.h>
693 +#include <EasiGlobal.h>
694 +
695 +#define SYSC_IVA2BOOTMOD_OFFSET 0x404
696 +#define SYSC_IVA2BOOTADDR_OFFSET 0x400
697 +
698 +#endif
699 Index: lk/drivers/dsp/bridge/hw/MLBAccInt.h
700 ===================================================================
701 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
702 +++ lk/drivers/dsp/bridge/hw/MLBAccInt.h 2008-08-18 10:38:36.000000000 +0300
703 @@ -0,0 +1,132 @@
704 +/*
705 + * linux/drivers/dsp/bridge/hw/omap3/mbox/MLBAccInt.h
706 + *
707 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
708 + *
709 + * Copyright (C) 2007 Texas Instruments, Inc.
710 + *
711 + * This package is free software; you can redistribute it and/or modify
712 + * it under the terms of the GNU General Public License version 2 as
713 + * published by the Free Software Foundation.
714 + *
715 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
716 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
717 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
718 + */
719 +
720 +
721 +#ifndef _MLB_ACC_INT_H
722 +#define _MLB_ACC_INT_H
723 +
724 +/* Mappings of level 1 EASI function numbers to function names */
725 +
726 +#define EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32 (MLB_BASE_EASIL1 + 3)
727 +#define EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32 (MLB_BASE_EASIL1 + 4)
728 +#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32 (MLB_BASE_EASIL1 + 7)
729 +#define EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32 (MLB_BASE_EASIL1 + 17)
730 +#define EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32 (MLB_BASE_EASIL1 + 29)
731 +#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32 \
732 + (MLB_BASE_EASIL1 + 33)
733 +#define EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32 (MLB_BASE_EASIL1 + 39)
734 +#define EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32 (MLB_BASE_EASIL1 + 44)
735 +#define EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32 \
736 + (MLB_BASE_EASIL1 + 50)
737 +#define EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32 \
738 + (MLB_BASE_EASIL1 + 51)
739 +#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32 \
740 + (MLB_BASE_EASIL1 + 56)
741 +#define EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32 \
742 + (MLB_BASE_EASIL1 + 57)
743 +#define EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32 \
744 + (MLB_BASE_EASIL1 + 60)
745 +#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32 \
746 + (MLB_BASE_EASIL1 + 62)
747 +#define EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32 \
748 + (MLB_BASE_EASIL1 + 63)
749 +#define EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32 \
750 + (MLB_BASE_EASIL1 + 192)
751 +#define EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32 \
752 + (MLB_BASE_EASIL1 + 193)
753 +
754 +/* Register set MAILBOX_MESSAGE___REGSET_0_15 address offset, bank address
755 + * increment and number of banks */
756 +
757 +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET (u32)(0x0040)
758 +#define MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP (u32)(0x0004)
759 +
760 +/* Register offset address definitions relative to register set
761 + * MAILBOX_MESSAGE___REGSET_0_15 */
762 +
763 +#define MLB_MAILBOX_MESSAGE___0_15_OFFSET (u32)(0x0)
764 +
765 +
766 +/* Register set MAILBOX_FIFOSTATUS___REGSET_0_15 address offset, bank address
767 + * increment and number of banks */
768 +
769 +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET (u32)(0x0080)
770 +#define MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP (u32)(0x0004)
771 +
772 +/* Register offset address definitions relative to register set
773 + * MAILBOX_FIFOSTATUS___REGSET_0_15 */
774 +
775 +#define MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET (u32)(0x0)
776 +
777 +
778 +/* Register set MAILBOX_MSGSTATUS___REGSET_0_15 address offset, bank address
779 + * increment and number of banks */
780 +
781 +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET (u32)(0x00c0)
782 +#define MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP (u32)(0x0004)
783 +
784 +/* Register offset address definitions relative to register set
785 + * MAILBOX_MSGSTATUS___REGSET_0_15 */
786 +
787 +#define MLB_MAILBOX_MSGSTATUS___0_15_OFFSET (u32)(0x0)
788 +
789 +
790 +/* Register set MAILBOX_IRQSTATUS___REGSET_0_3 address offset, bank address
791 + * increment and number of banks */
792 +
793 +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET (u32)(0x0100)
794 +#define MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP (u32)(0x0008)
795 +
796 +/* Register offset address definitions relative to register set
797 + * MAILBOX_IRQSTATUS___REGSET_0_3 */
798 +
799 +#define MLB_MAILBOX_IRQSTATUS___0_3_OFFSET (u32)(0x0)
800 +
801 +
802 +/* Register set MAILBOX_IRQENABLE___REGSET_0_3 address offset, bank address
803 + * increment and number of banks */
804 +
805 +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET (u32)(0x0104)
806 +#define MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP (u32)(0x0008)
807 +
808 +/* Register offset address definitions relative to register set
809 + * MAILBOX_IRQENABLE___REGSET_0_3 */
810 +
811 +#define MLB_MAILBOX_IRQENABLE___0_3_OFFSET (u32)(0x0)
812 +
813 +
814 +/* Register offset address definitions */
815 +
816 +#define MLB_MAILBOX_SYSCONFIG_OFFSET (u32)(0x10)
817 +#define MLB_MAILBOX_SYSSTATUS_OFFSET (u32)(0x14)
818 +
819 +
820 +/* Bitfield mask and offset declarations */
821 +
822 +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK (u32)(0x18)
823 +#define MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET (u32)(3)
824 +#define MLB_MAILBOX_SYSCONFIG_SoftReset_MASK (u32)(0x2)
825 +#define MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET (u32)(1)
826 +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK (u32)(0x1)
827 +#define MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET (u32)(0)
828 +#define MLB_MAILBOX_SYSSTATUS_ResetDone_MASK (u32)(0x1)
829 +#define MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET (u32)(0)
830 +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK (u32)(0x1)
831 +#define MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET (u32)(0)
832 +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK (u32)(0x7f)
833 +#define MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET (u32)(0)
834 +
835 +#endif /* _MLB_ACC_INT_H */
836 Index: lk/drivers/dsp/bridge/hw/MLBRegAcM.h
837 ===================================================================
838 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
839 +++ lk/drivers/dsp/bridge/hw/MLBRegAcM.h 2008-08-18 10:38:36.000000000 +0300
840 @@ -0,0 +1,200 @@
841 +/*
842 + * linux/drivers/dsp/bridge/hw/omap3/mbox/MLBRegAcM.h
843 + *
844 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
845 + *
846 + * Copyright (C) 2007 Texas Instruments, Inc.
847 + *
848 + * This package is free software; you can redistribute it and/or modify
849 + * it under the terms of the GNU General Public License version 2 as
850 + * published by the Free Software Foundation.
851 + *
852 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
853 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
854 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
855 + */
856 +
857 +#ifndef _MLB_REG_ACM_H
858 +#define _MLB_REG_ACM_H
859 +
860 +#include <GlobalTypes.h>
861 +#include <EasiGlobal.h>
862 +#include "MLBAccInt.h"
863 +
864 +#if defined(USE_LEVEL_1_MACROS)
865 +
866 +#define MLBMAILBOX_SYSCONFIGReadRegister32(baseAddress)\
867 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGReadRegister32),\
868 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+ \
869 + MLB_MAILBOX_SYSCONFIG_OFFSET))
870 +
871 +
872 +#define MLBMAILBOX_SYSCONFIGWriteRegister32(baseAddress, value)\
873 +{\
874 + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
875 + register u32 newValue = ((u32)(value));\
876 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGWriteRegister32);\
877 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
878 +}
879 +
880 +
881 +#define MLBMAILBOX_SYSCONFIGSIdleModeRead32(baseAddress)\
882 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeRead32),\
883 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
884 + (MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
885 + MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK) >>\
886 + MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET))
887 +
888 +
889 +#define MLBMAILBOX_SYSCONFIGSIdleModeWrite32(baseAddress, value)\
890 +{\
891 + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
892 + register u32 data = RD_MEM_32_VOLATILE(((u32)(baseAddress)) +\
893 + offset);\
894 + register u32 newValue = ((u32)(value));\
895 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSIdleModeWrite32);\
896 + data &= ~(MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK);\
897 + newValue <<= MLB_MAILBOX_SYSCONFIG_SIdleMode_OFFSET;\
898 + newValue &= MLB_MAILBOX_SYSCONFIG_SIdleMode_MASK;\
899 + newValue |= data;\
900 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
901 +}
902 +
903 +
904 +#define MLBMAILBOX_SYSCONFIGSoftResetWrite32(baseAddress, value)\
905 +{\
906 + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
907 + register u32 data =\
908 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
909 + register u32 newValue = ((u32)(value));\
910 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGSoftResetWrite32);\
911 + data &= ~(MLB_MAILBOX_SYSCONFIG_SoftReset_MASK);\
912 + newValue <<= MLB_MAILBOX_SYSCONFIG_SoftReset_OFFSET;\
913 + newValue &= MLB_MAILBOX_SYSCONFIG_SoftReset_MASK;\
914 + newValue |= data;\
915 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
916 +}
917 +
918 +
919 +#define MLBMAILBOX_SYSCONFIGAutoIdleRead32(baseAddress)\
920 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleRead32),\
921 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
922 + (MLB_MAILBOX_SYSCONFIG_OFFSET)))) &\
923 + MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK) >>\
924 + MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET))
925 +
926 +
927 +#define MLBMAILBOX_SYSCONFIGAutoIdleWrite32(baseAddress, value)\
928 +{\
929 + const u32 offset = MLB_MAILBOX_SYSCONFIG_OFFSET;\
930 + register u32 data =\
931 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
932 + register u32 newValue = ((u32)(value));\
933 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSCONFIGAutoIdleWrite32);\
934 + data &= ~(MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK);\
935 + newValue <<= MLB_MAILBOX_SYSCONFIG_AutoIdle_OFFSET;\
936 + newValue &= MLB_MAILBOX_SYSCONFIG_AutoIdle_MASK;\
937 + newValue |= data;\
938 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
939 +}
940 +
941 +
942 +#define MLBMAILBOX_SYSSTATUSResetDoneRead32(baseAddress)\
943 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_SYSSTATUSResetDoneRead32),\
944 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
945 + (MLB_MAILBOX_SYSSTATUS_OFFSET)))) &\
946 + MLB_MAILBOX_SYSSTATUS_ResetDone_MASK) >>\
947 + MLB_MAILBOX_SYSSTATUS_ResetDone_OFFSET))
948 +
949 +
950 +#define MLBMAILBOX_MESSAGE___0_15ReadRegister32(baseAddress, bank)\
951 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15ReadRegister32),\
952 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
953 + (MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
954 + MLB_MAILBOX_MESSAGE___0_15_OFFSET+(\
955 + (bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP))))
956 +
957 +
958 +#define MLBMAILBOX_MESSAGE___0_15WriteRegister32(baseAddress, bank, value)\
959 +{\
960 + const u32 offset = MLB_MAILBOX_MESSAGE___REGSET_0_15_OFFSET +\
961 + MLB_MAILBOX_MESSAGE___0_15_OFFSET +\
962 + ((bank)*MLB_MAILBOX_MESSAGE___REGSET_0_15_STEP);\
963 + register u32 newValue = ((u32)(value));\
964 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_MESSAGE___0_15WriteRegister32);\
965 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
966 +}
967 +
968 +
969 +#define MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32(baseAddress, bank)\
970 + (_DEBUG_LEVEL_1_EASI(\
971 + EASIL1_MLBMAILBOX_FIFOSTATUS___0_15ReadRegister32),\
972 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
973 + (MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
974 + MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
975 + ((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP))))
976 +
977 +
978 +#define MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress, bank)\
979 + (_DEBUG_LEVEL_1_EASI(\
980 + EASIL1_MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32),\
981 + (((RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
982 + (MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_OFFSET +\
983 + MLB_MAILBOX_FIFOSTATUS___0_15_OFFSET+\
984 + ((bank)*MLB_MAILBOX_FIFOSTATUS___REGSET_0_15_STEP)))) &\
985 + MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_MASK) >>\
986 + MLB_MAILBOX_FIFOSTATUS___0_15_FifoFullMBm_OFFSET))
987 +
988 +
989 +#define MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(baseAddress, bank)\
990 + (_DEBUG_LEVEL_1_EASI(\
991 + EASIL1_MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32),\
992 + (((RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
993 + (MLB_MAILBOX_MSGSTATUS___REGSET_0_15_OFFSET +\
994 + MLB_MAILBOX_MSGSTATUS___0_15_OFFSET+\
995 + ((bank)*MLB_MAILBOX_MSGSTATUS___REGSET_0_15_STEP)))) &\
996 + MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_MASK) >>\
997 + MLB_MAILBOX_MSGSTATUS___0_15_NbOfMsgMBm_OFFSET))
998 +
999 +
1000 +#define MLBMAILBOX_IRQSTATUS___0_3ReadRegister32(baseAddress, bank)\
1001 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3ReadRegister32),\
1002 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
1003 + (MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
1004 + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET+\
1005 + ((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP))))
1006 +
1007 +
1008 +#define MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(baseAddress, bank, value)\
1009 +{\
1010 + const u32 offset = MLB_MAILBOX_IRQSTATUS___REGSET_0_3_OFFSET +\
1011 + MLB_MAILBOX_IRQSTATUS___0_3_OFFSET +\
1012 + ((bank)*MLB_MAILBOX_IRQSTATUS___REGSET_0_3_STEP);\
1013 + register u32 newValue = ((u32)(value));\
1014 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQSTATUS___0_3WriteRegister32);\
1015 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1016 +}
1017 +
1018 +
1019 +#define MLBMAILBOX_IRQENABLE___0_3ReadRegister32(baseAddress, bank)\
1020 + (_DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3ReadRegister32),\
1021 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+\
1022 + (MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
1023 + MLB_MAILBOX_IRQENABLE___0_3_OFFSET+\
1024 + ((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP))))
1025 +
1026 +
1027 +#define MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, bank, value)\
1028 +{\
1029 + const u32 offset = MLB_MAILBOX_IRQENABLE___REGSET_0_3_OFFSET +\
1030 + MLB_MAILBOX_IRQENABLE___0_3_OFFSET +\
1031 + ((bank)*MLB_MAILBOX_IRQENABLE___REGSET_0_3_STEP);\
1032 + register u32 newValue = ((u32)(value));\
1033 + _DEBUG_LEVEL_1_EASI(EASIL1_MLBMAILBOX_IRQENABLE___0_3WriteRegister32);\
1034 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1035 +}
1036 +
1037 +
1038 +#endif /* USE_LEVEL_1_MACROS */
1039 +
1040 +#endif /* _MLB_REG_ACM_H */
1041 Index: lk/drivers/dsp/bridge/hw/MMUAccInt.h
1042 ===================================================================
1043 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1044 +++ lk/drivers/dsp/bridge/hw/MMUAccInt.h 2008-08-18 10:38:36.000000000 +0300
1045 @@ -0,0 +1,79 @@
1046 +/*
1047 + * linux/drivers/dsp/bridge/hw/omap3/mmu/MMUAccInt.h
1048 + *
1049 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
1050 + *
1051 + * Copyright (C) 2007 Texas Instruments, Inc.
1052 + *
1053 + * This package is free software; you can redistribute it and/or modify
1054 + * it under the terms of the GNU General Public License version 2 as
1055 + * published by the Free Software Foundation.
1056 + *
1057 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
1058 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
1059 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
1060 + */
1061 +
1062 +#ifndef _MMU_ACC_INT_H
1063 +#define _MMU_ACC_INT_H
1064 +
1065 +/* Mappings of level 1 EASI function numbers to function names */
1066 +
1067 +#define EASIL1_MMUMMU_SYSCONFIGReadRegister32 (MMU_BASE_EASIL1 + 3)
1068 +#define EASIL1_MMUMMU_SYSCONFIGIdleModeWrite32 (MMU_BASE_EASIL1 + 17)
1069 +#define EASIL1_MMUMMU_SYSCONFIGAutoIdleWrite32 (MMU_BASE_EASIL1 + 39)
1070 +#define EASIL1_MMUMMU_IRQSTATUSWriteRegister32 (MMU_BASE_EASIL1 + 51)
1071 +#define EASIL1_MMUMMU_IRQENABLEReadRegister32 (MMU_BASE_EASIL1 + 102)
1072 +#define EASIL1_MMUMMU_IRQENABLEWriteRegister32 (MMU_BASE_EASIL1 + 103)
1073 +#define EASIL1_MMUMMU_WALKING_STTWLRunningRead32 (MMU_BASE_EASIL1 + 156)
1074 +#define EASIL1_MMUMMU_CNTLTWLEnableRead32 (MMU_BASE_EASIL1 + 174)
1075 +#define EASIL1_MMUMMU_CNTLTWLEnableWrite32 (MMU_BASE_EASIL1 + 180)
1076 +#define EASIL1_MMUMMU_CNTLMMUEnableWrite32 (MMU_BASE_EASIL1 + 190)
1077 +#define EASIL1_MMUMMU_FAULT_ADReadRegister32 (MMU_BASE_EASIL1 + 194)
1078 +#define EASIL1_MMUMMU_TTBWriteRegister32 (MMU_BASE_EASIL1 + 198)
1079 +#define EASIL1_MMUMMU_LOCKReadRegister32 (MMU_BASE_EASIL1 + 203)
1080 +#define EASIL1_MMUMMU_LOCKWriteRegister32 (MMU_BASE_EASIL1 + 204)
1081 +#define EASIL1_MMUMMU_LOCKBaseValueRead32 (MMU_BASE_EASIL1 + 205)
1082 +#define EASIL1_MMUMMU_LOCKCurrentVictimRead32 (MMU_BASE_EASIL1 + 209)
1083 +#define EASIL1_MMUMMU_LOCKCurrentVictimWrite32 (MMU_BASE_EASIL1 + 211)
1084 +#define EASIL1_MMUMMU_LOCKCurrentVictimSet32 (MMU_BASE_EASIL1 + 212)
1085 +#define EASIL1_MMUMMU_LD_TLBReadRegister32 (MMU_BASE_EASIL1 + 213)
1086 +#define EASIL1_MMUMMU_LD_TLBWriteRegister32 (MMU_BASE_EASIL1 + 214)
1087 +#define EASIL1_MMUMMU_CAMWriteRegister32 (MMU_BASE_EASIL1 + 226)
1088 +#define EASIL1_MMUMMU_RAMWriteRegister32 (MMU_BASE_EASIL1 + 268)
1089 +#define EASIL1_MMUMMU_GFLUSHGlobalFlushWrite32 (MMU_BASE_EASIL1 + 317)
1090 +#define EASIL1_MMUMMU_FLUSH_ENTRYWriteRegister32 (MMU_BASE_EASIL1 + 322)
1091 +
1092 +/* Register offset address definitions */
1093 +#define MMU_MMU_SYSCONFIG_OFFSET 0x10
1094 +#define MMU_MMU_IRQSTATUS_OFFSET 0x18
1095 +#define MMU_MMU_IRQENABLE_OFFSET 0x1c
1096 +#define MMU_MMU_WALKING_ST_OFFSET 0x40
1097 +#define MMU_MMU_CNTL_OFFSET 0x44
1098 +#define MMU_MMU_FAULT_AD_OFFSET 0x48
1099 +#define MMU_MMU_TTB_OFFSET 0x4c
1100 +#define MMU_MMU_LOCK_OFFSET 0x50
1101 +#define MMU_MMU_LD_TLB_OFFSET 0x54
1102 +#define MMU_MMU_CAM_OFFSET 0x58
1103 +#define MMU_MMU_RAM_OFFSET 0x5c
1104 +#define MMU_MMU_GFLUSH_OFFSET 0x60
1105 +#define MMU_MMU_FLUSH_ENTRY_OFFSET 0x64
1106 +/* Bitfield mask and offset declarations */
1107 +#define MMU_MMU_SYSCONFIG_IdleMode_MASK 0x18
1108 +#define MMU_MMU_SYSCONFIG_IdleMode_OFFSET 3
1109 +#define MMU_MMU_SYSCONFIG_AutoIdle_MASK 0x1
1110 +#define MMU_MMU_SYSCONFIG_AutoIdle_OFFSET 0
1111 +#define MMU_MMU_WALKING_ST_TWLRunning_MASK 0x1
1112 +#define MMU_MMU_WALKING_ST_TWLRunning_OFFSET 0
1113 +#define MMU_MMU_CNTL_TWLEnable_MASK 0x4
1114 +#define MMU_MMU_CNTL_TWLEnable_OFFSET 2
1115 +#define MMU_MMU_CNTL_MMUEnable_MASK 0x2
1116 +#define MMU_MMU_CNTL_MMUEnable_OFFSET 1
1117 +#define MMU_MMU_LOCK_BaseValue_MASK 0xfc00
1118 +#define MMU_MMU_LOCK_BaseValue_OFFSET 10
1119 +#define MMU_MMU_LOCK_CurrentVictim_MASK 0x3f0
1120 +#define MMU_MMU_LOCK_CurrentVictim_OFFSET 4
1121 +#define MMU_MMU_GFLUSH_GlobalFlush_MASK 0x1
1122 +#define MMU_MMU_GFLUSH_GlobalFlush_OFFSET 0
1123 +
1124 +#endif /* _MMU_ACC_INT_H */
1125 Index: lk/drivers/dsp/bridge/hw/MMURegAcM.h
1126 ===================================================================
1127 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1128 +++ lk/drivers/dsp/bridge/hw/MMURegAcM.h 2008-08-18 10:38:36.000000000 +0300
1129 @@ -0,0 +1,267 @@
1130 +/*
1131 + * linux/drivers/dsp/bridge/hw/omap3/mmu/MMURegAcM.h
1132 + *
1133 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
1134 + *
1135 + * Copyright (C) 2007 Texas Instruments, Inc.
1136 + *
1137 + * This package is free software; you can redistribute it and/or modify
1138 + * it under the terms of the GNU General Public License version 2 as
1139 + * published by the Free Software Foundation.
1140 + *
1141 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
1142 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
1143 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
1144 + */
1145 +
1146 +
1147 +#ifndef _MMU_REG_ACM_H
1148 +#define _MMU_REG_ACM_H
1149 +
1150 +#include <GlobalTypes.h>
1151 +
1152 +#include <EasiGlobal.h>
1153 +
1154 +#include "MMUAccInt.h"
1155 +
1156 +#if defined(USE_LEVEL_1_MACROS)
1157 +
1158 +
1159 +#define MMUMMU_SYSCONFIGReadRegister32(baseAddress)\
1160 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGReadRegister32),\
1161 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_SYSCONFIG_OFFSET))
1162 +
1163 +
1164 +#define MMUMMU_SYSCONFIGIdleModeWrite32(baseAddress, value)\
1165 +{\
1166 + const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
1167 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1168 + register u32 newValue = (value);\
1169 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGIdleModeWrite32);\
1170 + data &= ~(MMU_MMU_SYSCONFIG_IdleMode_MASK);\
1171 + newValue <<= MMU_MMU_SYSCONFIG_IdleMode_OFFSET;\
1172 + newValue &= MMU_MMU_SYSCONFIG_IdleMode_MASK;\
1173 + newValue |= data;\
1174 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1175 +}
1176 +
1177 +
1178 +#define MMUMMU_SYSCONFIGAutoIdleWrite32(baseAddress, value)\
1179 +{\
1180 + const u32 offset = MMU_MMU_SYSCONFIG_OFFSET;\
1181 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1182 + register u32 newValue = (value);\
1183 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_SYSCONFIGAutoIdleWrite32);\
1184 + data &= ~(MMU_MMU_SYSCONFIG_AutoIdle_MASK);\
1185 + newValue <<= MMU_MMU_SYSCONFIG_AutoIdle_OFFSET;\
1186 + newValue &= MMU_MMU_SYSCONFIG_AutoIdle_MASK;\
1187 + newValue |= data;\
1188 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1189 +}
1190 +
1191 +
1192 +#define MMUMMU_IRQSTATUSReadRegister32(baseAddress)\
1193 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSReadRegister32),\
1194 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_IRQSTATUS_OFFSET))
1195 +
1196 +
1197 +#define MMUMMU_IRQSTATUSWriteRegister32(baseAddress, value)\
1198 +{\
1199 + const u32 offset = MMU_MMU_IRQSTATUS_OFFSET;\
1200 + register u32 newValue = (value);\
1201 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQSTATUSWriteRegister32);\
1202 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1203 +}
1204 +
1205 +
1206 +#define MMUMMU_IRQENABLEReadRegister32(baseAddress)\
1207 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEReadRegister32),\
1208 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_IRQENABLE_OFFSET))
1209 +
1210 +
1211 +#define MMUMMU_IRQENABLEWriteRegister32(baseAddress, value)\
1212 +{\
1213 + const u32 offset = MMU_MMU_IRQENABLE_OFFSET;\
1214 + register u32 newValue = (value);\
1215 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_IRQENABLEWriteRegister32);\
1216 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1217 +}
1218 +
1219 +
1220 +#define MMUMMU_WALKING_STTWLRunningRead32(baseAddress)\
1221 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_WALKING_STTWLRunningRead32),\
1222 + (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_WALKING_ST_OFFSET))))\
1223 + & MMU_MMU_WALKING_ST_TWLRunning_MASK) >>\
1224 + MMU_MMU_WALKING_ST_TWLRunning_OFFSET))
1225 +
1226 +
1227 +#define MMUMMU_CNTLTWLEnableRead32(baseAddress)\
1228 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableRead32),\
1229 + (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_CNTL_OFFSET)))) &\
1230 + MMU_MMU_CNTL_TWLEnable_MASK) >>\
1231 + MMU_MMU_CNTL_TWLEnable_OFFSET))
1232 +
1233 +
1234 +#define MMUMMU_CNTLTWLEnableWrite32(baseAddress, value)\
1235 +{\
1236 + const u32 offset = MMU_MMU_CNTL_OFFSET;\
1237 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1238 + register u32 newValue = (value);\
1239 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLTWLEnableWrite32);\
1240 + data &= ~(MMU_MMU_CNTL_TWLEnable_MASK);\
1241 + newValue <<= MMU_MMU_CNTL_TWLEnable_OFFSET;\
1242 + newValue &= MMU_MMU_CNTL_TWLEnable_MASK;\
1243 + newValue |= data;\
1244 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1245 +}
1246 +
1247 +
1248 +#define MMUMMU_CNTLMMUEnableWrite32(baseAddress, value)\
1249 +{\
1250 + const u32 offset = MMU_MMU_CNTL_OFFSET;\
1251 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1252 + register u32 newValue = (value);\
1253 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CNTLMMUEnableWrite32);\
1254 + data &= ~(MMU_MMU_CNTL_MMUEnable_MASK);\
1255 + newValue <<= MMU_MMU_CNTL_MMUEnable_OFFSET;\
1256 + newValue &= MMU_MMU_CNTL_MMUEnable_MASK;\
1257 + newValue |= data;\
1258 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1259 +}
1260 +
1261 +
1262 +#define MMUMMU_FAULT_ADReadRegister32(baseAddress)\
1263 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FAULT_ADReadRegister32),\
1264 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_FAULT_AD_OFFSET))
1265 +
1266 +
1267 +#define MMUMMU_TTBWriteRegister32(baseAddress, value)\
1268 +{\
1269 + const u32 offset = MMU_MMU_TTB_OFFSET;\
1270 + register u32 newValue = (value);\
1271 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_TTBWriteRegister32);\
1272 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1273 +}
1274 +
1275 +
1276 +#define MMUMMU_LOCKReadRegister32(baseAddress)\
1277 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKReadRegister32),\
1278 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_LOCK_OFFSET))
1279 +
1280 +
1281 +#define MMUMMU_LOCKWriteRegister32(baseAddress, value)\
1282 +{\
1283 + const u32 offset = MMU_MMU_LOCK_OFFSET;\
1284 + register u32 newValue = (value);\
1285 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKWriteRegister32);\
1286 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1287 +}
1288 +
1289 +
1290 +#define MMUMMU_LOCKBaseValueRead32(baseAddress)\
1291 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueRead32),\
1292 + (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
1293 + MMU_MMU_LOCK_BaseValue_MASK) >>\
1294 + MMU_MMU_LOCK_BaseValue_OFFSET))
1295 +
1296 +
1297 +#define MMUMMU_LOCKBaseValueWrite32(baseAddress, value)\
1298 +{\
1299 + const u32 offset = MMU_MMU_LOCK_OFFSET;\
1300 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1301 + register u32 newValue = (value);\
1302 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKBaseValueWrite32);\
1303 + data &= ~(MMU_MMU_LOCK_BaseValue_MASK);\
1304 + newValue <<= MMU_MMU_LOCK_BaseValue_OFFSET;\
1305 + newValue &= MMU_MMU_LOCK_BaseValue_MASK;\
1306 + newValue |= data;\
1307 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1308 +}
1309 +
1310 +
1311 +#define MMUMMU_LOCKCurrentVictimRead32(baseAddress)\
1312 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimRead32),\
1313 + (((RD_MEM_32_VOLATILE(((baseAddress)+(MMU_MMU_LOCK_OFFSET)))) &\
1314 + MMU_MMU_LOCK_CurrentVictim_MASK) >>\
1315 + MMU_MMU_LOCK_CurrentVictim_OFFSET))
1316 +
1317 +
1318 +#define MMUMMU_LOCKCurrentVictimWrite32(baseAddress, value)\
1319 +{\
1320 + const u32 offset = MMU_MMU_LOCK_OFFSET;\
1321 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1322 + register u32 newValue = (value);\
1323 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimWrite32);\
1324 + data &= ~(MMU_MMU_LOCK_CurrentVictim_MASK);\
1325 + newValue <<= MMU_MMU_LOCK_CurrentVictim_OFFSET;\
1326 + newValue &= MMU_MMU_LOCK_CurrentVictim_MASK;\
1327 + newValue |= data;\
1328 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1329 +}
1330 +
1331 +
1332 +#define MMUMMU_LOCKCurrentVictimSet32(var, value)\
1333 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LOCKCurrentVictimSet32),\
1334 + (((var) & ~(MMU_MMU_LOCK_CurrentVictim_MASK)) |\
1335 + (((value) << MMU_MMU_LOCK_CurrentVictim_OFFSET) &\
1336 + MMU_MMU_LOCK_CurrentVictim_MASK)))
1337 +
1338 +
1339 +#define MMUMMU_LD_TLBReadRegister32(baseAddress)\
1340 + (_DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBReadRegister32),\
1341 + RD_MEM_32_VOLATILE((baseAddress)+MMU_MMU_LD_TLB_OFFSET))
1342 +
1343 +
1344 +#define MMUMMU_LD_TLBWriteRegister32(baseAddress, value)\
1345 +{\
1346 + const u32 offset = MMU_MMU_LD_TLB_OFFSET;\
1347 + register u32 newValue = (value);\
1348 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_LD_TLBWriteRegister32);\
1349 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1350 +}
1351 +
1352 +
1353 +#define MMUMMU_CAMWriteRegister32(baseAddress, value)\
1354 +{\
1355 + const u32 offset = MMU_MMU_CAM_OFFSET;\
1356 + register u32 newValue = (value);\
1357 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_CAMWriteRegister32);\
1358 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1359 +}
1360 +
1361 +
1362 +#define MMUMMU_RAMWriteRegister32(baseAddress, value)\
1363 +{\
1364 + const u32 offset = MMU_MMU_RAM_OFFSET;\
1365 + register u32 newValue = (value);\
1366 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_RAMWriteRegister32);\
1367 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1368 +}
1369 +
1370 +
1371 +#define MMUMMU_GFLUSHGlobalFlushWrite32(baseAddress, value)\
1372 +{\
1373 + const u32 offset = MMU_MMU_GFLUSH_OFFSET;\
1374 + register u32 data = RD_MEM_32_VOLATILE((baseAddress)+offset);\
1375 + register u32 newValue = (value);\
1376 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_GFLUSHGlobalFlushWrite32);\
1377 + data &= ~(MMU_MMU_GFLUSH_GlobalFlush_MASK);\
1378 + newValue <<= MMU_MMU_GFLUSH_GlobalFlush_OFFSET;\
1379 + newValue &= MMU_MMU_GFLUSH_GlobalFlush_MASK;\
1380 + newValue |= data;\
1381 + WR_MEM_32_VOLATILE(baseAddress+offset, newValue);\
1382 +}
1383 +
1384 +
1385 +#define MMUMMU_FLUSH_ENTRYWriteRegister32(baseAddress, value)\
1386 +{\
1387 + const u32 offset = MMU_MMU_FLUSH_ENTRY_OFFSET;\
1388 + register u32 newValue = (value);\
1389 + _DEBUG_LEVEL_1_EASI(EASIL1_MMUMMU_FLUSH_ENTRYWriteRegister32);\
1390 + WR_MEM_32_VOLATILE((baseAddress)+offset, newValue);\
1391 +}
1392 +
1393 +
1394 +#endif /* USE_LEVEL_1_MACROS */
1395 +
1396 +#endif /* _MMU_REG_ACM_H */
1397 Index: lk/drivers/dsp/bridge/hw/PRCMAccInt.h
1398 ===================================================================
1399 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1400 +++ lk/drivers/dsp/bridge/hw/PRCMAccInt.h 2008-08-18 10:38:36.000000000 +0300
1401 @@ -0,0 +1,300 @@
1402 +/*
1403 + * linux/drivers/dsp/bridge/hw/omap3/prcm/PRCMAccInt.h
1404 + *
1405 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
1406 + *
1407 + * Copyright (C) 2007 Texas Instruments, Inc.
1408 + *
1409 + * This package is free software; you can redistribute it and/or modify
1410 + * it under the terms of the GNU General Public License version 2 as
1411 + * published by the Free Software Foundation.
1412 + *
1413 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
1414 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
1415 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
1416 + */
1417 +
1418 +#ifndef _PRCM_ACC_INT_H
1419 +#define _PRCM_ACC_INT_H
1420 +
1421 +/* Mappings of level 1 EASI function numbers to function names */
1422 +
1423 +#define EASIL1_PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32 \
1424 + (PRCM_BASE_EASIL1 + 349)
1425 +#define EASIL1_PRCMCM_FCLKEN1_COREReadRegister32 (PRCM_BASE_EASIL1 + 743)
1426 +#define EASIL1_PRCMCM_FCLKEN1_COREEN_GPT8Write32 (PRCM_BASE_EASIL1 + 951)
1427 +#define EASIL1_PRCMCM_FCLKEN1_COREEN_GPT7Write32 (PRCM_BASE_EASIL1 + 961)
1428 +#define EASIL1_PRCMCM_ICLKEN1_COREReadRegister32 \
1429 + (PRCM_BASE_EASIL1 + 1087)
1430 +#define EASIL1_PRCMCM_ICLKEN1_COREEN_MAILBOXESWrite32 \
1431 + (PRCM_BASE_EASIL1 + 1105)
1432 +#define EASIL1_PRCMCM_ICLKEN1_COREEN_GPT8Write32 \
1433 + (PRCM_BASE_EASIL1 + 1305)
1434 +#define EASIL1_PRCMCM_ICLKEN1_COREEN_GPT7Write32 \
1435 + (PRCM_BASE_EASIL1 + 1315)
1436 +#define EASIL1_PRCMCM_CLKSEL1_CORECLKSEL_L3ReadIssel132 \
1437 + (PRCM_BASE_EASIL1 + 2261)
1438 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32 \
1439 + (PRCM_BASE_EASIL1 + 2364)
1440 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32 \
1441 + (PRCM_BASE_EASIL1 + 2365)
1442 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32 \
1443 + (PRCM_BASE_EASIL1 + 2366)
1444 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32 \
1445 + (PRCM_BASE_EASIL1 + 2380)
1446 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32 \
1447 + (PRCM_BASE_EASIL1 + 2381)
1448 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32 \
1449 + (PRCM_BASE_EASIL1 + 2382)
1450 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32 \
1451 + (PRCM_BASE_EASIL1 + 2397)
1452 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32 \
1453 + (PRCM_BASE_EASIL1 + 2398)
1454 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32 \
1455 + (PRCM_BASE_EASIL1 + 2413)
1456 +#define EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32 \
1457 + (PRCM_BASE_EASIL1 + 2414)
1458 +#define EASIL1_PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32 \
1459 + (PRCM_BASE_EASIL1 + 3747)
1460 +#define EASIL1_PRCMCM_FCLKEN_DSPEN_DSPWrite32 (PRCM_BASE_EASIL1 + 3834)
1461 +#define EASIL1_PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32 \
1462 + (PRCM_BASE_EASIL1 + 3846)
1463 +#define EASIL1_PRCMCM_IDLEST_DSPReadRegister32 (PRCM_BASE_EASIL1 + 3850)
1464 +#define EASIL1_PRCMCM_IDLEST_DSPST_IPIRead32 (PRCM_BASE_EASIL1 + 3857)
1465 +#define EASIL1_PRCMCM_IDLEST_DSPST_DSPRead32 (PRCM_BASE_EASIL1 + 3863)
1466 +#define EASIL1_PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32 \
1467 + (PRCM_BASE_EASIL1 + 3877)
1468 +#define EASIL1_PRCMCM_CLKSEL_DSPSYNC_DSPWrite32 (PRCM_BASE_EASIL1 + 3927)
1469 +#define EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32 \
1470 + (PRCM_BASE_EASIL1 + 3941)
1471 +#define EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32 \
1472 + (PRCM_BASE_EASIL1 + 3965)
1473 +#define EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32 \
1474 + (PRCM_BASE_EASIL1 + 3987)
1475 +#define EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32 \
1476 + (PRCM_BASE_EASIL1 + 3993)
1477 +#define EASIL1_PRCMRM_RSTCTRL_DSPReadRegister32 (PRCM_BASE_EASIL1 + 3997)
1478 +#define EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32 \
1479 + (PRCM_BASE_EASIL1 + 4025)
1480 +#define EASIL1_PRCMRM_RSTST_DSPReadRegister32 (PRCM_BASE_EASIL1 + 4029)
1481 +#define EASIL1_PRCMRM_RSTST_DSPWriteRegister32 (PRCM_BASE_EASIL1 + 4030)
1482 +#define EASIL1_PRCMPM_PWSTCTRL_DSPForceStateWrite32 \
1483 + (PRCM_BASE_EASIL1 + 4165)
1484 +#define EASIL1_PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32 \
1485 + (PRCM_BASE_EASIL1 + 4193)
1486 +#define EASIL1_PRCMPM_PWSTST_DSPReadRegister32 (PRCM_BASE_EASIL1 + 4197)
1487 +#define EASIL1_PRCMPM_PWSTST_DSPInTransitionRead32 \
1488 + (PRCM_BASE_EASIL1 + 4198)
1489 +#define EASIL1_PRCMPM_PWSTST_DSPPowerStateStGet32 \
1490 + (PRCM_BASE_EASIL1 + 4235)
1491 +#define EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32 \
1492 + (PRCM_BASE_EASIL1 + 4368)
1493 +#define EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32 \
1494 + (PRCM_BASE_EASIL1 + 4370)
1495 +#define EASIL1_CM_CLKSEL_PER_GPT5Write32k32 (PRCM_BASE_EASIL1 + 4372)
1496 +#define EASIL1_CM_CLKSEL_PER_GPT6Write32k32 (PRCM_BASE_EASIL1 + 4373)
1497 +#define EASIL1_PRCMCM_CLKSTCTRL_IVA2WriteRegister32 \
1498 + (PRCM_BASE_EASIL1 + 4374)
1499 +#define EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32 \
1500 + (PRCM_BASE_EASIL1 + 4375)
1501 +#define EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32 \
1502 + (PRCM_BASE_EASIL1 + 4376)
1503 +#define EASIL1_PRCMPM_PWSTST_IVA2InTransitionRead32 \
1504 + (PRCM_BASE_EASIL1 + 4377)
1505 +#define EASIL1_PRCMPM_PWSTST_IVA2PowerStateStGet32 \
1506 + (PRCM_BASE_EASIL1 + 4378)
1507 +#define EASIL1_PRCMPM_PWSTST_IVA2ReadRegister32 (PRCM_BASE_EASIL1 + 4379)
1508 +
1509 +/* Register offset address definitions */
1510 +
1511 +#define PRCM_PRCM_CLKCFG_CTRL_OFFSET (u32)(0x80)
1512 +#define PRCM_CM_FCLKEN1_CORE_OFFSET (u32)(0x200)
1513 +#define PRCM_CM_ICLKEN1_CORE_OFFSET (u32)(0x210)
1514 +#define PRCM_CM_CLKSEL2_CORE_OFFSET (u32)(0x244)
1515 +#define PRCM_CM_CLKSEL1_PLL_OFFSET (u32)(0x540)
1516 +#define PRCM_CM_ICLKEN_DSP_OFFSET (u32)(0x810)
1517 +#define PRCM_CM_IDLEST_DSP_OFFSET (u32)(0x820)
1518 +#define PRCM_CM_AUTOIDLE_DSP_OFFSET (u32)(0x830)
1519 +#define PRCM_CM_CLKSEL_DSP_OFFSET (u32)(0x840)
1520 +#define PRCM_CM_CLKSTCTRL_DSP_OFFSET (u32)(0x848)
1521 +#define PRCM_RM_RSTCTRL_DSP_OFFSET (u32)(0x850)
1522 +#define PRCM_RM_RSTST_DSP_OFFSET (u32)(0x858)
1523 +#define PRCM_PM_PWSTCTRL_DSP_OFFSET (u32)(0x8e0)
1524 +#define PRCM_PM_PWSTST_DSP_OFFSET (u32)(0x8e4)
1525 +#define PRCM_PM_PWSTST_IVA2_OFFSET (u32)(0xE4)
1526 +#define PRCM_PM_PWSTCTRL_IVA2_OFFSET (u32)(0xE0)
1527 +#define PRCM_CM_CLKSTCTRL_IVA2_OFFSET (u32)(0x48)
1528 +#define CM_CLKSEL_PER_OFFSET (u32)(0x40)
1529 +
1530 +/* Bitfield mask and offset declarations */
1531 +
1532 +#define PRCM_PRCM_CLKCFG_CTRL_Valid_config_MASK (u32)(0x1)
1533 +#define PRCM_PRCM_CLKCFG_CTRL_Valid_config_OFFSET (u32)(0)
1534 +
1535 +#define PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK (u32)(0x400)
1536 +#define PRCM_CM_FCLKEN1_CORE_EN_GPT8_OFFSET (u32)(10)
1537 +
1538 +#define PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK (u32)(0x200)
1539 +#define PRCM_CM_FCLKEN1_CORE_EN_GPT7_OFFSET (u32)(9)
1540 +
1541 +#define PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK (u32)(0x400)
1542 +#define PRCM_CM_ICLKEN1_CORE_EN_GPT8_OFFSET (u32)(10)
1543 +
1544 +#define PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK (u32)(0x200)
1545 +#define PRCM_CM_ICLKEN1_CORE_EN_GPT7_OFFSET (u32)(9)
1546 +
1547 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK (u32)(0xc000)
1548 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET (u32)(14)
1549 +
1550 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK (u32)(0x3000)
1551 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET (u32)(12)
1552 +
1553 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK (u32)(0xc00)
1554 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET (u32)(10)
1555 +
1556 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK (u32)(0x300)
1557 +#define PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET (u32)(8)
1558 +
1559 +#define PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_MASK (u32)(0x3800000)
1560 +#define PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_OFFSET (u32)(23)
1561 +
1562 +#define PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK (u32)(0x2)
1563 +#define PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_OFFSET (u32)(1)
1564 +
1565 +#define PRCM_CM_IDLEST_DSP_ST_IPI_MASK (u32)(0x2)
1566 +#define PRCM_CM_IDLEST_DSP_ST_IPI_OFFSET (u32)(1)
1567 +
1568 +#define PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK (u32)(0x2)
1569 +#define PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_OFFSET (u32)(1)
1570 +
1571 +#define PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK (u32)(0x80)
1572 +#define PRCM_CM_CLKSEL_DSP_SYNC_DSP_OFFSET (u32)(7)
1573 +
1574 +#define PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK (u32)(0x60)
1575 +#define PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_OFFSET (u32)(5)
1576 +
1577 +#define PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK (u32)(0x1f)
1578 +#define PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_OFFSET (u32)(0)
1579 +
1580 +#define PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK (u32)(0x1)
1581 +#define PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET (u32)(0)
1582 +
1583 +#define PRCM_PM_PWSTCTRL_DSP_ForceState_MASK (u32)(0x40000)
1584 +#define PRCM_PM_PWSTCTRL_DSP_ForceState_OFFSET (u32)(18)
1585 +
1586 +#define PRCM_PM_PWSTCTRL_DSP_PowerState_MASK (u32)(0x3)
1587 +#define PRCM_PM_PWSTCTRL_DSP_PowerState_OFFSET (u32)(0)
1588 +
1589 +#define PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK (u32)(0x3)
1590 +#define PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET (u32)(0)
1591 +
1592 +#define PRCM_PM_PWSTST_DSP_InTransition_MASK (u32)(0x100000)
1593 +#define PRCM_PM_PWSTST_DSP_InTransition_OFFSET (u32)(20)
1594 +
1595 +#define PRCM_PM_PWSTST_IVA2_InTransition_MASK (u32)(0x100000)
1596 +#define PRCM_PM_PWSTST_IVA2_InTransition_OFFSET (u32)(20)
1597 +
1598 +#define PRCM_PM_PWSTST_DSP_PowerStateSt_MASK (u32)(0x3)
1599 +#define PRCM_PM_PWSTST_DSP_PowerStateSt_OFFSET (u32)(0)
1600 +
1601 +#define PRCM_PM_PWSTST_IVA2_PowerStateSt_MASK (u32)(0x3)
1602 +#define PRCM_PM_PWSTST_IVA2_PowerStateSt_OFFSET (u32)(0)
1603 +
1604 +#define CM_FCLKEN_PER_OFFSET (u32)(0x0)
1605 +#define CM_FCLKEN_PER_GPT5_OFFSET (u32)(6)
1606 +#define CM_FCLKEN_PER_GPT5_MASK (u32)(0x40)
1607 +
1608 +#define CM_FCLKEN_PER_GPT6_OFFSET (u32)(7)
1609 +#define CM_FCLKEN_PER_GPT6_MASK (u32)(0x80)
1610 +
1611 +#define CM_ICLKEN_PER_OFFSET (u32)(0x10)
1612 +#define CM_ICLKEN_PER_GPT5_OFFSET (u32)(6)
1613 +#define CM_ICLKEN_PER_GPT5_MASK (u32)(0x40)
1614 +
1615 +#define CM_ICLKEN_PER_GPT6_OFFSET (u32)(7)
1616 +#define CM_ICLKEN_PER_GPT6_MASK (u32)(0x80)
1617 +
1618 +#define CM_CLKSEL_PER_GPT5_OFFSET (u32)(3)
1619 +#define CM_CLKSEL_PER_GPT5_MASK (u32)(0x8)
1620 +
1621 +#define CM_CLKSEL_PER_GPT6_OFFSET (u32)(4)
1622 +#define CM_CLKSEL_PER_GPT6_MASK (u32)(0x10)
1623 +
1624 +
1625 +#define CM_FCLKEN_IVA2_OFFSET (u32)(0x0)
1626 +#define CM_FCLKEN_IVA2_EN_MASK (u32)(0x1)
1627 +#define CM_FCLKEN_IVA2_EN_OFFSET (u32)(0x0)
1628 +
1629 +#define CM_IDLEST_IVA2_OFFSET (u32)(0x20)
1630 +#define CM_IDLEST_IVA2_ST_IVA2_MASK (u32) (0x01)
1631 +#define CM_IDLEST_IVA2_ST_IVA2_OFFSET (u32) (0x00)
1632 +
1633 +#define CM_FCLKEN1_CORE_OFFSET (u32)(0xA00)
1634 +
1635 +#define CM_ICLKEN1_CORE_OFFSET (u32)(0xA10)
1636 +#define CM_ICLKEN1_CORE_EN_MAILBOXES_MASK (u32)(0x00000080) /* bit 7 */
1637 +#define CM_ICLKEN1_CORE_EN_MAILBOXES_OFFSET (u32)(7)
1638 +
1639 +#define CM_CLKSTCTRL_IVA2_OFFSET (u32)(0x0)
1640 +#define CM_CLKSTCTRL_IVA2_MASK (u32)(0x3)
1641 +
1642 +
1643 +#define PRM_RSTCTRL_IVA2_OFFSET (u32)(0x50)
1644 +#define PRM_RSTCTRL_IVA2_RST1_MASK (u32)(0x1)
1645 +#define PRM_RSTCTRL_IVA2_RST1_OFFSET (u32)(0x0)
1646 +#define PRM_RSTCTRL_IVA2_RST2_MASK (u32)(0x2)
1647 +#define PRM_RSTCTRL_IVA2_RST2_OFFSET (u32)(0x1)
1648 +#define PRM_RSTCTRL_IVA2_RST3_MASK (u32)(0x4)
1649 +#define PRM_RSTCTRL_IVA2_RST3_OFFSET (u32)(0x2)
1650 +
1651 +
1652 +/* The following represent the enumerated values for each bitfield */
1653 +
1654 +enum PRCMPRCM_CLKCFG_CTRLValid_configE {
1655 + PRCMPRCM_CLKCFG_CTRLValid_configUpdated = 0x0000,
1656 + PRCMPRCM_CLKCFG_CTRLValid_configClk_valid = 0x0001
1657 +} ;
1658 +
1659 +enum PRCMCM_CLKSEL2_CORECLKSEL_GPT8E {
1660 + PRCMCM_CLKSEL2_CORECLKSEL_GPT832k = 0x0000,
1661 + PRCMCM_CLKSEL2_CORECLKSEL_GPT8Sys = 0x0001,
1662 + PRCMCM_CLKSEL2_CORECLKSEL_GPT8Ext = 0x0002,
1663 + PRCMCM_CLKSEL2_CORECLKSEL_GPT8Reserved = 0x0003
1664 +} ;
1665 +
1666 +enum PRCMCM_CLKSEL2_CORECLKSEL_GPT7E {
1667 + PRCMCM_CLKSEL2_CORECLKSEL_GPT732k = 0x0000,
1668 + PRCMCM_CLKSEL2_CORECLKSEL_GPT7Sys = 0x0001,
1669 + PRCMCM_CLKSEL2_CORECLKSEL_GPT7Ext = 0x0002,
1670 + PRCMCM_CLKSEL2_CORECLKSEL_GPT7Reserved = 0x0003
1671 +} ;
1672 +
1673 +enum PRCMCM_CLKSEL2_CORECLKSEL_GPT6E {
1674 + PRCMCM_CLKSEL2_CORECLKSEL_GPT632k = 0x0000,
1675 + PRCMCM_CLKSEL2_CORECLKSEL_GPT6Sys = 0x0001,
1676 + PRCMCM_CLKSEL2_CORECLKSEL_GPT6Ext = 0x0002,
1677 + PRCMCM_CLKSEL2_CORECLKSEL_GPT6Reserved = 0x0003
1678 +} ;
1679 +
1680 +enum PRCMCM_CLKSEL2_CORECLKSEL_GPT5E {
1681 + PRCMCM_CLKSEL2_CORECLKSEL_GPT532k = 0x0000,
1682 + PRCMCM_CLKSEL2_CORECLKSEL_GPT5Sys = 0x0001,
1683 + PRCMCM_CLKSEL2_CORECLKSEL_GPT5Ext = 0x0002,
1684 + PRCMCM_CLKSEL2_CORECLKSEL_GPT5Reserved = 0x0003
1685 +} ;
1686 +
1687 +enum PRCMPM_PWSTCTRL_DSPPowerStateE {
1688 + PRCMPM_PWSTCTRL_DSPPowerStateON = 0x0000,
1689 + PRCMPM_PWSTCTRL_DSPPowerStateRET = 0x0001,
1690 + PRCMPM_PWSTCTRL_DSPPowerStateReserved = 0x0002,
1691 + PRCMPM_PWSTCTRL_DSPPowerStateOFF = 0x0003
1692 +} ;
1693 +
1694 +enum PRCMPM_PWSTCTRL_IVA2PowerStateE {
1695 + PRCMPM_PWSTCTRL_IVA2PowerStateON = 0x0003,
1696 + PRCMPM_PWSTCTRL_IVA2PowerStateRET = 0x0001,
1697 + PRCMPM_PWSTCTRL_IVA2PowerStateReserved = 0x0002,
1698 + PRCMPM_PWSTCTRL_IVA2PowerStateOFF = 0x0000
1699 +} ;
1700 +
1701 +#endif /* _PRCM_ACC_INT_H */
1702 Index: lk/drivers/dsp/bridge/hw/PRCMRegAcM.h
1703 ===================================================================
1704 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
1705 +++ lk/drivers/dsp/bridge/hw/PRCMRegAcM.h 2008-08-18 10:38:36.000000000 +0300
1706 @@ -0,0 +1,669 @@
1707 +/*
1708 + * linux/drivers/dsp/bridge/hw/omap3/prcm/PRCMRegAcM.h
1709 + *
1710 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
1711 + *
1712 + * Copyright (C) 2007 Texas Instruments, Inc.
1713 + *
1714 + * This package is free software; you can redistribute it and/or modify
1715 + * it under the terms of the GNU General Public License version 2 as
1716 + * published by the Free Software Foundation.
1717 + *
1718 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
1719 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
1720 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
1721 + */
1722 +
1723 +#ifndef _PRCM_REG_ACM_H
1724 +#define _PRCM_REG_ACM_H
1725 +
1726 +#include <GlobalTypes.h>
1727 +
1728 +#include <EasiGlobal.h>
1729 +
1730 +#include "PRCMAccInt.h"
1731 +
1732 +#if defined(USE_LEVEL_1_MACROS)
1733 +
1734 +#define PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32(baseAddress)\
1735 +{\
1736 + const u32 offset = PRCM_PRCM_CLKCFG_CTRL_OFFSET;\
1737 + const u32 newValue = \
1738 + (u32)PRCMPRCM_CLKCFG_CTRLValid_configClk_valid <<\
1739 + PRCM_PRCM_CLKCFG_CTRL_Valid_config_OFFSET;\
1740 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1741 + _DEBUG_LEVEL_1_EASI(\
1742 + EASIL1_PRCMPRCM_CLKCFG_CTRLValid_configWriteClk_valid32);\
1743 + data &= ~(PRCM_PRCM_CLKCFG_CTRL_Valid_config_MASK);\
1744 + data |= newValue;\
1745 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1746 +}
1747 +
1748 +
1749 +#define CM_FCLKEN_PERReadRegister32(baseAddress)\
1750 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\
1751 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_FCLKEN_PER_OFFSET))
1752 +
1753 +
1754 +#define CM_ICLKEN_PERReadRegister32(baseAddress)\
1755 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\
1756 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_ICLKEN_PER_OFFSET))
1757 +
1758 +
1759 +#define CM_FCLKEN_PER_GPT5WriteRegister32(baseAddress,value)\
1760 +{\
1761 + const u32 offset = CM_FCLKEN_PER_OFFSET;\
1762 + register u32 data = \
1763 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1764 + register u32 newValue = ((u32)(value));\
1765 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32);\
1766 + data &= ~(CM_FCLKEN_PER_GPT5_MASK);\
1767 + newValue <<= CM_FCLKEN_PER_GPT5_OFFSET;\
1768 + newValue &= CM_FCLKEN_PER_GPT5_MASK;\
1769 + newValue |= data;\
1770 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1771 +}
1772 +
1773 +
1774 +#define CM_FCLKEN_PER_GPT6WriteRegister32(baseAddress,value)\
1775 +{\
1776 + const u32 offset = CM_FCLKEN_PER_OFFSET;\
1777 + register u32 data =\
1778 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1779 + register u32 newValue = ((u32)(value));\
1780 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_FCLKEN_PER_GPT5WriteRegister32);\
1781 + data &= ~(CM_FCLKEN_PER_GPT6_MASK);\
1782 + newValue <<= CM_FCLKEN_PER_GPT6_OFFSET;\
1783 + newValue &= CM_FCLKEN_PER_GPT6_MASK;\
1784 + newValue |= data;\
1785 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1786 +}
1787 +
1788 +
1789 +#define CM_ICLKEN_PER_GPT5WriteRegister32(baseAddress,value)\
1790 +{\
1791 + const u32 offset = CM_ICLKEN_PER_OFFSET;\
1792 + register u32 data = \
1793 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1794 + register u32 newValue = ((u32)(value));\
1795 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32);\
1796 + data &= ~(CM_ICLKEN_PER_GPT5_MASK);\
1797 + newValue <<= CM_ICLKEN_PER_GPT5_OFFSET;\
1798 + newValue &= CM_ICLKEN_PER_GPT5_MASK;\
1799 + newValue |= data;\
1800 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1801 +}
1802 +
1803 +
1804 +#define CM_ICLKEN_PER_GPT6WriteRegister32(baseAddress,value)\
1805 +{\
1806 + const u32 offset = CM_ICLKEN_PER_OFFSET;\
1807 + register u32 data = \
1808 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1809 + register u32 newValue = ((u32)(value));\
1810 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_ICLKEN_PER_GPT5WriteRegister32);\
1811 + data &= ~(CM_ICLKEN_PER_GPT6_MASK);\
1812 + newValue <<= CM_ICLKEN_PER_GPT6_OFFSET;\
1813 + newValue &= CM_ICLKEN_PER_GPT6_MASK;\
1814 + newValue |= data;\
1815 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
1816 +}
1817 +
1818 +
1819 +#define CM_FCLKEN1_COREReadRegister32(baseAddress)\
1820 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREReadRegister32),\
1821 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_FCLKEN1_CORE_OFFSET))
1822 +
1823 +
1824 +#define PRCMCM_FCLKEN1_COREEN_GPT8Write32(baseAddress,value)\
1825 +{\
1826 + const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\
1827 + register u32 data = \
1828 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1829 + register u32 newValue = ((u32)(value));\
1830 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT8Write32);\
1831 + data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK);\
1832 + newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT8_OFFSET;\
1833 + newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT8_MASK;\
1834 + newValue |= data;\
1835 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1836 +}
1837 +
1838 +
1839 +#define PRCMCM_FCLKEN1_COREEN_GPT7Write32(baseAddress,value)\
1840 +{\
1841 + const u32 offset = PRCM_CM_FCLKEN1_CORE_OFFSET;\
1842 + register u32 data = \
1843 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1844 + register u32 newValue = ((u32)(value));\
1845 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN1_COREEN_GPT7Write32);\
1846 + data &= ~(PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK);\
1847 + newValue <<= PRCM_CM_FCLKEN1_CORE_EN_GPT7_OFFSET;\
1848 + newValue &= PRCM_CM_FCLKEN1_CORE_EN_GPT7_MASK;\
1849 + newValue |= data;\
1850 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1851 +}
1852 +
1853 +
1854 +#define CM_ICLKEN1_COREReadRegister32(baseAddress)\
1855 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREReadRegister32),\
1856 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+CM_ICLKEN1_CORE_OFFSET))
1857 +
1858 +
1859 +#define CM_ICLKEN1_COREEN_MAILBOXESWrite32(baseAddress, value)\
1860 +{\
1861 + const u32 offset = CM_ICLKEN1_CORE_OFFSET;\
1862 + register u32 data = \
1863 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1864 + register u32 newValue = ((u32)(value));\
1865 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_MAILBOXESWrite32);\
1866 + data &= ~(CM_ICLKEN1_CORE_EN_MAILBOXES_MASK);\
1867 + newValue <<= CM_ICLKEN1_CORE_EN_MAILBOXES_OFFSET;\
1868 + newValue &= CM_ICLKEN1_CORE_EN_MAILBOXES_MASK;\
1869 + newValue |= data;\
1870 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1871 +}
1872 +
1873 +
1874 +#define PRCMCM_ICLKEN1_COREEN_GPT8Write32(baseAddress, value)\
1875 +{\
1876 + const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET;\
1877 + register u32 data = \
1878 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1879 + register u32 newValue = ((u32)(value));\
1880 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT8Write32);\
1881 + data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK);\
1882 + newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT8_OFFSET;\
1883 + newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT8_MASK;\
1884 + newValue |= data;\
1885 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1886 +}
1887 +
1888 +
1889 +#define PRCMCM_ICLKEN1_COREEN_GPT7Write32(baseAddress, value)\
1890 +{\
1891 + const u32 offset = PRCM_CM_ICLKEN1_CORE_OFFSET;\
1892 + register u32 data =\
1893 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
1894 + register u32 newValue = ((u32)(value));\
1895 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN1_COREEN_GPT7Write32);\
1896 + data &= ~(PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK);\
1897 + newValue <<= PRCM_CM_ICLKEN1_CORE_EN_GPT7_OFFSET;\
1898 + newValue &= PRCM_CM_ICLKEN1_CORE_EN_GPT7_MASK;\
1899 + newValue |= data;\
1900 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
1901 +}
1902 +
1903 +
1904 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32(baseAddress)\
1905 +{\
1906 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1907 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT832k <<\
1908 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\
1909 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1910 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8Write32k32);\
1911 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\
1912 + data |= newValue;\
1913 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1914 +}
1915 +
1916 +
1917 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32(baseAddress)\
1918 +{\
1919 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1920 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Sys <<\
1921 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\
1922 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1923 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteSys32);\
1924 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\
1925 + data |= newValue;\
1926 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1927 +}
1928 +
1929 +
1930 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32(baseAddress)\
1931 +{\
1932 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1933 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT8Ext <<\
1934 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_OFFSET;\
1935 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1936 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT8WriteExt32);\
1937 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT8_MASK);\
1938 + data |= newValue;\
1939 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1940 +}
1941 +
1942 +
1943 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32(baseAddress)\
1944 +{\
1945 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1946 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT732k <<\
1947 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\
1948 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1949 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7Write32k32);\
1950 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\
1951 + data |= newValue;\
1952 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1953 +}
1954 +
1955 +
1956 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32(baseAddress)\
1957 +{\
1958 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1959 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Sys <<\
1960 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\
1961 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1962 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteSys32);\
1963 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\
1964 + data |= newValue;\
1965 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1966 +}
1967 +
1968 +
1969 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32(baseAddress)\
1970 +{\
1971 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1972 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT7Ext <<\
1973 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_OFFSET;\
1974 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1975 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT7WriteExt32);\
1976 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT7_MASK);\
1977 + data |= newValue;\
1978 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1979 +}
1980 +
1981 +
1982 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32(baseAddress)\
1983 +{\
1984 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1985 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Sys <<\
1986 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET;\
1987 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
1988 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteSys32);\
1989 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK);\
1990 + data |= newValue;\
1991 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
1992 +}
1993 +
1994 +
1995 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32(baseAddress)\
1996 +{\
1997 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
1998 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT6Ext <<\
1999 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_OFFSET;\
2000 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2001 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT6WriteExt32);\
2002 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT6_MASK);\
2003 + data |= newValue;\
2004 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2005 +}
2006 +
2007 +
2008 +#define CM_CLKSEL_PER_GPT5Write32k32(baseAddress)\
2009 +{\
2010 + const u32 offset = CM_CLKSEL_PER_OFFSET;\
2011 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k <<\
2012 + CM_CLKSEL_PER_GPT5_OFFSET;\
2013 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2014 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT5Write32k32);\
2015 + data &= ~(CM_CLKSEL_PER_GPT5_MASK);\
2016 + data |= newValue;\
2017 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2018 +}
2019 +
2020 +
2021 +#define CM_CLKSEL_PER_GPT6Write32k32(baseAddress)\
2022 +{\
2023 + const u32 offset = CM_CLKSEL_PER_OFFSET;\
2024 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT532k <<\
2025 + CM_CLKSEL_PER_GPT6_OFFSET;\
2026 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2027 + _DEBUG_LEVEL_1_EASI(EASIL1_CM_CLKSEL_PER_GPT6Write32k32);\
2028 + data &= ~(CM_CLKSEL_PER_GPT6_MASK);\
2029 + data |= newValue;\
2030 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2031 +}
2032 +
2033 +
2034 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32(baseAddress)\
2035 +{\
2036 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
2037 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Sys <<\
2038 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET;\
2039 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2040 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteSys32);\
2041 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK);\
2042 + data |= newValue;\
2043 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2044 +}
2045 +
2046 +
2047 +#define PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32(baseAddress)\
2048 +{\
2049 + const u32 offset = PRCM_CM_CLKSEL2_CORE_OFFSET;\
2050 + const u32 newValue = (u32)PRCMCM_CLKSEL2_CORECLKSEL_GPT5Ext <<\
2051 + PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_OFFSET;\
2052 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2053 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL2_CORECLKSEL_GPT5WriteExt32);\
2054 + data &= ~(PRCM_CM_CLKSEL2_CORE_CLKSEL_GPT5_MASK);\
2055 + data |= newValue;\
2056 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2057 +}
2058 +
2059 +
2060 +#define PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32(baseAddress)\
2061 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL1_PLLAPLLs_ClkinRead32),\
2062 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2063 + (PRCM_CM_CLKSEL1_PLL_OFFSET)))) &\
2064 + PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_MASK) >>\
2065 + PRCM_CM_CLKSEL1_PLL_APLLs_Clkin_OFFSET))
2066 +
2067 +
2068 +#define CM_FCLKEN_IVA2EN_DSPWrite32(baseAddress,value)\
2069 +{\
2070 + const u32 offset = CM_FCLKEN_IVA2_OFFSET;\
2071 + register u32 data = \
2072 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2073 + register u32 newValue = ((u32)(value));\
2074 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_FCLKEN_DSPEN_DSPWrite32);\
2075 + data &= ~(CM_FCLKEN_IVA2_EN_MASK);\
2076 + newValue <<= CM_FCLKEN_IVA2_EN_OFFSET;\
2077 + newValue &= CM_FCLKEN_IVA2_EN_MASK;\
2078 + newValue |= data;\
2079 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2080 +}
2081 +
2082 +
2083 +#define PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32(baseAddress, value)\
2084 +{\
2085 + const u32 offset = PRCM_CM_ICLKEN_DSP_OFFSET;\
2086 + register u32 data = \
2087 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2088 + register u32 newValue = ((u32)(value));\
2089 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_ICLKEN_DSPEN_DSP_IPIWrite32);\
2090 + data &= ~(PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK);\
2091 + newValue <<= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_OFFSET;\
2092 + newValue &= PRCM_CM_ICLKEN_DSP_EN_DSP_IPI_MASK;\
2093 + newValue |= data;\
2094 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2095 +}
2096 +
2097 +
2098 +#define PRCMCM_IDLEST_DSPReadRegister32(baseAddress)\
2099 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPReadRegister32),\
2100 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_CM_IDLEST_DSP_OFFSET))
2101 +
2102 +
2103 +#define PRCMCM_IDLEST_DSPST_IPIRead32(baseAddress)\
2104 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_IPIRead32),\
2105 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2106 + (PRCM_CM_IDLEST_DSP_OFFSET)))) &\
2107 + PRCM_CM_IDLEST_DSP_ST_IPI_MASK) >>\
2108 + PRCM_CM_IDLEST_DSP_ST_IPI_OFFSET))
2109 +
2110 +
2111 +#define PRM_IDLEST_IVA2ST_IVA2Read32(baseAddress)\
2112 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_IDLEST_DSPST_DSPRead32),\
2113 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2114 + (CM_IDLEST_IVA2_OFFSET)))) &\
2115 + CM_IDLEST_IVA2_ST_IVA2_MASK) >>\
2116 + CM_IDLEST_IVA2_ST_IVA2_OFFSET))
2117 +
2118 +
2119 +#define PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32(baseAddress, value)\
2120 +{\
2121 + const u32 offset = PRCM_CM_AUTOIDLE_DSP_OFFSET;\
2122 + register u32 data =\
2123 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2124 + register u32 newValue = ((u32)(value));\
2125 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_AUTOIDLE_DSPAUTO_DSP_IPIWrite32);\
2126 + data &= ~(PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK);\
2127 + newValue <<= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_OFFSET;\
2128 + newValue &= PRCM_CM_AUTOIDLE_DSP_AUTO_DSP_IPI_MASK;\
2129 + newValue |= data;\
2130 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2131 +}
2132 +
2133 +
2134 +#define PRCMCM_CLKSEL_DSPSYNC_DSPWrite32(baseAddress,value)\
2135 +{\
2136 + const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\
2137 + register u32 data = \
2138 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2139 + register u32 newValue = ((u32)(value));\
2140 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPSYNC_DSPWrite32);\
2141 + data &= ~(PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK);\
2142 + newValue <<= PRCM_CM_CLKSEL_DSP_SYNC_DSP_OFFSET;\
2143 + newValue &= PRCM_CM_CLKSEL_DSP_SYNC_DSP_MASK;\
2144 + newValue |= data;\
2145 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2146 +}
2147 +
2148 +
2149 +#define PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32(baseAddress, value)\
2150 +{\
2151 + const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\
2152 + register u32 data = \
2153 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2154 + register u32 newValue = ((u32)(value));\
2155 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSP_IFWrite32);\
2156 + data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK);\
2157 + newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_OFFSET;\
2158 + newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_IF_MASK;\
2159 + newValue |= data;\
2160 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2161 +}
2162 +
2163 +
2164 +#define PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32(baseAddress, value)\
2165 +{\
2166 + const u32 offset = PRCM_CM_CLKSEL_DSP_OFFSET;\
2167 + register u32 data = \
2168 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2169 + register u32 newValue = ((u32)(value));\
2170 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSEL_DSPCLKSEL_DSPWrite32);\
2171 + data &= ~(PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK);\
2172 + newValue <<= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_OFFSET;\
2173 + newValue &= PRCM_CM_CLKSEL_DSP_CLKSEL_DSP_MASK;\
2174 + newValue |= data;\
2175 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2176 +}
2177 +
2178 +
2179 +#define PRCMCM_CLKSTCTRL_IVA2WriteRegister32(baseAddress, value)\
2180 +{\
2181 + const u32 offset = PRCM_CM_CLKSTCTRL_IVA2_OFFSET;\
2182 + register u32 data = \
2183 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2184 + register u32 newValue = ((u32)(value));\
2185 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_IVA2WriteRegister32);\
2186 + data &= ~(CM_CLKSTCTRL_IVA2_MASK);\
2187 + newValue <<= CM_CLKSTCTRL_IVA2_OFFSET;\
2188 + newValue &= CM_CLKSTCTRL_IVA2_MASK;\
2189 + newValue |= data;\
2190 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2191 +}
2192 +
2193 +
2194 +#define PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32(baseAddress)\
2195 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPRead32),\
2196 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2197 + (PRCM_CM_CLKSTCTRL_DSP_OFFSET)))) &\
2198 + PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK) >>\
2199 + PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET))
2200 +
2201 +
2202 +#define PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32(baseAddress, value)\
2203 +{\
2204 + const u32 offset = PRCM_CM_CLKSTCTRL_DSP_OFFSET;\
2205 + register u32 data = \
2206 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2207 + register u32 newValue = ((u32)(value));\
2208 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMCM_CLKSTCTRL_DSPAutostate_DSPWrite32);\
2209 + data &= ~(PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK);\
2210 + newValue <<= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_OFFSET;\
2211 + newValue &= PRCM_CM_CLKSTCTRL_DSP_Autostate_DSP_MASK;\
2212 + newValue |= data;\
2213 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2214 +}
2215 +
2216 +
2217 +#define PRCMRM_RSTCTRL_DSPReadRegister32(baseAddress)\
2218 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPReadRegister32),\
2219 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_RM_RSTCTRL_DSP_OFFSET))
2220 +
2221 +
2222 +#define PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress,value)\
2223 +{\
2224 + const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\
2225 + register u32 data =\
2226 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2227 + register u32 newValue = ((u32)(value));\
2228 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\
2229 + data &= ~(PRM_RSTCTRL_IVA2_RST1_MASK);\
2230 + newValue <<= PRM_RSTCTRL_IVA2_RST1_OFFSET;\
2231 + newValue &= PRM_RSTCTRL_IVA2_RST1_MASK;\
2232 + newValue |= data;\
2233 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2234 +}
2235 +
2236 +
2237 +#define PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress,value)\
2238 +{\
2239 + const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\
2240 + register u32 data =\
2241 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2242 + register u32 newValue = ((u32)(value));\
2243 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\
2244 + data &= ~(PRM_RSTCTRL_IVA2_RST2_MASK);\
2245 + newValue <<= PRM_RSTCTRL_IVA2_RST2_OFFSET;\
2246 + newValue &= PRM_RSTCTRL_IVA2_RST2_MASK;\
2247 + newValue |= data;\
2248 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2249 +}
2250 +
2251 +
2252 +#define PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress,value)\
2253 +{\
2254 + const u32 offset = PRM_RSTCTRL_IVA2_OFFSET;\
2255 + register u32 data =\
2256 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2257 + register u32 newValue = ((u32)(value));\
2258 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTCTRL_DSPRST1_DSPWrite32);\
2259 + data &= ~(PRM_RSTCTRL_IVA2_RST3_MASK);\
2260 + newValue <<= PRM_RSTCTRL_IVA2_RST3_OFFSET;\
2261 + newValue &= PRM_RSTCTRL_IVA2_RST3_MASK;\
2262 + newValue |= data;\
2263 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2264 +}
2265 +
2266 +
2267 +#define PRCMRM_RSTST_DSPReadRegister32(baseAddress)\
2268 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPReadRegister32),\
2269 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_RM_RSTST_DSP_OFFSET))
2270 +
2271 +
2272 +#define PRCMRM_RSTST_DSPWriteRegister32(baseAddress,value)\
2273 +{\
2274 + const u32 offset = PRCM_RM_RSTST_DSP_OFFSET;\
2275 + register u32 newValue = ((u32)(value));\
2276 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMRM_RSTST_DSPWriteRegister32);\
2277 + WR_MEM_32_VOLATILE(((u32)(baseAddress))+offset, newValue);\
2278 +}
2279 +
2280 +
2281 +#define PRCMPM_PWSTCTRL_DSPForceStateWrite32(baseAddress, value)\
2282 +{\
2283 + const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET;\
2284 + register u32 data = \
2285 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+offset);\
2286 + register u32 newValue = ((u32)(value));\
2287 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPForceStateWrite32);\
2288 + data &= ~(PRCM_PM_PWSTCTRL_DSP_ForceState_MASK);\
2289 + newValue <<= PRCM_PM_PWSTCTRL_DSP_ForceState_OFFSET;\
2290 + newValue &= PRCM_PM_PWSTCTRL_DSP_ForceState_MASK;\
2291 + newValue |= data;\
2292 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, newValue);\
2293 +}
2294 +
2295 +
2296 +#define PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32(baseAddress)\
2297 +{\
2298 + const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET;\
2299 + const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateON <<\
2300 + PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET;\
2301 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2302 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32);\
2303 + data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK);\
2304 + data |= newValue;\
2305 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2306 +}
2307 +
2308 +
2309 +#define PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32(baseAddress)\
2310 +{\
2311 + const u32 offset = PRCM_PM_PWSTCTRL_IVA2_OFFSET;\
2312 + const u32 newValue = (u32)PRCMPM_PWSTCTRL_IVA2PowerStateOFF <<\
2313 + PRCM_PM_PWSTCTRL_IVA2_PowerState_OFFSET;\
2314 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2315 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32);\
2316 + data &= ~(PRCM_PM_PWSTCTRL_IVA2_PowerState_MASK);\
2317 + data |= newValue;\
2318 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2319 +}
2320 +
2321 +
2322 +#define PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32(baseAddress)\
2323 +{\
2324 + const u32 offset = PRCM_PM_PWSTCTRL_DSP_OFFSET;\
2325 + const u32 newValue = (u32)PRCMPM_PWSTCTRL_DSPPowerStateRET <<\
2326 + PRCM_PM_PWSTCTRL_DSP_PowerState_OFFSET;\
2327 + register u32 data = RD_MEM_32_VOLATILE((u32)(baseAddress)+offset);\
2328 + _DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32);\
2329 + data &= ~(PRCM_PM_PWSTCTRL_DSP_PowerState_MASK);\
2330 + data |= newValue;\
2331 + WR_MEM_32_VOLATILE((u32)(baseAddress)+offset, data);\
2332 +}
2333 +
2334 +
2335 +#define PRCMPM_PWSTST_DSPReadRegister32(baseAddress)\
2336 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPReadRegister32),\
2337 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_PM_PWSTST_DSP_OFFSET))
2338 +
2339 +
2340 +#define PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress)\
2341 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2ReadRegister32),\
2342 + RD_MEM_32_VOLATILE(((u32)(baseAddress))+PRCM_PM_PWSTST_IVA2_OFFSET))
2343 +
2344 +
2345 +#define PRCMPM_PWSTST_DSPInTransitionRead32(baseAddress)\
2346 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPInTransitionRead32),\
2347 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2348 + (PRCM_PM_PWSTST_DSP_OFFSET)))) &\
2349 + PRCM_PM_PWSTST_DSP_InTransition_MASK) >>\
2350 + PRCM_PM_PWSTST_DSP_InTransition_OFFSET))
2351 +
2352 +
2353 +#define PRCMPM_PWSTST_IVA2InTransitionRead32(baseAddress)\
2354 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2InTransitionRead32),\
2355 + (((RD_MEM_32_VOLATILE((((u32)(baseAddress))+\
2356 + (PRCM_PM_PWSTST_IVA2_OFFSET)))) &\
2357 + PRCM_PM_PWSTST_IVA2_InTransition_MASK) >>\
2358 + PRCM_PM_PWSTST_IVA2_InTransition_OFFSET))
2359 +
2360 +
2361 +#define PRCMPM_PWSTST_DSPPowerStateStGet32(var)\
2362 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_DSPPowerStateStGet32),\
2363 + (u32)((((u32)(var)) & PRCM_PM_PWSTST_DSP_PowerStateSt_MASK) >>\
2364 + PRCM_PM_PWSTST_DSP_PowerStateSt_OFFSET))
2365 +
2366 +
2367 +#define PRCMPM_PWSTST_IVA2PowerStateStGet32(var)\
2368 + (_DEBUG_LEVEL_1_EASI(EASIL1_PRCMPM_PWSTST_IVA2PowerStateStGet32),\
2369 + (u32)((((u32)(var)) & PRCM_PM_PWSTST_IVA2_PowerStateSt_MASK) >>\
2370 + PRCM_PM_PWSTST_IVA2_PowerStateSt_OFFSET))
2371 +
2372 +
2373 +#endif /* USE_LEVEL_1_MACROS */
2374 +
2375 +#endif /* _PRCM_REG_ACM_H */
2376 Index: lk/drivers/dsp/bridge/hw/hw_defs.h
2377 ===================================================================
2378 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2379 +++ lk/drivers/dsp/bridge/hw/hw_defs.h 2008-08-18 10:38:36.000000000 +0300
2380 @@ -0,0 +1,73 @@
2381 +/*
2382 + * linux/drivers/dsp/bridge/hw/common/inc/hw_defs.h
2383 + *
2384 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2385 + *
2386 + * Copyright (C) 2007 Texas Instruments, Inc.
2387 + *
2388 + * This package is free software; you can redistribute it and/or modify
2389 + * it under the terms of the GNU General Public License version 2 as
2390 + * published by the Free Software Foundation.
2391 + *
2392 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2393 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2394 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2395 + */
2396 +
2397 +
2398 +/*
2399 + * ======== hw_defs.h ========
2400 + * Description:
2401 + * Global HW definitions
2402 + *
2403 + *! Revision History:
2404 + *! ================
2405 + *! 19 Apr 2004 sb: Added generic page size, endianness and element size defns
2406 + *! 16 Feb 2003 sb: Initial version
2407 + */
2408 +#ifndef __HW_DEFS_H
2409 +#define __HW_DEFS_H
2410 +
2411 +#include <GlobalTypes.h>
2412 +
2413 +/* Page size */
2414 +#define HW_PAGE_SIZE_4KB 0x1000
2415 +#define HW_PAGE_SIZE_64KB 0x10000
2416 +#define HW_PAGE_SIZE_1MB 0x100000
2417 +#define HW_PAGE_SIZE_16MB 0x1000000
2418 +
2419 +/* HW_STATUS: return type for HW API */
2420 +typedef long HW_STATUS;
2421 +
2422 +/* HW_SetClear_t: Enumerated Type used to set and clear any bit */
2423 +enum HW_SetClear_t {
2424 + HW_CLEAR,
2425 + HW_SET
2426 +} ;
2427 +
2428 +/* HW_Endianism_t: Enumerated Type used to specify the endianism
2429 + * Do NOT change these values. They are used as bit fields. */
2430 +enum HW_Endianism_t {
2431 + HW_LITTLE_ENDIAN,
2432 + HW_BIG_ENDIAN
2433 +
2434 +} ;
2435 +
2436 +/* HW_ElementSize_t: Enumerated Type used to specify the element size
2437 + * Do NOT change these values. They are used as bit fields. */
2438 +enum HW_ElementSize_t {
2439 + HW_ELEM_SIZE_8BIT,
2440 + HW_ELEM_SIZE_16BIT,
2441 + HW_ELEM_SIZE_32BIT,
2442 + HW_ELEM_SIZE_64BIT
2443 +
2444 +} ;
2445 +
2446 +/* HW_IdleMode_t: Enumerated Type used to specify Idle modes */
2447 + enum HW_IdleMode_t {
2448 + HW_FORCE_IDLE,
2449 + HW_NO_IDLE,
2450 + HW_SMART_IDLE
2451 + } ;
2452 +
2453 +#endif /* __HW_DEFS_H */
2454 Index: lk/drivers/dsp/bridge/hw/hw_dspssC64P.c
2455 ===================================================================
2456 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2457 +++ lk/drivers/dsp/bridge/hw/hw_dspssC64P.c 2008-08-18 10:38:36.000000000 +0300
2458 @@ -0,0 +1,55 @@
2459 +/*
2460 + * linux/drivers/dsp/bridge/hw/omap3/dspss/hw_dspss64P.c
2461 + *
2462 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2463 + *
2464 + * Copyright (C) 2005-2006 Texas Instruments, Inc.
2465 + *
2466 + * This package is free software; you can redistribute it and/or modify
2467 + * it under the terms of the GNU General Public License version 2 as
2468 + * published by the Free Software Foundation.
2469 + *
2470 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2471 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2472 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2473 + */
2474 +
2475 +/*
2476 + * ======== hw_dspss64P.c ========
2477 + * Description:
2478 + * API definitions to configure DSP Subsystem modules like IPI
2479 + *
2480 + *! Revision History:
2481 + *! ================
2482 + *! 19 Apr 2004 sb: Implemented HW_DSPSS_IPIEndianismSet
2483 + *! 16 Feb 2003 sb: Initial version
2484 + */
2485 +
2486 +/* PROJECT SPECIFIC INCLUDE FILES */
2487 +#include <GlobalTypes.h>
2488 +#include <hw_defs.h>
2489 +#include <hw_dspssC64P.h>
2490 +#include <IVA2RegAcM.h>
2491 +#include <IPIAccInt.h>
2492 +
2493 +/* HW FUNCTIONS */
2494 +HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
2495 + enum HW_DSPSYSC_BootMode_t bootMode,
2496 + const u32 bootAddress)
2497 +{
2498 + HW_STATUS status = RET_OK;
2499 + u32 offset = SYSC_IVA2BOOTMOD_OFFSET;
2500 + u32 alignedBootAddr;
2501 +
2502 + /* if Boot mode it DIRECT BOOT, check that the bootAddress is
2503 + * aligned to atleast 1K :: TODO */
2504 + WR_MEM_32_VOLATILE((baseAddress) + offset, bootMode);
2505 +
2506 + offset = SYSC_IVA2BOOTADDR_OFFSET;
2507 +
2508 + alignedBootAddr = bootAddress & SYSC_IVA2BOOTADDR_MASK;
2509 +
2510 + WR_MEM_32_VOLATILE((baseAddress) + offset, alignedBootAddr);
2511 +
2512 + return status;
2513 +}
2514 Index: lk/drivers/dsp/bridge/hw/hw_dspssC64P.h
2515 ===================================================================
2516 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2517 +++ lk/drivers/dsp/bridge/hw/hw_dspssC64P.h 2008-08-18 10:38:36.000000000 +0300
2518 @@ -0,0 +1,48 @@
2519 +/*
2520 + * linux/drivers/dsp/bridge/hw/omap3/inc/hw_dspssC64P.h
2521 + *
2522 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2523 + *
2524 + * Copyright (C) 2005-2006 Texas Instruments, Inc.
2525 + *
2526 + * This package is free software; you can redistribute it and/or modify
2527 + * it under the terms of the GNU General Public License version 2 as
2528 + * published by the Free Software Foundation.
2529 + *
2530 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2531 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2532 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2533 + */
2534 +
2535 +
2536 +/*
2537 + * ======== hw_dspss.h ========
2538 + * Description:
2539 + * DSP Subsystem API declarations
2540 + *
2541 + *! Revision History:
2542 + *! ================
2543 + *! 19-Apr-2004 sb: Removed redundant argument from HW_DSPSS_IPIEndianismSet
2544 + *! Moved endianness and element size to generic hw_defs.h
2545 + *! 16 Feb 2003 sb: Initial version
2546 + */
2547 +
2548 +#ifndef __HW_DSPSS_H
2549 +#define __HW_DSPSS_H
2550 +#include <linux/types.h>
2551 +
2552 + enum HW_DSPSYSC_BootMode_t {
2553 + HW_DSPSYSC_DIRECTBOOT = 0x0,
2554 + HW_DSPSYSC_IDLEBOOT = 0x1,
2555 + HW_DSPSYSC_SELFLOOPBOOT = 0x2,
2556 + HW_DSPSYSC_USRBOOTSTRAP = 0x3,
2557 + HW_DSPSYSC_DEFAULTRESTORE = 0x4
2558 + } ;
2559 +
2560 +#define HW_DSP_IDLEBOOT_ADDR 0x007E0000
2561 +
2562 + extern HW_STATUS HW_DSPSS_BootModeSet(const u32 baseAddress,
2563 + enum HW_DSPSYSC_BootMode_t bootMode,
2564 + const u32 bootAddress);
2565 +
2566 +#endif /* __HW_DSPSS_H */
2567 Index: lk/drivers/dsp/bridge/hw/hw_mbox.c
2568 ===================================================================
2569 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2570 +++ lk/drivers/dsp/bridge/hw/hw_mbox.c 2008-08-18 10:38:36.000000000 +0300
2571 @@ -0,0 +1,255 @@
2572 +/*
2573 + * linux/drivers/dsp/bridge/hw/omap3/mbox/hw_mbox.c
2574 + *
2575 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2576 + *
2577 + * Copyright (C) 2007 Texas Instruments, Inc.
2578 + *
2579 + * This package is free software; you can redistribute it and/or modify
2580 + * it under the terms of the GNU General Public License version 2 as
2581 + * published by the Free Software Foundation.
2582 + *
2583 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2584 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2585 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2586 + */
2587 +
2588 +
2589 +/*
2590 + * ======== hw_mbox.c ========
2591 + * Description:
2592 + * Mailbox messaging & configuration API definitions
2593 + *
2594 + *! Revision History:
2595 + *! ================
2596 + *! 16 Feb 2003 sb: Initial version
2597 + */
2598 +
2599 +#include <GlobalTypes.h>
2600 +#include "MLBRegAcM.h"
2601 +#include <hw_defs.h>
2602 +#include <hw_mbox.h>
2603 +
2604 +/* width in bits of MBOX Id */
2605 +#define HW_MBOX_ID_WIDTH 2
2606 +
2607 +struct MAILBOX_CONTEXT mboxsetting = {0, 0, 0};
2608 +
2609 +/* Saves the mailbox context */
2610 +HW_STATUS HW_MBOX_saveSettings(u32 baseAddress)
2611 +{
2612 + HW_STATUS status = RET_OK;
2613 +
2614 + mboxsetting.sysconfig = MLBMAILBOX_SYSCONFIGReadRegister32(baseAddress);
2615 + /* Get current enable status */
2616 + mboxsetting.irqEnable0 = MLBMAILBOX_IRQENABLE___0_3ReadRegister32
2617 + (baseAddress, HW_MBOX_U0_ARM);
2618 + mboxsetting.irqEnable1 = MLBMAILBOX_IRQENABLE___0_3ReadRegister32
2619 + (baseAddress, HW_MBOX_U1_DSP1);
2620 + return status;
2621 +}
2622 +
2623 +/* Restores the mailbox context */
2624 +HW_STATUS HW_MBOX_restoreSettings(u32 baseAddress)
2625 +{
2626 + HW_STATUS status = RET_OK;
2627 + /* Restor IRQ enable status */
2628 + MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, HW_MBOX_U0_ARM,
2629 + mboxsetting.irqEnable0);
2630 + MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, HW_MBOX_U1_DSP1,
2631 + mboxsetting.irqEnable1);
2632 + /* Restore Sysconfig register */
2633 + MLBMAILBOX_SYSCONFIGWriteRegister32(baseAddress, mboxsetting.sysconfig);
2634 + return status;
2635 +}
2636 +
2637 +/* Reads a u32 from the sub module message box Specified. if there are no
2638 + * messages in the mailbox then and error is returned. */
2639 +HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2640 + u32 *const pReadValue)
2641 +{
2642 + HW_STATUS status = RET_OK;
2643 +
2644 + /* Check input parameters */
2645 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2646 + RES_INVALID_INPUT_PARAM);
2647 + CHECK_INPUT_PARAM(pReadValue, NULL, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2648 + RES_INVALID_INPUT_PARAM);
2649 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2650 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2651 +
2652 + /* Read 32-bit message in mail box */
2653 + *pReadValue = MLBMAILBOX_MESSAGE___0_15ReadRegister32(baseAddress,
2654 + (u32)mailBoxId);
2655 +
2656 + return status;
2657 +}
2658 +
2659 +/* Writes a u32 from the sub module message box Specified. */
2660 +HW_STATUS HW_MBOX_MsgWrite(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2661 + const u32 writeValue)
2662 +{
2663 + HW_STATUS status = RET_OK;
2664 +
2665 + /* Check input parameters */
2666 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2667 + RES_INVALID_INPUT_PARAM);
2668 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2669 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2670 +
2671 + /* Write 32-bit value to mailbox */
2672 + MLBMAILBOX_MESSAGE___0_15WriteRegister32(baseAddress, (u32)mailBoxId,
2673 + (u32)writeValue);
2674 +
2675 + return status;
2676 +}
2677 +
2678 +/* Reads the full status register for mailbox. */
2679 +HW_STATUS HW_MBOX_IsFull(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2680 + u32 *const pIsFull)
2681 +{
2682 + HW_STATUS status = RET_OK;
2683 + u32 fullStatus;
2684 +
2685 + /* Check input parameters */
2686 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2687 + RES_INVALID_INPUT_PARAM);
2688 + CHECK_INPUT_PARAM(pIsFull, NULL, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2689 + RES_INVALID_INPUT_PARAM);
2690 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2691 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2692 +
2693 + /* read the is full status parameter for Mailbox */
2694 + fullStatus = MLBMAILBOX_FIFOSTATUS___0_15FifoFullMBmRead32(baseAddress,
2695 + (u32)mailBoxId);
2696 +
2697 + /* fill in return parameter */
2698 + *pIsFull = (fullStatus & 0xFF);
2699 +
2700 + return status;
2701 +}
2702 +
2703 +/* Gets number of messages in a specified mailbox. */
2704 +HW_STATUS HW_MBOX_NumMsgGet(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2705 + u32 *const pNumMsg)
2706 +{
2707 + HW_STATUS status = RET_OK;
2708 +
2709 + /* Check input parameters */
2710 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2711 + RES_INVALID_INPUT_PARAM);
2712 + CHECK_INPUT_PARAM(pNumMsg, NULL, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2713 + RES_INVALID_INPUT_PARAM);
2714 +
2715 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2716 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2717 +
2718 + /* Get number of messages available for MailBox */
2719 + *pNumMsg = MLBMAILBOX_MSGSTATUS___0_15NbOfMsgMBmRead32(baseAddress,
2720 + (u32)mailBoxId);
2721 +
2722 + return status;
2723 +}
2724 +
2725 +/* Enables the specified IRQ. */
2726 +HW_STATUS HW_MBOX_EventEnable(const u32 baseAddress,
2727 + const HW_MBOX_Id_t mailBoxId,
2728 + const HW_MBOX_UserId_t userId,
2729 + const u32 events)
2730 +{
2731 + HW_STATUS status = RET_OK;
2732 + u32 irqEnableReg;
2733 +
2734 + /* Check input parameters */
2735 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2736 + RES_INVALID_INPUT_PARAM);
2737 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2738 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2739 + CHECK_INPUT_RANGE_MIN0(enableIrq, HW_MBOX_INT_MAX, RET_INVALID_ID,
2740 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2741 + CHECK_INPUT_RANGE_MIN0(userId, HW_MBOX_USER_MAX, RET_INVALID_ID,
2742 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2743 +
2744 + /* Get current enable status */
2745 + irqEnableReg = MLBMAILBOX_IRQENABLE___0_3ReadRegister32(baseAddress,
2746 + (u32)userId);
2747 +
2748 + /* update enable value */
2749 + irqEnableReg |= ((u32)(events)) << (((u32)(mailBoxId)) *
2750 + HW_MBOX_ID_WIDTH);
2751 +
2752 + /* write new enable status */
2753 + MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, (u32)userId,
2754 + (u32)irqEnableReg);
2755 +
2756 + mboxsetting.sysconfig = MLBMAILBOX_SYSCONFIGReadRegister32(baseAddress);
2757 + /* Get current enable status */
2758 + mboxsetting.irqEnable0 = MLBMAILBOX_IRQENABLE___0_3ReadRegister32
2759 + (baseAddress, HW_MBOX_U0_ARM);
2760 + mboxsetting.irqEnable1 = MLBMAILBOX_IRQENABLE___0_3ReadRegister32
2761 + (baseAddress, HW_MBOX_U1_DSP1);
2762 + return status;
2763 +}
2764 +
2765 +/* Disables the specified IRQ. */
2766 +HW_STATUS HW_MBOX_EventDisable(const u32 baseAddress,
2767 + const HW_MBOX_Id_t mailBoxId,
2768 + const HW_MBOX_UserId_t userId,
2769 + const u32 events)
2770 +{
2771 + HW_STATUS status = RET_OK;
2772 + u32 irqDisableReg;
2773 +
2774 + /* Check input parameters */
2775 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2776 + RES_INVALID_INPUT_PARAM);
2777 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2778 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2779 + CHECK_INPUT_RANGE_MIN0(disableIrq, HW_MBOX_INT_MAX, RET_INVALID_ID,
2780 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2781 + CHECK_INPUT_RANGE_MIN0(userId, HW_MBOX_USER_MAX, RET_INVALID_ID,
2782 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2783 +
2784 + /* Get current enable status */
2785 + irqDisableReg = MLBMAILBOX_IRQENABLE___0_3ReadRegister32(baseAddress,
2786 + (u32)userId);
2787 +
2788 + /* update enable value */
2789 + irqDisableReg &= ~((u32)(events)) << (((u32)(mailBoxId)) *
2790 + HW_MBOX_ID_WIDTH);
2791 +
2792 + /* write new enable status */
2793 + MLBMAILBOX_IRQENABLE___0_3WriteRegister32(baseAddress, (u32)userId,
2794 + (u32)irqDisableReg);
2795 +
2796 + return status;
2797 +}
2798 +
2799 +/* Sets the status of the specified IRQ. */
2800 +HW_STATUS HW_MBOX_EventAck(const u32 baseAddress, const HW_MBOX_Id_t mailBoxId,
2801 + const HW_MBOX_UserId_t userId, const u32 event)
2802 +{
2803 + HW_STATUS status = RET_OK;
2804 + u32 irqStatusReg;
2805 +
2806 + /* Check input parameters */
2807 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM, RES_MBOX_BASE +
2808 + RES_INVALID_INPUT_PARAM);
2809 +
2810 + CHECK_INPUT_RANGE_MIN0(irqStatus, HW_MBOX_INT_MAX, RET_INVALID_ID,
2811 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2812 + CHECK_INPUT_RANGE_MIN0(mailBoxId, HW_MBOX_ID_MAX, RET_INVALID_ID,
2813 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2814 + CHECK_INPUT_RANGE_MIN0(userId, HW_MBOX_USER_MAX, RET_INVALID_ID,
2815 + RES_MBOX_BASE + RES_INVALID_INPUT_PARAM);
2816 +
2817 + /* calculate status to write */
2818 + irqStatusReg = ((u32)event) << (((u32)(mailBoxId)) *
2819 + HW_MBOX_ID_WIDTH);
2820 +
2821 + /* clear Irq Status for specified mailbox/User Id */
2822 + MLBMAILBOX_IRQSTATUS___0_3WriteRegister32(baseAddress, (u32)userId,
2823 + (u32)irqStatusReg);
2824 +
2825 + return status;
2826 +}
2827 Index: lk/drivers/dsp/bridge/hw/hw_mbox.h
2828 ===================================================================
2829 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
2830 +++ lk/drivers/dsp/bridge/hw/hw_mbox.h 2008-08-18 10:38:36.000000000 +0300
2831 @@ -0,0 +1,358 @@
2832 +/*
2833 + * linux/drivers/dsp/bridge/hw/omap3/inc/hw_mbox.h
2834 + *
2835 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
2836 + *
2837 + * Copyright (C) 2007 Texas Instruments, Inc.
2838 + *
2839 + * This package is free software; you can redistribute it and/or modify
2840 + * it under the terms of the GNU General Public License version 2 as
2841 + * published by the Free Software Foundation.
2842 + *
2843 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
2844 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
2845 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
2846 + */
2847 +
2848 +/*
2849 + * ======== hw_mbox.h ========
2850 + * Description:
2851 + * HW Mailbox API and types definitions
2852 + *
2853 + *! Revision History:
2854 + *! ================
2855 + *! 16 Feb 2003 sb: Initial version
2856 + */
2857 +#ifndef __MBOX_H
2858 +#define __MBOX_H
2859 +
2860 +/* Bitmasks for Mailbox interrupt sources */
2861 +#define HW_MBOX_INT_NEW_MSG 0x1
2862 +#define HW_MBOX_INT_NOT_FULL 0x2
2863 +#define HW_MBOX_INT_ALL 0x3
2864 +
2865 +/* Maximum number of messages that mailbox can hald at a time. */
2866 +#define HW_MBOX_MAX_NUM_MESSAGES 4
2867 +
2868 +/* HW_MBOX_Id_t: Enumerated Type used to specify Mailbox Sub Module Id Number */
2869 +typedef enum HW_MBOX_Id_label {
2870 + HW_MBOX_ID_0,
2871 + HW_MBOX_ID_1,
2872 + HW_MBOX_ID_2,
2873 + HW_MBOX_ID_3,
2874 + HW_MBOX_ID_4,
2875 + HW_MBOX_ID_5
2876 +
2877 +} HW_MBOX_Id_t, *pHW_MBOX_Id_t;
2878 +
2879 +/* HW_MBOX_UserId_t: Enumerated Type used to specify Mail box User Id */
2880 +typedef enum HW_MBOX_UserId_label {
2881 + HW_MBOX_U0_ARM,
2882 + HW_MBOX_U1_DSP1,
2883 + HW_MBOX_U2_DSP2,
2884 + HW_MBOX_U3_ARM
2885 +
2886 +} HW_MBOX_UserId_t, *pHW_MBOX_UserId_t;
2887 +
2888 +/* Mailbox context settings */
2889 +struct MAILBOX_CONTEXT {
2890 + u32 sysconfig;
2891 + u32 irqEnable0;
2892 + u32 irqEnable1;
2893 +};
2894 +
2895 +/*
2896 +* FUNCTION : HW_MBOX_MsgRead
2897 +*
2898 +* INPUTS:
2899 +*
2900 +* Identifier : baseAddress
2901 +* Type : const u32
2902 +* Description : Base Address of instance of Mailbox module
2903 +*
2904 +* Identifier : mailBoxId
2905 +* Type : const HW_MBOX_Id_t
2906 +* Description : Mail Box Sub module Id to read
2907 +*
2908 +* OUTPUTS:
2909 +*
2910 +* Identifier : pReadValue
2911 +* Type : u32 *const
2912 +* Description : Value read from MailBox
2913 +*
2914 +* RETURNS:
2915 +*
2916 +* Type : ReturnCode_t
2917 +* Description : RET_OK No errors occured
2918 +* RET_BAD_NULL_PARAM Address/ptr Paramater was set to 0/NULL
2919 +* RET_INVALID_ID Invalid Id used
2920 +* RET_EMPTY Mailbox empty
2921 +*
2922 +* PURPOSE: : this function reads a u32 from the sub module message
2923 +* box Specified. if there are no messages in the mailbox
2924 +* then and error is returned.
2925 +*/
2926 +extern HW_STATUS HW_MBOX_MsgRead(const u32 baseAddress,
2927 + const HW_MBOX_Id_t mailBoxId,
2928 + u32 *const pReadValue);
2929 +
2930 +/*
2931 +* FUNCTION : HW_MBOX_MsgWrite
2932 +*
2933 +* INPUTS:
2934 +*
2935 +* Identifier : baseAddress
2936 +* Type : const u32
2937 +* Description : Base Address of instance of Mailbox module
2938 +*
2939 +* Identifier : mailBoxId
2940 +* Type : const HW_MBOX_Id_t
2941 +* Description : Mail Box Sub module Id to write
2942 +*
2943 +* Identifier : writeValue
2944 +* Type : const u32
2945 +* Description : Value to write to MailBox
2946 +*
2947 +* RETURNS:
2948 +*
2949 +* Type : ReturnCode_t
2950 +* Description : RET_OK No errors occured
2951 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
2952 +* RET_INVALID_ID Invalid Id used
2953 +*
2954 +* PURPOSE: : this function writes a u32 from the sub module message
2955 +* box Specified.
2956 +*/
2957 +extern HW_STATUS HW_MBOX_MsgWrite(
2958 + const u32 baseAddress,
2959 + const HW_MBOX_Id_t mailBoxId,
2960 + const u32 writeValue
2961 + );
2962 +
2963 +/*
2964 +* FUNCTION : HW_MBOX_IsFull
2965 +*
2966 +* INPUTS:
2967 +*
2968 +* Identifier : baseAddress
2969 +* Type : const u32
2970 +* Description : Base Address of instance of Mailbox module
2971 +*
2972 +* Identifier : mailBoxId
2973 +* Type : const HW_MBOX_Id_t
2974 +* Description : Mail Box Sub module Id to check
2975 +*
2976 +* OUTPUTS:
2977 +*
2978 +* Identifier : pIsFull
2979 +* Type : u32 *const
2980 +* Description : false means mail box not Full
2981 +* true means mailbox full.
2982 +*
2983 +* RETURNS:
2984 +*
2985 +* Type : ReturnCode_t
2986 +* Description : RET_OK No errors occured
2987 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
2988 +* RET_INVALID_ID Invalid Id used
2989 +*
2990 +* PURPOSE: : this function reads the full status register for mailbox.
2991 +*/
2992 +extern HW_STATUS HW_MBOX_IsFull(
2993 + const u32 baseAddress,
2994 + const HW_MBOX_Id_t mailBoxId,
2995 + u32 *const pIsFull
2996 + );
2997 +
2998 +/*
2999 +* FUNCTION : HW_MBOX_NumMsgGet
3000 +*
3001 +* INPUTS:
3002 +*
3003 +* Identifier : baseAddress
3004 +* Type : const u32
3005 +* Description : Base Address of instance of Mailbox module
3006 +*
3007 +* Identifier : mailBoxId
3008 +* Type : const HW_MBOX_Id_t
3009 +* Description : Mail Box Sub module Id to get num messages
3010 +*
3011 +* OUTPUTS:
3012 +*
3013 +* Identifier : pNumMsg
3014 +* Type : u32 *const
3015 +* Description : Number of messages in mailbox
3016 +*
3017 +* RETURNS:
3018 +*
3019 +* Type : ReturnCode_t
3020 +* Description : RET_OK No errors occured
3021 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3022 +* RET_INVALID_ID Inavlid ID input at parameter
3023 +*
3024 +* PURPOSE: : this function gets number of messages in a specified mailbox.
3025 +*/
3026 +extern HW_STATUS HW_MBOX_NumMsgGet(
3027 + const u32 baseAddress,
3028 + const HW_MBOX_Id_t mailBoxId,
3029 + u32 *const pNumMsg
3030 + );
3031 +
3032 +/*
3033 +* FUNCTION : HW_MBOX_EventEnable
3034 +*
3035 +* INPUTS:
3036 +*
3037 +* Identifier : baseAddress
3038 +* Type : const u32
3039 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3040 +*
3041 +* Identifier : mailBoxId
3042 +* Type : const HW_MBOX_Id_t
3043 +* Description : Mail Box Sub module Id to enable
3044 +*
3045 +* Identifier : userId
3046 +* Type : const HW_MBOX_UserId_t
3047 +* Description : Mail box User Id to enable
3048 +*
3049 +* Identifier : enableIrq
3050 +* Type : const u32
3051 +* Description : Irq value to enable
3052 +*
3053 +* RETURNS:
3054 +*
3055 +* Type : ReturnCode_t
3056 +* Description : RET_OK No errors occured
3057 +* RET_BAD_NULL_PARAM A Pointer Paramater was set to NULL
3058 +* RET_INVALID_ID Invalid Id used
3059 +*
3060 +* PURPOSE: : this function enables the specified IRQ.
3061 +*/
3062 +extern HW_STATUS HW_MBOX_EventEnable(
3063 + const u32 baseAddress,
3064 + const HW_MBOX_Id_t mailBoxId,
3065 + const HW_MBOX_UserId_t userId,
3066 + const u32 events
3067 + );
3068 +
3069 +/*
3070 +* FUNCTION : HW_MBOX_EventDisable
3071 +*
3072 +* INPUTS:
3073 +*
3074 +* Identifier : baseAddress
3075 +* Type : const u32
3076 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3077 +*
3078 +* Identifier : mailBoxId
3079 +* Type : const HW_MBOX_Id_t
3080 +* Description : Mail Box Sub module Id to disable
3081 +*
3082 +* Identifier : userId
3083 +* Type : const HW_MBOX_UserId_t
3084 +* Description : Mail box User Id to disable
3085 +*
3086 +* Identifier : enableIrq
3087 +* Type : const u32
3088 +* Description : Irq value to disable
3089 +*
3090 +* RETURNS:
3091 +*
3092 +* Type : ReturnCode_t
3093 +* Description : RET_OK No errors occured
3094 +* RET_BAD_NULL_PARAM A Pointer Paramater was set to NULL
3095 +* RET_INVALID_ID Invalid Id used
3096 +*
3097 +* PURPOSE: : this function disables the specified IRQ.
3098 +*/
3099 +extern HW_STATUS HW_MBOX_EventDisable(
3100 + const u32 baseAddress,
3101 + const HW_MBOX_Id_t mailBoxId,
3102 + const HW_MBOX_UserId_t userId,
3103 + const u32 events
3104 + );
3105 +
3106 +/*
3107 +* FUNCTION : HW_MBOX_EventAck
3108 +*
3109 +* INPUTS:
3110 +*
3111 +* Identifier : baseAddress
3112 +* Type : const u32
3113 +* Description : Base Address of instance of Mailbox module
3114 +*
3115 +* Identifier : mailBoxId
3116 +* Type : const HW_MBOX_Id_t
3117 +* Description : Mail Box Sub module Id to set
3118 +*
3119 +* Identifier : userId
3120 +* Type : const HW_MBOX_UserId_t
3121 +* Description : Mail box User Id to set
3122 +*
3123 +* Identifier : irqStatus
3124 +* Type : const u32
3125 +* Description : The value to write IRQ status
3126 +*
3127 +* OUTPUTS:
3128 +*
3129 +* RETURNS:
3130 +*
3131 +* Type : ReturnCode_t
3132 +* Description : RET_OK No errors occured
3133 +* RET_BAD_NULL_PARAM Address Paramater was set to 0
3134 +* RET_INVALID_ID Invalid Id used
3135 +*
3136 +* PURPOSE: : this function sets the status of the specified IRQ.
3137 +*/
3138 +extern HW_STATUS HW_MBOX_EventAck(
3139 + const u32 baseAddress,
3140 + const HW_MBOX_Id_t mailBoxId,
3141 + const HW_MBOX_UserId_t userId,
3142 + const u32 event
3143 + );
3144 +
3145 +/*
3146 +* FUNCTION : HW_MBOX_saveSettings
3147 +*
3148 +* INPUTS:
3149 +*
3150 +* Identifier : baseAddress
3151 +* Type : const u32
3152 +* Description : Base Address of instance of Mailbox module
3153 +*
3154 +*
3155 +* RETURNS:
3156 +*
3157 +* Type : ReturnCode_t
3158 +* Description : RET_OK No errors occured
3159 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3160 +* RET_INVALID_ID Invalid Id used
3161 +* RET_EMPTY Mailbox empty
3162 +*
3163 +* PURPOSE: : this function saves the context of mailbox
3164 +*/
3165 +extern HW_STATUS HW_MBOX_saveSettings(u32 baseAddres);
3166 +
3167 +/*
3168 +* FUNCTION : HW_MBOX_restoreSettings
3169 +*
3170 +* INPUTS:
3171 +*
3172 +* Identifier : baseAddress
3173 +* Type : const u32
3174 +* Description : Base Address of instance of Mailbox module
3175 +*
3176 +*
3177 +* RETURNS:
3178 +*
3179 +* Type : ReturnCode_t
3180 +* Description : RET_OK No errors occured
3181 +* RET_BAD_NULL_PARAM Address/pointer Paramater was set to 0/NULL
3182 +* RET_INVALID_ID Invalid Id used
3183 +* RET_EMPTY Mailbox empty
3184 +*
3185 +* PURPOSE: : this function restores the context of mailbox
3186 +*/
3187 +extern HW_STATUS HW_MBOX_restoreSettings(u32 baseAddres);
3188 +
3189 +#endif /* __MBOX_H */
3190 Index: lk/drivers/dsp/bridge/hw/hw_mmu.c
3191 ===================================================================
3192 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3193 +++ lk/drivers/dsp/bridge/hw/hw_mmu.c 2008-08-18 10:38:36.000000000 +0300
3194 @@ -0,0 +1,607 @@
3195 +/*
3196 + * linux/drivers/dsp/bridge/hw/omap3/mmu/hw_mmu.c
3197 + *
3198 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
3199 + *
3200 + * Copyright (C) 2007 Texas Instruments, Inc.
3201 + *
3202 + * This package is free software; you can redistribute it and/or modify
3203 + * it under the terms of the GNU General Public License version 2 as
3204 + * published by the Free Software Foundation.
3205 + *
3206 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
3207 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
3208 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
3209 + */
3210 +
3211 +/*
3212 + * ======== hw_mmu.c ========
3213 + * Description:
3214 + * API definitions to setup MMU TLB and PTE
3215 + *
3216 + *! Revision History:
3217 + *! ================
3218 + *! 19-Apr-2004 sb TLBAdd and TLBFlush input the page size in bytes instead
3219 + of an enum. TLBAdd inputs mapping attributes struct instead
3220 + of individual arguments.
3221 + Removed MMU.h and other cosmetic updates.
3222 + *! 08-Mar-2004 sb Added the Page Table Management APIs
3223 + *! 16 Feb 2003 sb: Initial version
3224 + */
3225 +
3226 +#include <GlobalTypes.h>
3227 +#include "MMURegAcM.h"
3228 +#include <hw_defs.h>
3229 +#include <hw_mmu.h>
3230 +#include <linux/types.h>
3231 +
3232 +#define MMU_BASE_VAL_MASK 0xFC00
3233 +#define MMU_PAGE_MAX 3
3234 +#define MMU_ELEMENTSIZE_MAX 3
3235 +#define MMU_ADDR_MASK 0xFFFFF000
3236 +#define MMU_TTB_MASK 0xFFFFC000
3237 +#define MMU_SECTION_ADDR_MASK 0xFFF00000
3238 +#define MMU_SSECTION_ADDR_MASK 0xFF000000
3239 +#define MMU_PAGE_TABLE_MASK 0xFFFFFC00
3240 +#define MMU_LARGE_PAGE_MASK 0xFFFF0000
3241 +#define MMU_SMALL_PAGE_MASK 0xFFFFF000
3242 +
3243 +#define MMU_LOAD_TLB 0x00000001
3244 +
3245 +/* HW_MMUPageSize_t: Enumerated Type used to specify the MMU Page Size(SLSS) */
3246 +enum HW_MMUPageSize_t {
3247 + HW_MMU_SECTION,
3248 + HW_MMU_LARGE_PAGE,
3249 + HW_MMU_SMALL_PAGE,
3250 + HW_MMU_SUPERSECTION
3251 +} ;
3252 +
3253 +/*
3254 +* FUNCTION : MMU_FlushEntry
3255 +*
3256 +* INPUTS:
3257 +*
3258 +* Identifier : baseAddress
3259 +* Type : const u32
3260 +* Description : Base Address of instance of MMU module
3261 +*
3262 +* RETURNS:
3263 +*
3264 +* Type : HW_STATUS
3265 +* Description : RET_OK -- No errors occured
3266 +* RET_BAD_NULL_PARAM -- A Pointer
3267 +* Paramater was set to NULL
3268 +*
3269 +* PURPOSE: : Flush the TLB entry pointed by the
3270 +* lock counter register
3271 +* even if this entry is set protected
3272 +*
3273 +* METHOD: : Check the Input parameter and Flush a
3274 +* single entry in the TLB.
3275 +*/
3276 +static HW_STATUS MMU_FlushEntry(const u32 baseAddress);
3277 +
3278 +/*
3279 +* FUNCTION : MMU_SetCAMEntry
3280 +*
3281 +* INPUTS:
3282 +*
3283 +* Identifier : baseAddress
3284 +* TypE : const u32
3285 +* Description : Base Address of instance of MMU module
3286 +*
3287 +* Identifier : pageSize
3288 +* TypE : const u32
3289 +* Description : It indicates the page size
3290 +*
3291 +* Identifier : preservedBit
3292 +* Type : const u32
3293 +* Description : It indicates the TLB entry is preserved entry
3294 +* or not
3295 +*
3296 +* Identifier : validBit
3297 +* Type : const u32
3298 +* Description : It indicates the TLB entry is valid entry or not
3299 +*
3300 +*
3301 +* Identifier : virtualAddrTag
3302 +* Type : const u32
3303 +* Description : virtual Address
3304 +*
3305 +* RETURNS:
3306 +*
3307 +* Type : HW_STATUS
3308 +* Description : RET_OK -- No errors occured
3309 +* RET_BAD_NULL_PARAM -- A Pointer Paramater
3310 +* was set to NULL
3311 +* RET_PARAM_OUT_OF_RANGE -- Input Parameter out
3312 +* of Range
3313 +*
3314 +* PURPOSE: : Set MMU_CAM reg
3315 +*
3316 +* METHOD: : Check the Input parameters and set the CAM entry.
3317 +*/
3318 +static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
3319 + const u32 pageSize,
3320 + const u32 preservedBit,
3321 + const u32 validBit,
3322 + const u32 virtualAddrTag);
3323 +
3324 +/*
3325 +* FUNCTION : MMU_SetRAMEntry
3326 +*
3327 +* INPUTS:
3328 +*
3329 +* Identifier : baseAddress
3330 +* Type : const u32
3331 +* Description : Base Address of instance of MMU module
3332 +*
3333 +* Identifier : physicalAddr
3334 +* Type : const u32
3335 +* Description : Physical Address to which the corresponding
3336 +* virtual Address shouldpoint
3337 +*
3338 +* Identifier : endianism
3339 +* Type : HW_Endianism_t
3340 +* Description : endianism for the given page
3341 +*
3342 +* Identifier : elementSize
3343 +* Type : HW_ElementSize_t
3344 +* Description : The element size ( 8,16, 32 or 64 bit)
3345 +*
3346 +* Identifier : mixedSize
3347 +* Type : HW_MMUMixedSize_t
3348 +* Description : Element Size to follow CPU or TLB
3349 +*
3350 +* RETURNS:
3351 +*
3352 +* Type : HW_STATUS
3353 +* Description : RET_OK -- No errors occured
3354 +* RET_BAD_NULL_PARAM -- A Pointer Paramater
3355 +* was set to NULL
3356 +* RET_PARAM_OUT_OF_RANGE -- Input Parameter
3357 +* out of Range
3358 +*
3359 +* PURPOSE: : Set MMU_CAM reg
3360 +*
3361 +* METHOD: : Check the Input parameters and set the RAM entry.
3362 +*/
3363 +static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
3364 + const u32 physicalAddr,
3365 + enum HW_Endianism_t endianism,
3366 + enum HW_ElementSize_t elementSize,
3367 + enum HW_MMUMixedSize_t mixedSize);
3368 +
3369 +/* HW FUNCTIONS */
3370 +
3371 +HW_STATUS HW_MMU_Enable(const u32 baseAddress)
3372 +{
3373 + HW_STATUS status = RET_OK;
3374 +
3375 + MMUMMU_CNTLMMUEnableWrite32(baseAddress, HW_SET);
3376 +
3377 + return status;
3378 +}
3379 +
3380 +HW_STATUS HW_MMU_Disable(const u32 baseAddress)
3381 +{
3382 + HW_STATUS status = RET_OK;
3383 +
3384 + MMUMMU_CNTLMMUEnableWrite32(baseAddress, HW_CLEAR);
3385 +
3386 + return status;
3387 +}
3388 +
3389 +HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
3390 + u32 numLockedEntries)
3391 +{
3392 + HW_STATUS status = RET_OK;
3393 +
3394 + MMUMMU_LOCKBaseValueWrite32(baseAddress, numLockedEntries);
3395 +
3396 + return status;
3397 +}
3398 +
3399 +HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
3400 + u32 victimEntryNum)
3401 +{
3402 + HW_STATUS status = RET_OK;
3403 +
3404 + MMUMMU_LOCKCurrentVictimWrite32(baseAddress, victimEntryNum);
3405 +
3406 + return status;
3407 +}
3408 +
3409 +HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress)
3410 +{
3411 + HW_STATUS status = RET_OK;
3412 +
3413 + MMUMMU_GFLUSHGlobalFlushWrite32(baseAddress, HW_SET);
3414 +
3415 + return status;
3416 +}
3417 +
3418 +HW_STATUS HW_MMU_EventAck(const u32 baseAddress, u32 irqMask)
3419 +{
3420 + HW_STATUS status = RET_OK;
3421 +
3422 + MMUMMU_IRQSTATUSWriteRegister32(baseAddress, irqMask);
3423 +
3424 + return status;
3425 +}
3426 +
3427 +HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
3428 + u32 irqMask)
3429 +{
3430 + HW_STATUS status = RET_OK;
3431 + u32 irqReg;
3432 +
3433 + irqReg = MMUMMU_IRQENABLEReadRegister32(baseAddress);
3434 +
3435 + MMUMMU_IRQENABLEWriteRegister32(baseAddress, irqReg & ~irqMask);
3436 +
3437 + return status;
3438 +}
3439 +
3440 +HW_STATUS HW_MMU_EventEnable(const u32 baseAddress, u32 irqMask)
3441 +{
3442 + HW_STATUS status = RET_OK;
3443 + u32 irqReg;
3444 +
3445 + irqReg = MMUMMU_IRQENABLEReadRegister32(baseAddress);
3446 +
3447 + MMUMMU_IRQENABLEWriteRegister32(baseAddress, irqReg | irqMask);
3448 +
3449 + return status;
3450 +}
3451 +
3452 +
3453 +HW_STATUS HW_MMU_EventStatus(const u32 baseAddress, u32 *irqMask)
3454 +{
3455 + HW_STATUS status = RET_OK;
3456 +
3457 + *irqMask = MMUMMU_IRQSTATUSReadRegister32(baseAddress);
3458 +
3459 + return status;
3460 +}
3461 +
3462 +
3463 +HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress, u32 *addr)
3464 +{
3465 + HW_STATUS status = RET_OK;
3466 +
3467 + /*Check the input Parameters*/
3468 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3469 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3470 +
3471 + /* read values from register */
3472 + *addr = MMUMMU_FAULT_ADReadRegister32(baseAddress);
3473 +
3474 + return status;
3475 +}
3476 +
3477 +HW_STATUS HW_MMU_TTBSet(const u32 baseAddress, u32 TTBPhysAddr)
3478 +{
3479 + HW_STATUS status = RET_OK;
3480 + u32 loadTTB;
3481 +
3482 + /*Check the input Parameters*/
3483 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3484 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3485 +
3486 + loadTTB = TTBPhysAddr & ~0x7FUL;
3487 + /* write values to register */
3488 + MMUMMU_TTBWriteRegister32(baseAddress, loadTTB);
3489 +
3490 + return status;
3491 +}
3492 +
3493 +HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress)
3494 +{
3495 + HW_STATUS status = RET_OK;
3496 +
3497 + MMUMMU_CNTLTWLEnableWrite32(baseAddress, HW_SET);
3498 +
3499 + return status;
3500 +}
3501 +
3502 +HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress)
3503 +{
3504 + HW_STATUS status = RET_OK;
3505 +
3506 + MMUMMU_CNTLTWLEnableWrite32(baseAddress, HW_CLEAR);
3507 +
3508 + return status;
3509 +}
3510 +
3511 +HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress, u32 virtualAddr,
3512 + u32 pageSize)
3513 +{
3514 + HW_STATUS status = RET_OK;
3515 + u32 virtualAddrTag;
3516 + enum HW_MMUPageSize_t pgSizeBits;
3517 +
3518 + switch (pageSize) {
3519 + case HW_PAGE_SIZE_4KB:
3520 + pgSizeBits = HW_MMU_SMALL_PAGE;
3521 + break;
3522 +
3523 + case HW_PAGE_SIZE_64KB:
3524 + pgSizeBits = HW_MMU_LARGE_PAGE;
3525 + break;
3526 +
3527 + case HW_PAGE_SIZE_1MB:
3528 + pgSizeBits = HW_MMU_SECTION;
3529 + break;
3530 +
3531 + case HW_PAGE_SIZE_16MB:
3532 + pgSizeBits = HW_MMU_SUPERSECTION;
3533 + break;
3534 +
3535 + default:
3536 + return RET_FAIL;
3537 + }
3538 +
3539 + /* Generate the 20-bit tag from virtual address */
3540 + virtualAddrTag = ((virtualAddr & MMU_ADDR_MASK) >> 12);
3541 +
3542 + MMU_SetCAMEntry(baseAddress, pgSizeBits, 0, 0, virtualAddrTag);
3543 +
3544 + MMU_FlushEntry(baseAddress);
3545 +
3546 + return status;
3547 +}
3548 +
3549 +HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
3550 + u32 physicalAddr,
3551 + u32 virtualAddr,
3552 + u32 pageSize,
3553 + u32 entryNum,
3554 + struct HW_MMUMapAttrs_t *mapAttrs,
3555 + enum HW_SetClear_t preservedBit,
3556 + enum HW_SetClear_t validBit)
3557 +{
3558 + HW_STATUS status = RET_OK;
3559 + u32 lockReg;
3560 + u32 virtualAddrTag;
3561 + enum HW_MMUPageSize_t mmuPgSize;
3562 +
3563 + /*Check the input Parameters*/
3564 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3565 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3566 + CHECK_INPUT_RANGE_MIN0(pageSize, MMU_PAGE_MAX, RET_PARAM_OUT_OF_RANGE,
3567 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3568 + CHECK_INPUT_RANGE_MIN0(mapAttrs->elementSize, MMU_ELEMENTSIZE_MAX,
3569 + RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE +
3570 + RES_INVALID_INPUT_PARAM);
3571 +
3572 + switch (pageSize) {
3573 + case HW_PAGE_SIZE_4KB:
3574 + mmuPgSize = HW_MMU_SMALL_PAGE;
3575 + break;
3576 +
3577 + case HW_PAGE_SIZE_64KB:
3578 + mmuPgSize = HW_MMU_LARGE_PAGE;
3579 + break;
3580 +
3581 + case HW_PAGE_SIZE_1MB:
3582 + mmuPgSize = HW_MMU_SECTION;
3583 + break;
3584 +
3585 + case HW_PAGE_SIZE_16MB:
3586 + mmuPgSize = HW_MMU_SUPERSECTION;
3587 + break;
3588 +
3589 + default:
3590 + return RET_FAIL;
3591 + }
3592 +
3593 + lockReg = MMUMMU_LOCKReadRegister32(baseAddress);
3594 +
3595 + /* Generate the 20-bit tag from virtual address */
3596 + virtualAddrTag = ((virtualAddr & MMU_ADDR_MASK) >> 12);
3597 +
3598 + /* Write the fields in the CAM Entry Register */
3599 + MMU_SetCAMEntry(baseAddress, mmuPgSize, preservedBit, validBit,
3600 + virtualAddrTag);
3601 +
3602 + /* Write the different fields of the RAM Entry Register */
3603 + /* endianism of the page,Element Size of the page (8, 16, 32, 64 bit)*/
3604 + MMU_SetRAMEntry(baseAddress, physicalAddr, mapAttrs->endianism,
3605 + mapAttrs->elementSize, mapAttrs->mixedSize);
3606 +
3607 + /* Update the MMU Lock Register */
3608 + /* currentVictim between lockedBaseValue and (MMU_Entries_Number - 1)*/
3609 + MMUMMU_LOCKCurrentVictimWrite32(baseAddress, entryNum);
3610 +
3611 + /* Enable loading of an entry in TLB by writing 1
3612 + into LD_TLB_REG register */
3613 + MMUMMU_LD_TLBWriteRegister32(baseAddress, MMU_LOAD_TLB);
3614 +
3615 +
3616 + MMUMMU_LOCKWriteRegister32(baseAddress, lockReg);
3617 +
3618 + return status;
3619 +}
3620 +
3621 +HW_STATUS HW_MMU_PteSet(const u32 pgTblVa,
3622 + u32 physicalAddr,
3623 + u32 virtualAddr,
3624 + u32 pageSize,
3625 + struct HW_MMUMapAttrs_t *mapAttrs)
3626 +{
3627 + HW_STATUS status = RET_OK;
3628 + u32 pteAddr, pteVal;
3629 + s32 numEntries = 1;
3630 +
3631 + switch (pageSize) {
3632 + case HW_PAGE_SIZE_4KB:
3633 + pteAddr = HW_MMU_PteAddrL2(pgTblVa,
3634 + virtualAddr & MMU_SMALL_PAGE_MASK);
3635 + pteVal = ((physicalAddr & MMU_SMALL_PAGE_MASK) |
3636 + (mapAttrs->endianism << 9) |
3637 + (mapAttrs->elementSize << 4) |
3638 + (mapAttrs->mixedSize << 11) | 2
3639 + );
3640 + break;
3641 +
3642 + case HW_PAGE_SIZE_64KB:
3643 + numEntries = 16;
3644 + pteAddr = HW_MMU_PteAddrL2(pgTblVa,
3645 + virtualAddr & MMU_LARGE_PAGE_MASK);
3646 + pteVal = ((physicalAddr & MMU_LARGE_PAGE_MASK) |
3647 + (mapAttrs->endianism << 9) |
3648 + (mapAttrs->elementSize << 4) |
3649 + (mapAttrs->mixedSize << 11) | 1
3650 + );
3651 + break;
3652 +
3653 + case HW_PAGE_SIZE_1MB:
3654 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3655 + virtualAddr & MMU_SECTION_ADDR_MASK);
3656 + pteVal = ((((physicalAddr & MMU_SECTION_ADDR_MASK) |
3657 + (mapAttrs->endianism << 15) |
3658 + (mapAttrs->elementSize << 10) |
3659 + (mapAttrs->mixedSize << 17)) &
3660 + ~0x40000) | 0x2
3661 + );
3662 + break;
3663 +
3664 + case HW_PAGE_SIZE_16MB:
3665 + numEntries = 16;
3666 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3667 + virtualAddr & MMU_SSECTION_ADDR_MASK);
3668 + pteVal = (((physicalAddr & MMU_SSECTION_ADDR_MASK) |
3669 + (mapAttrs->endianism << 15) |
3670 + (mapAttrs->elementSize << 10) |
3671 + (mapAttrs->mixedSize << 17)
3672 + ) | 0x40000 | 0x2
3673 + );
3674 + break;
3675 +
3676 + case HW_MMU_COARSE_PAGE_SIZE:
3677 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3678 + virtualAddr & MMU_SECTION_ADDR_MASK);
3679 + pteVal = (physicalAddr & MMU_PAGE_TABLE_MASK) | 1;
3680 + break;
3681 +
3682 + default:
3683 + return RET_FAIL;
3684 + }
3685 +
3686 + while (--numEntries >= 0)
3687 + ((u32 *)pteAddr)[numEntries] = pteVal;
3688 +
3689 + return status;
3690 +}
3691 +
3692 +HW_STATUS HW_MMU_PteClear(const u32 pgTblVa,
3693 + u32 virtualAddr,
3694 + u32 pgSize)
3695 +{
3696 + HW_STATUS status = RET_OK;
3697 + u32 pteAddr;
3698 + s32 numEntries = 1;
3699 +
3700 + switch (pgSize) {
3701 + case HW_PAGE_SIZE_4KB:
3702 + pteAddr = HW_MMU_PteAddrL2(pgTblVa,
3703 + virtualAddr & MMU_SMALL_PAGE_MASK);
3704 + break;
3705 +
3706 + case HW_PAGE_SIZE_64KB:
3707 + numEntries = 16;
3708 + pteAddr = HW_MMU_PteAddrL2(pgTblVa,
3709 + virtualAddr & MMU_LARGE_PAGE_MASK);
3710 + break;
3711 +
3712 + case HW_PAGE_SIZE_1MB:
3713 + case HW_MMU_COARSE_PAGE_SIZE:
3714 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3715 + virtualAddr & MMU_SECTION_ADDR_MASK);
3716 + break;
3717 +
3718 + case HW_PAGE_SIZE_16MB:
3719 + numEntries = 16;
3720 + pteAddr = HW_MMU_PteAddrL1(pgTblVa,
3721 + virtualAddr & MMU_SSECTION_ADDR_MASK);
3722 + break;
3723 +
3724 + default:
3725 + return RET_FAIL;
3726 + }
3727 +
3728 + while (--numEntries >= 0)
3729 + ((u32 *)pteAddr)[numEntries] = 0;
3730 +
3731 + return status;
3732 +}
3733 +
3734 +/* MMU_FlushEntry */
3735 +static HW_STATUS MMU_FlushEntry(const u32 baseAddress)
3736 +{
3737 + HW_STATUS status = RET_OK;
3738 + u32 flushEntryData = 0x1;
3739 +
3740 + /*Check the input Parameters*/
3741 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3742 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3743 +
3744 + /* write values to register */
3745 + MMUMMU_FLUSH_ENTRYWriteRegister32(baseAddress, flushEntryData);
3746 +
3747 + return status;
3748 +}
3749 +
3750 +/* MMU_SetCAMEntry */
3751 +static HW_STATUS MMU_SetCAMEntry(const u32 baseAddress,
3752 + const u32 pageSize,
3753 + const u32 preservedBit,
3754 + const u32 validBit,
3755 + const u32 virtualAddrTag)
3756 +{
3757 + HW_STATUS status = RET_OK;
3758 + u32 mmuCamReg;
3759 +
3760 + /*Check the input Parameters*/
3761 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3762 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3763 +
3764 + mmuCamReg = (virtualAddrTag << 12);
3765 + mmuCamReg = (mmuCamReg) | (pageSize) | (validBit << 2) |
3766 + (preservedBit << 3) ;
3767 +
3768 + /* write values to register */
3769 + MMUMMU_CAMWriteRegister32(baseAddress, mmuCamReg);
3770 +
3771 + return status;
3772 +}
3773 +
3774 +/* MMU_SetRAMEntry */
3775 +static HW_STATUS MMU_SetRAMEntry(const u32 baseAddress,
3776 + const u32 physicalAddr,
3777 + enum HW_Endianism_t endianism,
3778 + enum HW_ElementSize_t elementSize,
3779 + enum HW_MMUMixedSize_t mixedSize)
3780 +{
3781 + HW_STATUS status = RET_OK;
3782 + u32 mmuRamReg;
3783 +
3784 + /*Check the input Parameters*/
3785 + CHECK_INPUT_PARAM(baseAddress, 0, RET_BAD_NULL_PARAM,
3786 + RES_MMU_BASE + RES_INVALID_INPUT_PARAM);
3787 + CHECK_INPUT_RANGE_MIN0(elementSize, MMU_ELEMENTSIZE_MAX,
3788 + RET_PARAM_OUT_OF_RANGE, RES_MMU_BASE +
3789 + RES_INVALID_INPUT_PARAM);
3790 +
3791 +
3792 + mmuRamReg = (physicalAddr & MMU_ADDR_MASK);
3793 + mmuRamReg = (mmuRamReg) | ((endianism << 9) | (elementSize << 7) |
3794 + (mixedSize << 6));
3795 +
3796 + /* write values to register */
3797 + MMUMMU_RAMWriteRegister32(baseAddress, mmuRamReg);
3798 +
3799 + return status;
3800 +
3801 +}
3802 Index: lk/drivers/dsp/bridge/hw/hw_mmu.h
3803 ===================================================================
3804 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3805 +++ lk/drivers/dsp/bridge/hw/hw_mmu.h 2008-08-18 10:38:36.000000000 +0300
3806 @@ -0,0 +1,178 @@
3807 +/*
3808 + * linux/drivers/dsp/bridge/hw/omap3/inc/hw_mmu.h
3809 + *
3810 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
3811 + *
3812 + * Copyright (C) 2007 Texas Instruments, Inc.
3813 + *
3814 + * This package is free software; you can redistribute it and/or modify
3815 + * it under the terms of the GNU General Public License version 2 as
3816 + * published by the Free Software Foundation.
3817 + *
3818 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
3819 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
3820 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
3821 + */
3822 +
3823 +
3824 +/*
3825 + * ======== hw_mmu.h ========
3826 + * Description:
3827 + * MMU types and API declarations
3828 + *
3829 + *! Revision History:
3830 + *! ================
3831 + *! 19-Apr-2004 sb Moved & renamed endianness, page size, element size
3832 + TLBAdd takes in MMUMapAttrs instead of separate arguments
3833 + *! 08-Mar-2004 sb Added the Page Table management APIs
3834 + *! 16 Feb 2003 sb: Initial version
3835 + */
3836 +#ifndef __HW_MMU_H
3837 +#define __HW_MMU_H
3838 +
3839 +#include <linux/types.h>
3840 +
3841 +/* Bitmasks for interrupt sources */
3842 +#define HW_MMU_TRANSLATION_FAULT 0x2
3843 +#define HW_MMU_ALL_INTERRUPTS 0x1F
3844 +
3845 +#define HW_MMU_COARSE_PAGE_SIZE 0x400
3846 +
3847 +/* HW_MMUMixedSize_t: Enumerated Type used to specify whether to follow
3848 + CPU/TLB Element size */
3849 +enum HW_MMUMixedSize_t {
3850 + HW_MMU_TLBES,
3851 + HW_MMU_CPUES
3852 +
3853 +} ;
3854 +
3855 +/* HW_MMUMapAttrs_t: Struct containing MMU mapping attributes */
3856 +struct HW_MMUMapAttrs_t {
3857 + enum HW_Endianism_t endianism;
3858 + enum HW_ElementSize_t elementSize;
3859 + enum HW_MMUMixedSize_t mixedSize;
3860 +} ;
3861 +
3862 +extern HW_STATUS HW_MMU_Enable(const u32 baseAddress);
3863 +
3864 +extern HW_STATUS HW_MMU_Disable(const u32 baseAddress);
3865 +
3866 +extern HW_STATUS HW_MMU_NumLockedSet(const u32 baseAddress,
3867 + u32 numLockedEntries);
3868 +
3869 +extern HW_STATUS HW_MMU_VictimNumSet(const u32 baseAddress,
3870 + u32 victimEntryNum);
3871 +
3872 +/* For MMU faults */
3873 +extern HW_STATUS HW_MMU_EventAck(const u32 baseAddress,
3874 + u32 irqMask);
3875 +
3876 +extern HW_STATUS HW_MMU_EventDisable(const u32 baseAddress,
3877 + u32 irqMask);
3878 +
3879 +extern HW_STATUS HW_MMU_EventEnable(const u32 baseAddress,
3880 + u32 irqMask);
3881 +
3882 +extern HW_STATUS HW_MMU_EventStatus(const u32 baseAddress,
3883 + u32 *irqMask);
3884 +
3885 +extern HW_STATUS HW_MMU_FaultAddrRead(const u32 baseAddress,
3886 + u32 *addr);
3887 +
3888 +/* Set the TT base address */
3889 +extern HW_STATUS HW_MMU_TTBSet(const u32 baseAddress,
3890 + u32 TTBPhysAddr);
3891 +
3892 +extern HW_STATUS HW_MMU_TWLEnable(const u32 baseAddress);
3893 +
3894 +extern HW_STATUS HW_MMU_TWLDisable(const u32 baseAddress);
3895 +
3896 +extern HW_STATUS HW_MMU_TLBFlush(const u32 baseAddress,
3897 + u32 virtualAddr,
3898 + u32 pageSize);
3899 +
3900 +extern HW_STATUS HW_MMU_TLBFlushAll(const u32 baseAddress);
3901 +
3902 +extern HW_STATUS HW_MMU_TLBAdd(const u32 baseAddress,
3903 + u32 physicalAddr,
3904 + u32 virtualAddr,
3905 + u32 pageSize,
3906 + u32 entryNum,
3907 + struct HW_MMUMapAttrs_t *mapAttrs,
3908 + enum HW_SetClear_t preservedBit,
3909 + enum HW_SetClear_t validBit);
3910 +
3911 +
3912 +/* For PTEs */
3913 +extern HW_STATUS HW_MMU_PteSet(const u32 pgTblVa,
3914 + u32 physicalAddr,
3915 + u32 virtualAddr,
3916 + u32 pageSize,
3917 + struct HW_MMUMapAttrs_t *mapAttrs);
3918 +
3919 +extern HW_STATUS HW_MMU_PteClear(const u32 pgTblVa,
3920 + u32 pgSize,
3921 + u32 virtualAddr);
3922 +
3923 +static inline u32 HW_MMU_PteAddrL1(u32 L1_base, u32 va)
3924 +{
3925 + u32 pteAddr;
3926 + u32 VA_31_to_20;
3927 +
3928 + VA_31_to_20 = va >> (20 - 2); /* Left-shift by 2 here itself */
3929 + VA_31_to_20 &= 0xFFFFFFFCUL;
3930 + pteAddr = L1_base + VA_31_to_20;
3931 +
3932 + return pteAddr;
3933 +}
3934 +
3935 +static inline u32 HW_MMU_PteAddrL2(u32 L2_base, u32 va)
3936 +{
3937 + u32 pteAddr;
3938 +
3939 + pteAddr = (L2_base & 0xFFFFFC00) | ((va >> 10) & 0x3FC);
3940 +
3941 + return pteAddr;
3942 +}
3943 +
3944 +static inline u32 HW_MMU_PteCoarseL1(u32 pteVal)
3945 +{
3946 + u32 pteCoarse;
3947 +
3948 + pteCoarse = pteVal & 0xFFFFFC00;
3949 +
3950 + return pteCoarse;
3951 +}
3952 +
3953 +static inline u32 HW_MMU_PteSizeL1(u32 pteVal)
3954 +{
3955 + u32 pteSize = 0;
3956 +
3957 + if ((pteVal & 0x3) == 0x1) {
3958 + /* Points to L2 PT */
3959 + pteSize = HW_MMU_COARSE_PAGE_SIZE;
3960 + }
3961 +
3962 + if ((pteVal & 0x3) == 0x2) {
3963 + if (pteVal & (1 << 18))
3964 + pteSize = HW_PAGE_SIZE_16MB;
3965 + else
3966 + pteSize = HW_PAGE_SIZE_1MB;
3967 + }
3968 +
3969 + return pteSize;
3970 +}
3971 +
3972 +static inline u32 HW_MMU_PteSizeL2(u32 pteVal)
3973 +{
3974 + u32 pteSize = 0;
3975 +
3976 + if (pteVal & 0x2)
3977 + pteSize = HW_PAGE_SIZE_4KB;
3978 + else if (pteVal & 0x1)
3979 + pteSize = HW_PAGE_SIZE_64KB;
3980 +
3981 + return pteSize;
3982 +}
3983 +
3984 +#endif /* __HW_MMU_H */
3985 Index: lk/drivers/dsp/bridge/hw/hw_prcm.c
3986 ===================================================================
3987 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
3988 +++ lk/drivers/dsp/bridge/hw/hw_prcm.c 2008-08-18 10:38:36.000000000 +0300
3989 @@ -0,0 +1,167 @@
3990 +/*
3991 + * linux/drivers/dsp/bridge/hw/omap3/prcm/hw_prcm.c
3992 + *
3993 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
3994 + *
3995 + * Copyright (C) 2007 Texas Instruments, Inc.
3996 + *
3997 + * This package is free software; you can redistribute it and/or modify
3998 + * it under the terms of the GNU General Public License version 2 as
3999 + * published by the Free Software Foundation.
4000 + *
4001 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
4002 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
4003 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
4004 + */
4005 +
4006 +/*
4007 + * ======== hw_prcm.c ========
4008 + * Description:
4009 + * API definitions to configure PRCM (Power, Reset & Clocks Manager)
4010 + *
4011 + *! Revision History:
4012 + *! ================
4013 + *! 16 Feb 2003 sb: Initial version
4014 + */
4015 +
4016 +#include <GlobalTypes.h>
4017 +#include "PRCMRegAcM.h"
4018 +#include <hw_defs.h>
4019 +#include <hw_prcm.h>
4020 +
4021 +static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
4022 + enum HW_RstModule_t r,
4023 + enum HW_SetClear_t val);
4024 +
4025 +HW_STATUS HW_RST_Reset(const u32 baseAddress, enum HW_RstModule_t r)
4026 +{
4027 + return HW_RST_WriteVal(baseAddress, r, HW_SET);
4028 +}
4029 +
4030 +HW_STATUS HW_RST_UnReset(const u32 baseAddress, enum HW_RstModule_t r)
4031 +{
4032 + return HW_RST_WriteVal(baseAddress, r, HW_CLEAR);
4033 +}
4034 +
4035 +static HW_STATUS HW_RST_WriteVal(const u32 baseAddress,
4036 + enum HW_RstModule_t r,
4037 + enum HW_SetClear_t val)
4038 +{
4039 + HW_STATUS status = RET_OK;
4040 +
4041 + switch (r) {
4042 + case HW_RST1_IVA2:
4043 + PRM_RSTCTRL_IVA2RST1_DSPWrite32(baseAddress, val);
4044 + break;
4045 + case HW_RST2_IVA2:
4046 + PRM_RSTCTRL_IVA2RST2_DSPWrite32(baseAddress, val);
4047 + break;
4048 + case HW_RST3_IVA2:
4049 + PRM_RSTCTRL_IVA2RST3_DSPWrite32(baseAddress, val);
4050 + break;
4051 + default:
4052 + status = RET_FAIL;
4053 + break;
4054 + }
4055 + return status;
4056 +}
4057 +
4058 +HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress, enum HW_PwrModule_t p,
4059 + enum HW_PwrState_t *value)
4060 +{
4061 + HW_STATUS status = RET_OK;
4062 + u32 temp;
4063 +
4064 + switch (p) {
4065 + case HW_PWR_DOMAIN_DSP:
4066 + /* wait until Transition is complete */
4067 + do {
4068 + /* mdelay(1); */
4069 + temp = PRCMPM_PWSTST_IVA2InTransitionRead32
4070 + (baseAddress);
4071 +
4072 + } while (temp);
4073 +
4074 + temp = PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress);
4075 + *value = PRCMPM_PWSTST_IVA2PowerStateStGet32(temp);
4076 + break;
4077 +
4078 + default:
4079 + status = RET_FAIL;
4080 + break;
4081 + }
4082 + return status;
4083 +}
4084 +
4085 +HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value)
4086 +{
4087 + HW_STATUS status = RET_OK;
4088 +
4089 + *value = PRCMPM_PWSTST_IVA2ReadRegister32(baseAddress);
4090 +
4091 + return status;
4092 +}
4093 +
4094 +
4095 +HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
4096 + enum HW_PwrModule_t p,
4097 + enum HW_PwrState_t value)
4098 +{
4099 + HW_STATUS status = RET_OK;
4100 +
4101 + switch (p) {
4102 + case HW_PWR_DOMAIN_DSP:
4103 + switch (value) {
4104 + case HW_PWR_STATE_ON:
4105 + PRCMPM_PWSTCTRL_IVA2PowerStateWriteON32(baseAddress);
4106 + break;
4107 + case HW_PWR_STATE_RET:
4108 + PRCMPM_PWSTCTRL_DSPPowerStateWriteRET32(baseAddress);
4109 + break;
4110 + case HW_PWR_STATE_OFF:
4111 + PRCMPM_PWSTCTRL_IVA2PowerStateWriteOFF32(baseAddress);
4112 + break;
4113 + default:
4114 + status = RET_FAIL;
4115 + break;
4116 + }
4117 + break;
4118 +
4119 + default:
4120 + status = RET_FAIL;
4121 + break;
4122 + }
4123 +
4124 + return status;
4125 +}
4126 +
4127 +HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
4128 + enum HW_TransitionState_t val)
4129 +{
4130 + HW_STATUS status = RET_OK;
4131 +
4132 + PRCMCM_CLKSTCTRL_IVA2WriteRegister32(baseAddress, val);
4133 +
4134 + return status;
4135 +
4136 +}
4137 +
4138 +HW_STATUS HW_RSTST_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
4139 + u32 *value)
4140 +{
4141 + HW_STATUS status = RET_OK;
4142 +
4143 + *value = PRCMRM_RSTST_DSPReadRegister32(baseAddress);
4144 +
4145 + return status;
4146 +}
4147 +
4148 +HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress, enum HW_RstModule_t m,
4149 + u32 *value)
4150 +{
4151 + HW_STATUS status = RET_OK;
4152 +
4153 + *value = PRCMRM_RSTCTRL_DSPReadRegister32(baseAddress);
4154 +
4155 + return status;
4156 +}
4157 Index: lk/drivers/dsp/bridge/hw/hw_prcm.h
4158 ===================================================================
4159 --- /dev/null 1970-01-01 00:00:00.000000000 +0000
4160 +++ lk/drivers/dsp/bridge/hw/hw_prcm.h 2008-08-18 10:38:36.000000000 +0300
4161 @@ -0,0 +1,168 @@
4162 +/*
4163 + * linux/drivers/dsp/bridge/hw/omap3/inc/hw_prcm.h
4164 + *
4165 + * DSP-BIOS Bridge driver support functions for TI OMAP processors.
4166 + *
4167 + * Copyright (C) 2007 Texas Instruments, Inc.
4168 + *
4169 + * This package is free software; you can redistribute it and/or modify
4170 + * it under the terms of the GNU General Public License version 2 as
4171 + * published by the Free Software Foundation.
4172 + *
4173 + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
4174 + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
4175 + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
4176 + */
4177 +
4178 +/*
4179 + * ======== hw_prcm.h ========
4180 + * Description:
4181 + * PRCM types and API declarations
4182 + *
4183 + *! Revision History:
4184 + *! ================
4185 + *! 16 Feb 2003 sb: Initial version
4186 + */
4187 +
4188 +#ifndef __HW_PRCM_H
4189 +#define __HW_PRCM_H
4190 +
4191 +/* HW_ClkModule: Enumerated Type used to specify the clock domain */
4192 +
4193 +enum HW_ClkModule_t {
4194 +/* DSP Domain */
4195 + HW_CLK_DSP_CPU,
4196 + HW_CLK_DSP_IPI_MMU,
4197 + HW_CLK_IVA_ARM,
4198 + HW_CLK_IVA_COP, /* IVA Coprocessor */
4199 +
4200 +/* Core Domain */
4201 + HW_CLK_FN_WDT4, /* Functional Clock */
4202 + HW_CLK_FN_WDT3,
4203 + HW_CLK_FN_UART2,
4204 + HW_CLK_FN_UART1,
4205 + HW_CLK_GPT5,
4206 + HW_CLK_GPT6,
4207 + HW_CLK_GPT7,
4208 + HW_CLK_GPT8,
4209 +
4210 + HW_CLK_IF_WDT4, /* Interface Clock */
4211 + HW_CLK_IF_WDT3,
4212 + HW_CLK_IF_UART2,
4213 + HW_CLK_IF_UART1,
4214 + HW_CLK_IF_MBOX
4215 +
4216 +} ;
4217 +
4218 +enum HW_ClkSubsys_t {
4219 + HW_CLK_DSPSS,
4220 + HW_CLK_IVASS
4221 +} ;
4222 +
4223 +/* HW_GPtimers: General purpose timers */
4224 +enum HW_GPtimer_t {
4225 + HW_GPT5 = 5,
4226 + HW_GPT6 = 6,
4227 + HW_GPT7 = 7,
4228 + HW_GPT8 = 8
4229 +} ;
4230 +
4231 +
4232 +/* GP timers Input clock type: General purpose timers */
4233 +enum HW_Clocktype_t {
4234 + HW_CLK_32KHz = 0,
4235 + HW_CLK_SYS = 1,
4236 + HW_CLK_EXT = 2
4237 +} ;
4238 +
4239 +/* HW_ClkDiv: Clock divisors */
4240 +enum HW_ClkDiv_t {
4241 + HW_CLK_DIV_1 = 0x1,
4242 + HW_CLK_DIV_2 = 0x2,
4243 + HW_CLK_DIV_3 = 0x3,
4244 + HW_CLK_DIV_4 = 0x4,
4245 + HW_CLK_DIV_6 = 0x6,
4246 + HW_CLK_DIV_8 = 0x8,
4247 + HW_CLK_DIV_12 = 0xC
4248 +} ;
4249 +
4250 +/* HW_RstModule: Enumerated Type used to specify the module to be reset */
4251 +enum HW_RstModule_t {
4252 + HW_RST1_IVA2, /* Reset the DSP */
4253 + HW_RST2_IVA2, /* Reset MMU and LEON HWa */
4254 + HW_RST3_IVA2 /* Reset LEON sequencer */
4255 +} ;
4256 +
4257 +/* HW_PwrModule: Enumerated Type used to specify the power domain */
4258 +enum HW_PwrModule_t {
4259 +/* Domains */
4260 + HW_PWR_DOMAIN_CORE,
4261 + HW_PWR_DOMAIN_MPU,
4262 + HW_PWR_DOMAIN_WAKEUP,
4263 + HW_PWR_DOMAIN_DSP,
4264 +
4265 +/* Sub-domains */
4266 + HW_PWR_DSP_IPI, /* IPI = Intrusive Port Interface */
4267 + HW_PWR_IVA_ISP /* ISP = Intrusive Slave Port */
4268 +} ;
4269 +
4270 +enum HW_PwrState_t {
4271 + HW_PWR_STATE_OFF,
4272 + HW_PWR_STATE_RET,
4273 + HW_PWR_STATE_INACT,
4274 + HW_PWR_STATE_ON = 3
4275 +} ;
4276 +
4277 +enum HW_ForceState_t {
4278 + HW_FORCE_OFF,
4279 + HW_FORCE_ON
4280 +} ;
4281 +
4282 +enum HW_IdleState_t {
4283 + HW_ACTIVE,
4284 + HW_STANDBY
4285 +
4286 +} ;
4287 +
4288 +enum HW_TransitionState_t {
4289 + HW_AUTOTRANS_DIS,
4290 + HW_SW_SUP_SLEEP,
4291 + HW_SW_SUP_WAKEUP,
4292 + HW_AUTOTRANS_EN
4293 +} ;
4294 +
4295 +
4296 +extern HW_STATUS HW_RST_Reset(const u32 baseAddress,
4297 + enum HW_RstModule_t r);
4298 +
4299 +extern HW_STATUS HW_RST_UnReset(const u32 baseAddress,
4300 + enum HW_RstModule_t r);
4301 +
4302 +extern HW_STATUS HW_RSTCTRL_RegGet(const u32 baseAddress,
4303 + enum HW_RstModule_t p,
4304 + u32 *value);
4305 +extern HW_STATUS HW_RSTST_RegGet(const u32 baseAddress,
4306 + enum HW_RstModule_t p, u32 *value);
4307 +
4308 +extern HW_STATUS HW_PWR_PowerStateSet(const u32 baseAddress,
4309 + enum HW_PwrModule_t p,
4310 + enum HW_PwrState_t value);
4311 +
4312 +extern HW_STATUS HW_CLK_SetInputClock(const u32 baseAddress,
4313 + enum HW_GPtimer_t gpt,
4314 + enum HW_Clocktype_t c);
4315 +
4316 +extern HW_STATUS HW_PWR_IVA2StateGet(const u32 baseAddress,
4317 + enum HW_PwrModule_t p,
4318 + enum HW_PwrState_t *value);
4319 +
4320 +extern HW_STATUS HW_PWRST_IVA2RegGet(const u32 baseAddress, u32 *value);
4321 +
4322 +extern HW_STATUS HW_PWR_IVA2PowerStateSet(const u32 baseAddress,
4323 + enum HW_PwrModule_t p,
4324 + enum HW_PwrState_t value);
4325 +
4326 +extern HW_STATUS HW_PWR_CLKCTRL_IVA2RegSet(const u32 baseAddress,
4327 + enum HW_TransitionState_t val);
4328 +
4329 +#endif /* __HW_PRCM_H */