From b77496b8b133dc8dbb1ef2d0888b1b02952b4fca Mon Sep 17 00:00:00 2001 From: Tommy Thorn Date: Sat, 18 Apr 2009 01:31:36 -0700 Subject: [PATCH] Target ML401: Almost working (untested) I haven't been able to test this yet, but it's a step in the right direction. --- rtl/target/ML401/README-ML401.txt | 29 +++++ rtl/target/ML401/config.h | 15 +++ rtl/target/ML401/dpram.v | 48 +++++++ rtl/target/ML401/dpram_simple.v | 54 ++++++++ rtl/target/ML401/dtag0.data | 256 ++++++++++++++++++++++++++++++++++++++ rtl/target/ML401/dtag1.data | 256 ++++++++++++++++++++++++++++++++++++++ rtl/target/ML401/dtag2.data | 256 ++++++++++++++++++++++++++++++++++++++ rtl/target/ML401/dtag3.data | 256 ++++++++++++++++++++++++++++++++++++++ rtl/target/ML401/ml401.ucf | 15 +++ rtl/target/ML401/rs232.v | 59 +++++++++ rtl/target/ML401/simpledpram.v | 33 +++++ rtl/target/ML401/tag0.data | 128 +++++++++++++++++++ rtl/target/ML401/tag1.data | 128 +++++++++++++++++++ rtl/target/ML401/tag2.data | 128 +++++++++++++++++++ rtl/target/ML401/tag3.data | 128 +++++++++++++++++++ rtl/target/ML401/top.v | 144 +++++++++++++++++++++ 16 files changed, 1933 insertions(+) create mode 100644 rtl/target/ML401/README-ML401.txt create mode 100644 rtl/target/ML401/config.h create mode 100644 rtl/target/ML401/dpram.v create mode 100644 rtl/target/ML401/dpram_simple.v create mode 100644 rtl/target/ML401/dtag0.data create mode 100644 rtl/target/ML401/dtag1.data create mode 100644 rtl/target/ML401/dtag2.data create mode 100644 rtl/target/ML401/dtag3.data create mode 100644 rtl/target/ML401/ml401.ucf create mode 100644 rtl/target/ML401/rs232.v create mode 100644 rtl/target/ML401/simpledpram.v create mode 100644 rtl/target/ML401/tag0.data create mode 100644 rtl/target/ML401/tag1.data create mode 100644 rtl/target/ML401/tag2.data create mode 100644 rtl/target/ML401/tag3.data create mode 100644 rtl/target/ML401/top.v diff --git a/rtl/target/ML401/README-ML401.txt b/rtl/target/ML401/README-ML401.txt new file mode 100644 index 0000000..0906f85 --- /dev/null +++ b/rtl/target/ML401/README-ML401.txt @@ -0,0 +1,29 @@ +YARI does build on ML401, but due ISE with it's binary project format, +I'm unable to successfully create a complete project here. + +However, making one from scratch isn't too hard: +- Create a new project +- Use an Virtex 4, XC4XL25, speed -10 +- Add these sources: + + config.h + dpram.v + dpram_simple.v + rs232.v + simpledpram.v + top.v + ml401.ucf + + ../../soclib/rs232in.v + ../../soclib/rs232out.v + + ../../yari-core/asm.v + ../../yari-core/perfcounters.v + ../../yari-core/stage_D.v + ../../yari-core/stage_I.v + ../../yari-core/stage_M.v + ../../yari-core/stage_X.v + ../../yari-core/yari.v + +Voila ! + diff --git a/rtl/target/ML401/config.h b/rtl/target/ML401/config.h new file mode 100644 index 0000000..a1e7228 --- /dev/null +++ b/rtl/target/ML401/config.h @@ -0,0 +1,15 @@ +// Don't edit this! Edit config.sh +// This configuration file was autogenerated by config.sh on Sat May 24 19:41:20 PDT 2008 + +// Cachable range +parameter CACHEABLE_BITS=32; + +// Instruction cache (4-way associtative tag-sequential 8 KiB) +parameter IC_SET_INDEX_BITS=2; // Caches has four sets +parameter IC_LINE_INDEX_BITS=7; // Each set has 128 lines +parameter IC_WORD_INDEX_BITS=2; // Each line has 4 32-bit words (128 bits) + +// Data cache (4-way associtative tag-sequential 16 KiB) +parameter DC_SET_INDEX_BITS=2; // Caches has four sets +parameter DC_LINE_INDEX_BITS=8; // Each set has 256 lines +parameter DC_WORD_INDEX_BITS=2; // Each line has 4 32-bit words (128 bits) diff --git a/rtl/target/ML401/dpram.v b/rtl/target/ML401/dpram.v new file mode 100644 index 0000000..b07d15e --- /dev/null +++ b/rtl/target/ML401/dpram.v @@ -0,0 +1,48 @@ +`timescale 1 ns / 10 ps + +module dpram (clock, + address_a, byteena_a, wrdata_a, wren_a, rddata_a, + address_b, byteena_b, wrdata_b, wren_b, rddata_b); + + parameter DATA_WIDTH = 32; + parameter ADDR_WIDTH = 7; + parameter INIT_FILE = "dummy"; // This is ignored right now + + input clock; + + input [ADDR_WIDTH-1:0] address_a; + input [DATA_WIDTH/8-1:0] byteena_a; + input [DATA_WIDTH-1:0] wrdata_a; + input wren_a; + output [DATA_WIDTH-1:0] rddata_a; + + input [ADDR_WIDTH-1:0] address_b; + input [DATA_WIDTH-1:0] wrdata_b; + input [DATA_WIDTH/8-1:0] byteena_b; + input wren_b; + output [DATA_WIDTH-1:0] rddata_b; + + dpram_simple s0(clock, + address_a, wrdata_a[ 7: 0], byteena_a[0] & wren_a, rddata_a[ 7: 0], + address_b, wrdata_b[ 7: 0], byteena_b[0] & wren_b, rddata_b[ 7: 0]); + defparam s0.DATA_WIDTH = DATA_WIDTH / 4, + s0.DATA_WIDTH = DATA_WIDTH; + + dpram_simple s1(clock, + address_a, wrdata_a[15: 8], byteena_a[1] & wren_a, rddata_a[15: 8], + address_b, wrdata_b[15: 8], byteena_b[1] & wren_b, rddata_b[15: 8]); + defparam s1.DATA_WIDTH = DATA_WIDTH / 4, + s1.DATA_WIDTH = DATA_WIDTH; + + dpram_simple s2(clock, + address_a, wrdata_a[23:16], byteena_a[2] & wren_a, rddata_a[23:16], + address_b, wrdata_b[23:16], byteena_b[2] & wren_b, rddata_b[23:16]); + defparam s2.DATA_WIDTH = DATA_WIDTH / 4, + s2.DATA_WIDTH = DATA_WIDTH; + + dpram_simple s3(clock, + address_a, wrdata_a[31:24], byteena_a[3] & wren_a, rddata_a[31:24], + address_b, wrdata_b[31:24], byteena_b[3] & wren_b, rddata_b[31:24]); + defparam s3.DATA_WIDTH = DATA_WIDTH / 4, + s3.DATA_WIDTH = DATA_WIDTH; +endmodule diff --git a/rtl/target/ML401/dpram_simple.v b/rtl/target/ML401/dpram_simple.v new file mode 100644 index 0000000..88ca72a --- /dev/null +++ b/rtl/target/ML401/dpram_simple.v @@ -0,0 +1,54 @@ +`timescale 1 ns / 10 ps + +module dpram_simple(clock, + address_a, wrdata_a, wren_a, rddata_a, + address_b, wrdata_b, wren_b, rddata_b); + + parameter DATA_WIDTH = 8; + parameter ADDR_WIDTH = 7; + parameter INIT_FILE = "somefile"; // No .mif! + parameter DEBUG = 0; + + input clock; + + input [ADDR_WIDTH-1:0] address_a; + input [DATA_WIDTH-1:0] wrdata_a; + input wren_a; + output reg [DATA_WIDTH-1:0] rddata_a; + + input [ADDR_WIDTH-1:0] address_b; + input [DATA_WIDTH-1:0] wrdata_b; + input wren_b; + output reg [DATA_WIDTH-1:0] rddata_b; + + // Declare the RAM variable + reg [DATA_WIDTH-1:0] ram[(1 << ADDR_WIDTH)-1:0]; + + always @(posedge clock) begin + if (wren_a) + ram[address_a] <= wrdata_a; + + /* + * Read (if read_addr == write_addr, return OLD data). To return + * NEW data, use = (blocking write) rather than <= (non-blocking write) + * in the write assignment. NOTE: NEW data may require extra bypass + * logic around the RAM. + */ + + rddata_a <= ram[address_a]; + end + + always @(posedge clock) begin + if (wren_b) + ram[address_b] <= wrdata_b; + + /* + * Read (if read_addr == write_addr, return OLD data). To return + * NEW data, use = (blocking write) rather than <= (non-blocking write) + * in the write assignment. NOTE: NEW data may require extra bypass + * logic around the RAM. + */ + + rddata_b <= ram[address_b]; + end +endmodule diff --git a/rtl/target/ML401/dtag0.data b/rtl/target/ML401/dtag0.data new file mode 100644 index 0000000..9ba937c --- /dev/null +++ b/rtl/target/ML401/dtag0.data @@ -0,0 +1,256 @@ +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff +1fffff 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+1ffffc +1ffffc +1ffffc +1ffffc +1ffffc +1ffffc diff --git a/rtl/target/ML401/ml401.ucf b/rtl/target/ML401/ml401.ucf new file mode 100644 index 0000000..c260d0f --- /dev/null +++ b/rtl/target/ML401/ml401.ucf @@ -0,0 +1,15 @@ +# The ML401 has a 10CES. The ES part apparently has to be set here. +CONFIG STEPPING="ES"; + +NET iSYS_CLK_100 LOC = AE14; +NET iSYS_CLK_100 IOSTANDARD = LVCMOS33; +NET iSYS_RST LOC = D6; +NET iSYS_RST PULLUP; +NET iSYS_RST TIG; + +NET iUART_RXD LOC = W2; +NET iUART_RXD IOSTANDARD = LVCMOS33; +NET iUART_RXD TIG; +NET oUART_TXD LOC = W1; +NET oUART_TXD IOSTANDARD = LVCMOS33; +NET oUART_TXD TIG; diff --git a/rtl/target/ML401/rs232.v b/rtl/target/ML401/rs232.v new file mode 100644 index 0000000..afe2613 --- /dev/null +++ b/rtl/target/ML401/rs232.v @@ -0,0 +1,59 @@ +`timescale 1ns/10ps +module rs232(input wire clk, + input wire rst, + + input wire [3:0] iKEY, + input wire [31:0] vsynccnt, + + // Master connections + input wire `REQ rs232_req, + output wire `RES rs232_res, + + input wire rs232in_attention, + input wire [7:0] rs232in_data, + + input wire rs232out_busy, + output wire rs232out_w, + output wire [7:0] rs232out_d); + + parameter debug = 1; + + reg [31:0] tsc = 0; // A free running counter.... + reg [ 7:0] rs232in_cnt = 0; + + wire [31:0] addr = rs232_req`A; + reg [31:0] rd_data = 0; + assign rs232_res`RD = rd_data; + assign rs232_res`HOLD = 0; + + reg [3:0] iKEY_; + + + always @(posedge clk) + if (rst) begin + rd_data <= 0; + tsc <= 0; + rs232in_cnt <= 0; + end else begin + iKEY_ <= iKEY; + + rd_data <= 0; + tsc <= tsc + 1; + if (rs232in_attention) + rs232in_cnt <= rs232in_cnt + 1'h1; + + if (rs232_req`R) begin + case (addr[4:2]) + 0: rd_data <= {31'h0,rs232out_busy};// 0 + 1: rd_data <= {24'h0,rs232in_data}; // 4 + 2: rd_data <= {24'h0,rs232in_cnt}; // 8 + 3: rd_data <= tsc; // 12 + 4: rd_data <= ~iKEY_; + 5: rd_data <= vsynccnt; + endcase + end + end + + assign rs232out_d = rs232_req`WD; + assign rs232out_w = rs232_req`W & addr[3:0] == 0; +endmodule diff --git a/rtl/target/ML401/simpledpram.v b/rtl/target/ML401/simpledpram.v new file mode 100644 index 0000000..516e5b0 --- /dev/null +++ b/rtl/target/ML401/simpledpram.v @@ -0,0 +1,33 @@ +`timescale 1ns/10ps +module simpledpram(clock, + wraddress, wrdata, wren, + rdaddress, rddata); + parameter DATA_WIDTH = 32; + parameter ADDR_WIDTH = 7; + parameter INIT_FILE = "somefile.mif"; + + input clock; + input [(ADDR_WIDTH-1):0] rdaddress; + output reg [(DATA_WIDTH-1):0] rddata; + input [(DATA_WIDTH-1):0] wrdata; + input wren; + input [(ADDR_WIDTH-1):0] wraddress; + + // Declare the RAM variable + (* ram_init_file = INIT_FILE *) + reg [DATA_WIDTH-1:0] ram[(1 << ADDR_WIDTH)-1:0]; + + always @ (posedge clock) begin + // Write + if (wren) + ram[wraddress] <= wrdata; + + // Read (if rdaddress == wraddress, return OLD data). To return + // NEW data, use = (blocking write) rather than <= (non-blocking write) + // in the write assignment. NOTE: NEW data may require extra bypass + // logic around the RAM. + rddata <= ram[rdaddress]; + end + + initial $readmemh({INIT_FILE,".data"}, ram); +endmodule diff --git a/rtl/target/ML401/tag0.data b/rtl/target/ML401/tag0.data new file mode 100644 index 0000000..9f4fdb8 --- /dev/null +++ b/rtl/target/ML401/tag0.data @@ -0,0 +1,128 @@ +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 +17f800 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+17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 +17f803 diff --git a/rtl/target/ML401/top.v b/rtl/target/ML401/top.v new file mode 100644 index 0000000..1212b7c --- /dev/null +++ b/rtl/target/ML401/top.v @@ -0,0 +1,144 @@ +// ----------------------------------------------------------------------- +// +// Copyright 2004,2007-2009 Tommy Thorn - All Rights Reserved +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, Inc., 53 Temple Place Ste 330, +// Bostom MA 02111-1307, USA; either version 2 of the License, or +// (at your option) any later version; incorporated herein by reference. +// +// ----------------------------------------------------------------------- + +`timescale 1ns/10ps +`include "../../soclib/pipeconnect.h" +module main + (input iSYS_CLK_100 + ,input iSYS_RST + + ,input iUART_RXD + ,output oUART_TXD + + ); + + parameter FREQ = 100_000_000; // match clock frequency + parameter BPS = 9_600; // Serial speed + + // Copied from yari.v + parameter ID_DC = 2'd1; + parameter ID_IC = 2'd2; + parameter ID_FB = 2'd3; + + wire clock; // The master clock + + /* + wire video_clock; + wire clock_locked; + + // Actually, just a 1-1 clock filter for c0 + // and a 65 MHz for video_clock + pll pll_inst(.inclk0(iCLK_50) + ,.c0(clock) + ,.c2(video_clock) + ,.locked(clock_locked)); + reg iSW17_, iSW17, manual_reset; + */ + assign clock = iSYS_CLK_100; + wire reset = iSYS_RST; + + wire [ 7:0] rs232out_transmit_data; + wire rs232out_write_enable; + wire rs232out_busy; + + wire [ 7:0] rs232in_received_data; + wire rs232in_received_data_valid; + + wire mem_waitrequest; + wire [1:0] mem_id; + wire [29:0] mem_address; + wire mem_read; + wire mem_write; + wire [31:0] mem_writedata; + wire [3:0] mem_writedatamask; + wire [31:0] mem_readdata; + wire [1:0] mem_readdataid; + + wire yari_mem_waitrequest; + wire [1:0] yari_mem_id; + wire [29:0] yari_mem_address; + wire yari_mem_read; + wire yari_mem_write; + wire [31:0] yari_mem_writedata; + wire [3:0] yari_mem_writedatamask; + + wire `REQ rs232_req; + wire `RES rs232_res; + + yari yari_inst( + .clock(clock) + ,.rst(reset) + + // Inputs + ,.mem_waitrequest (yari_mem_waitrequest) + ,.mem_readdata (mem_readdata) + ,.mem_readdataid (mem_readdataid) + + // Outputs + ,.mem_id (yari_mem_id) + ,.mem_address (yari_mem_address) + ,.mem_read (yari_mem_read) + ,.mem_write (yari_mem_write) + ,.mem_writedata (yari_mem_writedata) + ,.mem_writedatamask(yari_mem_writedatamask) + + ,.peripherals_req(rs232_req) + ,.peripherals_res(rs232_res) + ); + + rs232out rs232out_inst + (.clock (clock), + .serial_out (oUART_TXD), + .transmit_data(rs232out_transmit_data), + .we (rs232out_write_enable), + .busy (rs232out_busy)); + + defparam rs232out_inst.frequency = FREQ, + rs232out_inst.bps = BPS; + + + rs232in rs232in_inst + (.clock (clock), + .serial_in (iUART_RXD), + .received_data(rs232in_received_data), + .attention (rs232in_received_data_valid)); + + defparam rs232in_inst.frequency = FREQ, + rs232in_inst.bps = BPS; + + wire [31:0] vsynccnt; + + rs232 rs232_inst(.clk(clock), + .rst(reset), + + .iKEY(0), + .vsynccnt(vsynccnt), + + .rs232_req(rs232_req), + .rs232_res(rs232_res), + + .rs232in_attention(rs232in_received_data_valid), + .rs232in_data (rs232in_received_data), + + .rs232out_busy(rs232out_busy), + .rs232out_w (rs232out_write_enable), + .rs232out_d (rs232out_transmit_data)); + + + assign mem_id = yari_mem_id; + assign mem_address = yari_mem_address; + assign mem_read = yari_mem_read; + assign mem_write = yari_mem_write; + assign mem_writedata = yari_mem_writedata; + assign mem_writedatamask = yari_mem_writedatamask; + assign yari_mem_waitrequest = mem_waitrequest; +endmodule -- 2.11.4.GIT