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commit	de3b50da426a12cf85f84d1621942bc3e7d039dc
author	Tommy Thorn <tommy-git@thorn.ws>
	Mon, 5 May 2008 01:42:55 +0000 (4 18:42 -0700)
committer	Tommy Thorn <tommy-git@thorn.ws>
	Tue, 23 Sep 2008 09:32:30 +0000 (23 02:32 -0700)
tree	ba2ff1fec27661a40c6199881c3b00a8e8257fe3	tree \| snapshot (tar.gz zip)
parent	2d562a095a720e78924c02796a994ad8481e8bba	commit \| diff

TARGET DE2-70: New port to Terasic's DE2-70

The most significant piece is the SSRAM controller.

This port still hasn't been pushed to the limited. Expect ~ 2X the
performance.

21 files changed:

README		diff \| blob \| blame \| history
rtl/target/DE2-70/Makefile	[new file with mode: 0644]	blob
rtl/target/DE2-70/config.h	[new file with mode: 0644]	blob
rtl/target/DE2-70/dtag0.mif	[new file with mode: 0644]	blob
rtl/target/DE2-70/dtag1.mif	[new file with mode: 0644]	blob
rtl/target/DE2-70/dtag2.mif	[new file with mode: 0644]	blob
rtl/target/DE2-70/dtag3.mif	[new file with mode: 0644]	blob
rtl/target/DE2-70/dummy_master.v	[new file with mode: 0644]	blob
rtl/target/DE2-70/main.qpf	[new file with mode: 0644]	blob
rtl/target/DE2-70/main.qsf	[new file with mode: 0644]	blob
rtl/target/DE2-70/main.v	[new file with mode: 0644]	blob
rtl/target/DE2-70/main_assignment_defaults.qdf	[new file with mode: 0644]	blob
rtl/target/DE2-70/mega/pll.ppf	[new file with mode: 0644]	blob
rtl/target/DE2-70/mega/pll.v	[new file with mode: 0644]	blob
rtl/target/DE2-70/ssram_ctrl.v	[new file with mode: 0644]	blob
rtl/target/DE2-70/tag0.mif	[new file with mode: 0644]	blob
rtl/target/DE2-70/tag1.mif	[new file with mode: 0644]	blob
rtl/target/DE2-70/tag2.mif	[new file with mode: 0644]	blob
rtl/target/DE2-70/tag3.mif	[new file with mode: 0644]	blob
rtl/target/niosdevkit-1c20/main.qsf		diff \| blob \| blame \| history
testcases/Makefile		diff \| blob \| blame \| history

MOVED TO GITHUB (A High Performance MIPS I Compatible Soft-core RISC Processor)

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