LPRP: A new 16-bit async sram controller

LPRP: A new 16-bit async sram controller

    This controller uses the PSRAM in async mode which means a
    70 ns cycle time which at 48 MHz implies 4 cycles.
    Unfortunately I had to raise it to 5 to get it stable.

    To avoid the problem with CE being active for too long (4 us),
    all writes pause (This could surely be improved).

    Also in the change:
    - Use the PLL in 1:1 to improve the clock.
    - A SignalTapII file I use from time to time