2 use IEEE.std_logic_1164.
all;
3 use IEEE.numeric_std.
all;
7 DEPTH
: positive
:= 64; -- How many slots
8 DATA_WIDTH
: positive
:= 16; -- How many bits per slot
9 ADDR_WIDTH
: positive
:= 6 -- = ceil(log2(DEPTH))
14 wr_addr
: in unsigned
(ADDR_WIDTH
-1 downto 0);
15 wr_data
: in signed
(DATA_WIDTH
-1 downto 0);
16 rd_addr
: in unsigned
(ADDR_WIDTH
-1 downto 0);
17 rd_data
: out signed
(DATA_WIDTH
-1 downto 0)
21 architecture rtl
of tsyncram
is
23 type MEM_TYPE
is array(0 to DEPTH
-1) of
24 signed
(DATA_WIDTH
-1 downto 0);
25 signal memory
: MEM_TYPE
;
30 if ( rising_edge
(clk
) ) then
31 if ( wr_e
= '1' ) then
32 memory
( to_integer
(wr_addr
) ) <= wr_data
;
34 rd_data
<= memory
( to_integer
(rd_addr
) );