theora-fpga/theora_hardware/divider.vhd

   1 library std;
   2 library ieee;
   3 library work;
   4
   5 use ieee.std_logic_1164.all;
   6 use ieee.numeric_std.all;
   7 use work.all;
   8
   9
  10 entity divider is
  11   generic (
  12     WIDTH : positive := 32);
  13   port (Clk,
  14         Reset_n       : in  std_logic;
  15
  16         in_request    : out std_logic;
  17         in_valid      : in  std_logic;
  18         dividend      : in  unsigned(WIDTH-1 downto 0);
  19         divisor       : in  unsigned(WIDTH-1 downto 0);
  20
  21         out_requested : in  std_logic;
  22         out_valid     : out std_logic;
  23         quotient      : out unsigned(WIDTH-1 downto 0);
  24         remainder     : out unsigned(WIDTH-1 downto 0)
  25         );
  26 end entity divider;
  27
  28 architecture a_divider of divider is
  29   type state_t is (stt_readIn, stt_divide, stt_writeOut);
  30   signal state : state_t;
  31
  32
  33   signal s_divisor   :   unsigned(WIDTH*2-1 downto 0);
  34   signal s_quotient  :   unsigned(WIDTH-1 downto 0);
  35   signal s_remainder :   unsigned(WIDTH*2-1 downto 0);
  36
  37   signal s_in_request : std_logic;
  38   signal s_out_valid  : std_logic;
  39   signal s_repetition : integer range 0 to WIDTH+1;
  40
  41 begin  -- a_divider
  42
  43   in_request <= s_in_request;
  44   out_valid <= s_out_valid;
  45
  46   process (clk)
  47
  48     procedure ReadIn is
  49     begin
  50       s_out_valid <= '0';            -- came from WriteOut, out_valid must be 0
  51       s_in_request <= '1';
  52       if( s_in_request = '1' and in_valid = '1' )then
  53         s_remainder <= resize("00", WIDTH) & dividend;
  54         s_divisor <= divisor & resize("00", WIDTH);
  55         s_quotient <= resize("00", WIDTH);
  56         s_repetition <= 0;
  57         s_in_request <= '0';
  58         state <= stt_divide;
  59       end if;
  60     end procedure ReadIn;
  61
  62     procedure Divide is
  63       variable v_subtractor : unsigned(WIDTH*2-1 downto 0);
  64     begin
  65       v_subtractor := s_remainder - s_divisor;
  66
  67       s_divisor <= SHIFT_RIGHT(s_divisor, 1);
  68       s_quotient <= SHIFT_LEFT(s_quotient, 1);
  69       if (v_subtractor(WIDTH*2-1) = '0') then  -- positive
  70         s_quotient(0) <= '1';
  71         s_remainder <= v_subtractor;
  72       else
  73         s_quotient(0) <= '0';
  74       end if;
  75       s_repetition <= s_repetition + 1;
  76       if (s_repetition = WIDTH) then
  77         state <= stt_writeOut;
  78         s_repetition <= 0;
  79       end if;
  80     end procedure Divide;
  81
  82
  83     procedure WriteOut is
  84     begin
  85       s_out_valid <= '1';
  86       quotient <= s_quotient;
  87       remainder <= s_remainder(WIDTH-1 downto 0);
  88       if (out_requested = '1') then
  89         state <= stt_readIn;
  90       end if;
  91     end procedure WriteOut;
  92
  93   begin
  94     if (clk'event and clk = '1') then
  95       if (Reset_n = '0') then
  96         s_in_request <= '0';
  97         s_out_valid <= '0';
  98
  99         s_repetition <= 0;
 100         state <= stt_readIn;
 101
 102       else
 103         case state is
 104           when stt_readIn => ReadIn;
 105           when stt_divide => Divide;
 106           when stt_writeOut => WriteOut;
 107           when others => ReadIn; state <= stt_readIn;
 108         end case;
 109       end if;
 110     end if;
 111   end process;
 112
 113 end a_divider;