include/asm-xtensa/pgtable.h

   1 /*
   2  * include/asm-xtensa/pgtable.h
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * Copyright (C) 2001 - 2007 Tensilica Inc.
   9  */
  10
  11 #ifndef _XTENSA_PGTABLE_H
  12 #define _XTENSA_PGTABLE_H
  13
  14 #include <asm-generic/pgtable-nopmd.h>
  15 #include <asm/page.h>
  16
  17 /*
  18  * We only use two ring levels, user and kernel space.
  19  */
  20
  21 #define USER_RING               1       /* user ring level */
  22 #define KERNEL_RING             0       /* kernel ring level */
  23
  24 /*
  25  * The Xtensa architecture port of Linux has a two-level page table system,
  26  * i.e. the logical three-level Linux page table layout is folded.
  27  * Each task has the following memory page tables:
  28  *
  29  *   PGD table (page directory), ie. 3rd-level page table:
  30  *      One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
  31  *      (Architectures that don't have the PMD folded point to the PMD tables)
  32  *
  33  *      The pointer to the PGD table for a given task can be retrieved from
  34  *      the task structure (struct task_struct*) t, e.g. current():
  35  *        (t->mm ? t->mm : t->active_mm)->pgd
  36  *
  37  *   PMD tables (page middle-directory), ie. 2nd-level page tables:
  38  *      Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
  39  *
  40  *   PTE tables (page table entry), ie. 1st-level page tables:
  41  *      One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
  42  *      invalid_pte_table for absent mappings.
  43  *
  44  * The individual pages are 4 kB big with special pages for the empty_zero_page.
  45  */
  46
  47 #define PGDIR_SHIFT     22
  48 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
  49 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
  50
  51 /*
  52  * Entries per page directory level: we use two-level, so
  53  * we don't really have any PMD directory physically.
  54  */
  55 #define PTRS_PER_PTE            1024
  56 #define PTRS_PER_PTE_SHIFT      10
  57 #define PTRS_PER_PGD            1024
  58 #define PGD_ORDER               0
  59 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
  60 #define FIRST_USER_ADDRESS      0
  61 #define FIRST_USER_PGD_NR       (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
  62
  63 /*
  64  * Virtual memory area. We keep a distance to other memory regions to be
  65  * on the safe side. We also use this area for cache aliasing.
  66  */
  67
  68 #define VMALLOC_START           0xC0000000
  69 <<<<<<< HEAD:include/asm-xtensa/pgtable.h
  70 #define VMALLOC_END             0xC6FEFFFF
  71 #define TLBTEMP_BASE_1          0xC6FF0000
  72 #define TLBTEMP_BASE_2          0xC6FF8000
  73 #define MODULE_START            0xC7000000
  74 #define MODULE_END              0xC7FFFFFF
  75 =======
  76 #define VMALLOC_END             0xC7FEFFFF
  77 #define TLBTEMP_BASE_1          0xC7FF0000
  78 #define TLBTEMP_BASE_2          0xC7FF8000
  79 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:include/asm-xtensa/pgtable.h
  80
  81 /*
  82  * Xtensa Linux config PTE layout (when present):
  83  *      31-12:  PPN
  84  *      11-6:   Software
  85  *      5-4:    RING
  86  *      3-0:    CA
  87  *
  88  * Similar to the Alpha and MIPS ports, we need to keep track of the ref
  89  * and mod bits in software.  We have a software "you can read
  90  * from this page" bit, and a hardware one which actually lets the
  91  * process read from the page.  On the same token we have a software
  92  * writable bit and the real hardware one which actually lets the
  93  * process write to the page.
  94  *
  95  * See further below for PTE layout for swapped-out pages.
  96  */
  97
  98 #define _PAGE_HW_EXEC           (1<<0)  /* hardware: page is executable */
  99 #define _PAGE_HW_WRITE          (1<<1)  /* hardware: page is writable */
 100
 101 #define _PAGE_FILE              (1<<1)  /* non-linear mapping, if !present */
 102 #define _PAGE_PROTNONE          (3<<0)  /* special case for VM_PROT_NONE */
 103
 104 /* None of these cache modes include MP coherency:  */
 105 #define _PAGE_CA_BYPASS         (0<<2)  /* bypass, non-speculative */
 106 #define _PAGE_CA_WB             (1<<2)  /* write-back */
 107 #define _PAGE_CA_WT             (2<<2)  /* write-through */
 108 #define _PAGE_CA_MASK           (3<<2)
 109 #define _PAGE_INVALID           (3<<2)
 110
 111 #define _PAGE_USER              (1<<4)  /* user access (ring=1) */
 112
 113 /* Software */
 114 #define _PAGE_WRITABLE_BIT      6
 115 #define _PAGE_WRITABLE          (1<<6)  /* software: page writable */
 116 #define _PAGE_DIRTY             (1<<7)  /* software: page dirty */
 117 #define _PAGE_ACCESSED          (1<<8)  /* software: page accessed (read) */
 118
 119 /* On older HW revisions, we always have to set bit 0 */
 120 #if XCHAL_HW_VERSION_MAJOR < 2000
 121 # define _PAGE_VALID            (1<<0)
 122 #else
 123 # define _PAGE_VALID            0
 124 #endif
 125
 126 #define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
 127 #define _PAGE_PRESENT   (_PAGE_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
 128
 129 #ifdef CONFIG_MMU
 130
 131 #define PAGE_NONE          __pgprot(_PAGE_INVALID | _PAGE_USER | _PAGE_PROTNONE)
 132 #define PAGE_COPY          __pgprot(_PAGE_PRESENT | _PAGE_USER)
 133 #define PAGE_COPY_EXEC     __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
 134 #define PAGE_READONLY      __pgprot(_PAGE_PRESENT | _PAGE_USER)
 135 #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
 136 #define PAGE_SHARED        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
 137 #define PAGE_SHARED_EXEC \
 138         __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
 139 #define PAGE_KERNEL        __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
 140 #define PAGE_KERNEL_EXEC   __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
 141
 142 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
 143 # define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED)
 144 #else
 145 # define _PAGE_DIRECTORY (_PAGE_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
 146 #endif
 147
 148 #else /* no mmu */
 149
 150 # define PAGE_NONE       __pgprot(0)
 151 # define PAGE_SHARED     __pgprot(0)
 152 # define PAGE_COPY       __pgprot(0)
 153 # define PAGE_READONLY   __pgprot(0)
 154 # define PAGE_KERNEL     __pgprot(0)
 155
 156 #endif
 157
 158 /*
 159  * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
 160  * the MMU can't do page protection for execute, and considers that the same as
 161  * read.  Also, write permissions may imply read permissions.
 162  * What follows is the closest we can get by reasonable means..
 163  * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
 164  */
 165 #define __P000  PAGE_NONE               /* private --- */
 166 #define __P001  PAGE_READONLY           /* private --r */
 167 #define __P010  PAGE_COPY               /* private -w- */
 168 #define __P011  PAGE_COPY               /* private -wr */
 169 #define __P100  PAGE_READONLY_EXEC      /* private x-- */
 170 #define __P101  PAGE_READONLY_EXEC      /* private x-r */
 171 #define __P110  PAGE_COPY_EXEC          /* private xw- */
 172 #define __P111  PAGE_COPY_EXEC          /* private xwr */
 173
 174 #define __S000  PAGE_NONE               /* shared  --- */
 175 #define __S001  PAGE_READONLY           /* shared  --r */
 176 #define __S010  PAGE_SHARED             /* shared  -w- */
 177 #define __S011  PAGE_SHARED             /* shared  -wr */
 178 #define __S100  PAGE_READONLY_EXEC      /* shared  x-- */
 179 #define __S101  PAGE_READONLY_EXEC      /* shared  x-r */
 180 #define __S110  PAGE_SHARED_EXEC        /* shared  xw- */
 181 #define __S111  PAGE_SHARED_EXEC        /* shared  xwr */
 182
 183 #ifndef __ASSEMBLY__
 184
 185 #define pte_ERROR(e) \
 186         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
 187 #define pgd_ERROR(e) \
 188         printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
 189
 190 extern unsigned long empty_zero_page[1024];
 191
 192 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 193
 194 extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
 195
 196 /*
 197  * The pmd contains the kernel virtual address of the pte page.
 198  */
 199 #define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
 200 #define pmd_page(pmd) virt_to_page(pmd_val(pmd))
 201
 202 /*
 203  * pte status.
 204  */
 205 #define pte_none(pte)    (pte_val(pte) == _PAGE_INVALID)
 206 #define pte_present(pte)                                                \
 207         (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_INVALID)              \
 208          || ((pte_val(pte) & _PAGE_PROTNONE) == _PAGE_PROTNONE))
 209 #define pte_clear(mm,addr,ptep)                                         \
 210         do { update_pte(ptep, __pte(_PAGE_INVALID)); } while(0)
 211
 212 #define pmd_none(pmd)    (!pmd_val(pmd))
 213 #define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
 214 #define pmd_bad(pmd)     (pmd_val(pmd) & ~PAGE_MASK)
 215 #define pmd_clear(pmdp)  do { set_pmd(pmdp, __pmd(0)); } while (0)
 216
 217 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
 218 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
 219 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
 220 static inline int pte_file(pte_t pte)  { return pte_val(pte) & _PAGE_FILE; }
 221 static inline pte_t pte_wrprotect(pte_t pte)
 222         { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
 223 static inline pte_t pte_mkclean(pte_t pte)
 224         { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
 225 static inline pte_t pte_mkold(pte_t pte)
 226         { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
 227 static inline pte_t pte_mkdirty(pte_t pte)
 228         { pte_val(pte) |= _PAGE_DIRTY; return pte; }
 229 static inline pte_t pte_mkyoung(pte_t pte)
 230         { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
 231 static inline pte_t pte_mkwrite(pte_t pte)
 232         { pte_val(pte) |= _PAGE_WRITABLE; return pte; }
 233
 234 /*
 235  * Conversion functions: convert a page and protection to a page entry,
 236  * and a page entry and page directory to the page they refer to.
 237  */
 238
 239 #define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
 240 #define pte_same(a,b)           (pte_val(a) == pte_val(b))
 241 #define pte_page(x)             pfn_to_page(pte_pfn(x))
 242 #define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
 243 #define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
 244
 245 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 246 {
 247         return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
 248 }
 249
 250 /*
 251  * Certain architectures need to do special things when pte's
 252  * within a page table are directly modified.  Thus, the following
 253  * hook is made available.
 254  */
 255 static inline void update_pte(pte_t *ptep, pte_t pteval)
 256 {
 257         *ptep = pteval;
 258 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
 259         __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
 260 #endif
 261
 262 }
 263
 264 struct mm_struct;
 265
 266 static inline void
 267 set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval)
 268 {
 269         update_pte(ptep, pteval);
 270 }
 271
 272
 273 static inline void
 274 set_pmd(pmd_t *pmdp, pmd_t pmdval)
 275 {
 276         *pmdp = pmdval;
 277 }
 278
 279 struct vm_area_struct;
 280
 281 static inline int
 282 ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
 283                           pte_t *ptep)
 284 {
 285         pte_t pte = *ptep;
 286         if (!pte_young(pte))
 287                 return 0;
 288         update_pte(ptep, pte_mkold(pte));
 289         return 1;
 290 }
 291
 292 static inline pte_t
 293 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 294 {
 295         pte_t pte = *ptep;
 296         pte_clear(mm, addr, ptep);
 297         return pte;
 298 }
 299
 300 static inline void
 301 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
 302 {
 303         pte_t pte = *ptep;
 304         update_pte(ptep, pte_wrprotect(pte));
 305 }
 306
 307 /* to find an entry in a kernel page-table-directory */
 308 #define pgd_offset_k(address)   pgd_offset(&init_mm, address)
 309
 310 /* to find an entry in a page-table-directory */
 311 #define pgd_offset(mm,address)  ((mm)->pgd + pgd_index(address))
 312
 313 #define pgd_index(address)      ((address) >> PGDIR_SHIFT)
 314
 315 /* Find an entry in the second-level page table.. */
 316 #define pmd_offset(dir,address) ((pmd_t*)(dir))
 317
 318 /* Find an entry in the third-level page table.. */
 319 #define pte_index(address)      (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
 320 #define pte_offset_kernel(dir,addr)                                     \
 321         ((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr))
 322 #define pte_offset_map(dir,addr)        pte_offset_kernel((dir),(addr))
 323 #define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir),(addr))
 324
 325 #define pte_unmap(pte)          do { } while (0)
 326 #define pte_unmap_nested(pte)   do { } while (0)
 327
 328
 329 /*
 330  * Encode and decode a swap entry.
 331  *
 332  * Format of swap pte:
 333  *  bit    0       MBZ
 334  *  bit    1       page-file (must be zero)
 335  *  bits   2 -  3  page hw access mode (must be 11: _PAGE_INVALID)
 336  *  bits   4 -  5  ring protection (must be 01: _PAGE_USER)
 337  *  bits   6 - 10  swap type (5 bits -> 32 types)
 338  *  bits  11 - 31  swap offset / PAGE_SIZE (21 bits -> 8GB)
 339
 340  * Format of file pte:
 341  *  bit    0       MBZ
 342  *  bit    1       page-file (must be one: _PAGE_FILE)
 343  *  bits   2 -  3  page hw access mode (must be 11: _PAGE_INVALID)
 344  *  bits   4 -  5  ring protection (must be 01: _PAGE_USER)
 345  *  bits   6 - 31  file offset / PAGE_SIZE
 346  */
 347
 348 #define __swp_type(entry)       (((entry).val >> 6) & 0x1f)
 349 #define __swp_offset(entry)     ((entry).val >> 11)
 350 #define __swp_entry(type,offs)  \
 351         ((swp_entry_t) {((type) << 6) | ((offs) << 11) | _PAGE_INVALID})
 352 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
 353 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
 354
 355 #define PTE_FILE_MAX_BITS       28
 356 #define pte_to_pgoff(pte)       (pte_val(pte) >> 4)
 357 #define pgoff_to_pte(off)       \
 358         ((pte_t) { ((off) << 4) | _PAGE_INVALID | _PAGE_FILE })
 359
 360 #endif /*  !defined (__ASSEMBLY__) */
 361
 362
 363 #ifdef __ASSEMBLY__
 364
 365 /* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
 366  *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
 367  *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
 368  *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
 369  *
 370  * Note: We require an additional temporary register which can be the same as
 371  *       the register that holds the address.
 372  *
 373  * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
 374  *
 375  */
 376 #define _PGD_INDEX(rt,rs)       extui   rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
 377 #define _PTE_INDEX(rt,rs)       extui   rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
 378
 379 #define _PGD_OFFSET(mm,adr,tmp)         l32i    mm, mm, MM_PGD;         \
 380                                         _PGD_INDEX(tmp, adr);           \
 381                                         addx4   mm, tmp, mm
 382
 383 #define _PTE_OFFSET(pmd,adr,tmp)        _PTE_INDEX(tmp, adr);           \
 384                                         srli    pmd, pmd, PAGE_SHIFT;   \
 385                                         slli    pmd, pmd, PAGE_SHIFT;   \
 386                                         addx4   pmd, tmp, pmd
 387
 388 #else
 389
 390 extern void paging_init(void);
 391
 392 #define kern_addr_valid(addr)   (1)
 393
 394 extern  void update_mmu_cache(struct vm_area_struct * vma,
 395                               unsigned long address, pte_t pte);
 396
 397 /*
 398  * remap a physical page `pfn' of size `size' with page protection `prot'
 399  * into virtual address `from'
 400  */
 401
 402 #define io_remap_pfn_range(vma,from,pfn,size,prot) \
 403                 remap_pfn_range(vma, from, pfn, size, prot)
 404
 405
 406 extern void pgtable_cache_init(void);
 407
 408 typedef pte_t *pte_addr_t;
 409
 410 #endif /* !defined (__ASSEMBLY__) */
 411
 412 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 413 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
 414 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
 415 #define __HAVE_ARCH_PTEP_MKDIRTY
 416 #define __HAVE_ARCH_PTE_SAME
 417
 418 #include <asm-generic/pgtable.h>
 419
 420 #endif /* _XTENSA_PGTABLE_H */