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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / pci / probe.c
blob52fe96dde8d39ea3f0038b4763ab744bb062681c
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include "pci.h"
13
14 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
15 #define CARDBUS_RESERVE_BUSNR 3
16 #define PCI_CFG_SPACE_SIZE 256
17 #define PCI_CFG_SPACE_EXP_SIZE 4096
18
19 /* Ugh. Need to stop exporting this to modules. */
20 LIST_HEAD(pci_root_buses);
21 EXPORT_SYMBOL(pci_root_buses);
22
23 LIST_HEAD(pci_devices);
24
25 /*
26 * Some device drivers need know if pci is initiated.
27 * Basically, we think pci is not initiated when there
28 * is no device in list of pci_devices.
29 */
30 int no_pci_devices(void)
31 {
32 return list_empty(&pci_devices);
33 }
34
35 EXPORT_SYMBOL(no_pci_devices);
36
37 #ifdef HAVE_PCI_LEGACY
38 /**
39 * pci_create_legacy_files - create legacy I/O port and memory files
40 * @b: bus to create files under
41 *
42 * Some platforms allow access to legacy I/O port and ISA memory space on
43 * a per-bus basis. This routine creates the files and ties them into
44 * their associated read, write and mmap files from pci-sysfs.c
45 */
46 static void pci_create_legacy_files(struct pci_bus *b)
47 {
48 b->legacy_io = kzalloc(sizeof(struct bin_attribute) * 2,
49 GFP_ATOMIC);
50 if (b->legacy_io) {
51 b->legacy_io->attr.name = "legacy_io";
52 b->legacy_io->size = 0xffff;
53 b->legacy_io->attr.mode = S_IRUSR | S_IWUSR;
54 b->legacy_io->read = pci_read_legacy_io;
55 b->legacy_io->write = pci_write_legacy_io;
56 device_create_bin_file(&b->dev, b->legacy_io);
57
58 /* Allocated above after the legacy_io struct */
59 b->legacy_mem = b->legacy_io + 1;
60 b->legacy_mem->attr.name = "legacy_mem";
61 b->legacy_mem->size = 1024*1024;
62 b->legacy_mem->attr.mode = S_IRUSR | S_IWUSR;
63 b->legacy_mem->mmap = pci_mmap_legacy_mem;
64 device_create_bin_file(&b->dev, b->legacy_mem);
65 }
66 }
67
68 void pci_remove_legacy_files(struct pci_bus *b)
69 {
70 if (b->legacy_io) {
71 device_remove_bin_file(&b->dev, b->legacy_io);
72 device_remove_bin_file(&b->dev, b->legacy_mem);
73 kfree(b->legacy_io); /* both are allocated here */
74 }
75 }
76 #else /* !HAVE_PCI_LEGACY */
77 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
78 void pci_remove_legacy_files(struct pci_bus *bus) { return; }
79 #endif /* HAVE_PCI_LEGACY */
80
81 /*
82 * PCI Bus Class Devices
83 */
84 static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
85 struct device_attribute *attr,
86 char *buf)
87 {
88 int ret;
89 cpumask_t cpumask;
90
91 cpumask = pcibus_to_cpumask(to_pci_bus(dev));
92 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
93 if (ret < PAGE_SIZE)
94 buf[ret++] = '\n';
95 return ret;
96 }
97 DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
98
99 /*
100 * PCI Bus Class
101 */
102 static void release_pcibus_dev(struct device *dev)
103 {
104 struct pci_bus *pci_bus = to_pci_bus(dev);
105
106 if (pci_bus->bridge)
107 put_device(pci_bus->bridge);
108 kfree(pci_bus);
109 }
110
111 static struct class pcibus_class = {
112 .name = "pci_bus",
113 .dev_release = &release_pcibus_dev,
114 };
115
116 static int __init pcibus_class_init(void)
117 {
118 return class_register(&pcibus_class);
119 }
120 postcore_initcall(pcibus_class_init);
121
122 /*
123 * Translate the low bits of the PCI base
124 * to the resource type
125 */
126 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
127 {
128 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
129 return IORESOURCE_IO;
130
131 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
132 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
133
134 return IORESOURCE_MEM;
135 }
136
137 /*
138 * Find the extent of a PCI decode..
139 */
140 static u32 pci_size(u32 base, u32 maxbase, u32 mask)
141 {
142 u32 size = mask & maxbase; /* Find the significant bits */
143 if (!size)
144 return 0;
145
146 /* Get the lowest of them to find the decode size, and
147 from that the extent. */
148 size = (size & ~(size-1)) - 1;
149
150 /* base == maxbase can be valid only if the BAR has
151 already been programmed with all 1s. */
152 if (base == maxbase && ((base | size) & mask) != mask)
153 return 0;
154
155 return size;
156 }
157
158 static u64 pci_size64(u64 base, u64 maxbase, u64 mask)
159 {
160 u64 size = mask & maxbase; /* Find the significant bits */
161 if (!size)
162 return 0;
163
164 /* Get the lowest of them to find the decode size, and
165 from that the extent. */
166 size = (size & ~(size-1)) - 1;
167
168 /* base == maxbase can be valid only if the BAR has
169 already been programmed with all 1s. */
170 if (base == maxbase && ((base | size) & mask) != mask)
171 return 0;
172
173 return size;
174 }
175
176 static inline int is_64bit_memory(u32 mask)
177 {
178 if ((mask & (PCI_BASE_ADDRESS_SPACE|PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
179 (PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64))
180 return 1;
181 return 0;
182 }
183
184 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
185 {
186 unsigned int pos, reg, next;
187 u32 l, sz;
188 struct resource *res;
189
190 for(pos=0; pos<howmany; pos = next) {
191 u64 l64;
192 u64 sz64;
193 u32 raw_sz;
194
195 next = pos+1;
196 res = &dev->resource[pos];
197 res->name = pci_name(dev);
198 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
199 pci_read_config_dword(dev, reg, &l);
200 pci_write_config_dword(dev, reg, ~0);
201 pci_read_config_dword(dev, reg, &sz);
202 pci_write_config_dword(dev, reg, l);
203 if (!sz || sz == 0xffffffff)
204 continue;
205 if (l == 0xffffffff)
206 l = 0;
207 raw_sz = sz;
208 if ((l & PCI_BASE_ADDRESS_SPACE) ==
209 PCI_BASE_ADDRESS_SPACE_MEMORY) {
210 sz = pci_size(l, sz, (u32)PCI_BASE_ADDRESS_MEM_MASK);
211 /*
212 * For 64bit prefetchable memory sz could be 0, if the
213 * real size is bigger than 4G, so we need to check
214 * szhi for that.
215 */
216 if (!is_64bit_memory(l) && !sz)
217 continue;
218 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
219 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
220 } else {
221 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
222 if (!sz)
223 continue;
224 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
225 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
226 }
227 res->end = res->start + (unsigned long) sz;
228 res->flags |= pci_calc_resource_flags(l);
229 if (is_64bit_memory(l)) {
230 u32 szhi, lhi;
231
232 pci_read_config_dword(dev, reg+4, &lhi);
233 pci_write_config_dword(dev, reg+4, ~0);
234 pci_read_config_dword(dev, reg+4, &szhi);
235 pci_write_config_dword(dev, reg+4, lhi);
236 sz64 = ((u64)szhi << 32) | raw_sz;
237 l64 = ((u64)lhi << 32) | l;
238 sz64 = pci_size64(l64, sz64, PCI_BASE_ADDRESS_MEM_MASK);
239 next++;
240 #if BITS_PER_LONG == 64
241 if (!sz64) {
242 res->start = 0;
243 res->end = 0;
244 res->flags = 0;
245 continue;
246 }
247 res->start = l64 & PCI_BASE_ADDRESS_MEM_MASK;
248 res->end = res->start + sz64;
249 #else
250 if (sz64 > 0x100000000ULL) {
251 printk(KERN_ERR "PCI: Unable to handle 64-bit "
252 "BAR for device %s\n", pci_name(dev));
253 res->start = 0;
254 res->flags = 0;
255 } else if (lhi) {
256 /* 64-bit wide address, treat as disabled */
257 pci_write_config_dword(dev, reg,
258 l & ~(u32)PCI_BASE_ADDRESS_MEM_MASK);
259 pci_write_config_dword(dev, reg+4, 0);
260 res->start = 0;
261 res->end = sz;
262 }
263 #endif
264 }
265 }
266 if (rom) {
267 dev->rom_base_reg = rom;
268 res = &dev->resource[PCI_ROM_RESOURCE];
269 res->name = pci_name(dev);
270 pci_read_config_dword(dev, rom, &l);
271 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
272 pci_read_config_dword(dev, rom, &sz);
273 pci_write_config_dword(dev, rom, l);
274 if (l == 0xffffffff)
275 l = 0;
276 if (sz && sz != 0xffffffff) {
277 sz = pci_size(l, sz, (u32)PCI_ROM_ADDRESS_MASK);
278 if (sz) {
279 res->flags = (l & IORESOURCE_ROM_ENABLE) |
280 IORESOURCE_MEM | IORESOURCE_PREFETCH |
281 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
282 res->start = l & PCI_ROM_ADDRESS_MASK;
283 res->end = res->start + (unsigned long) sz;
284 }
285 }
286 }
287 }
288
289 <<<<<<< HEAD:drivers/pci/probe.c
290 void pci_read_bridge_bases(struct pci_bus *child)
291 =======
292 void __devinit pci_read_bridge_bases(struct pci_bus *child)
293 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/pci/probe.c
294 {
295 struct pci_dev *dev = child->self;
296 u8 io_base_lo, io_limit_lo;
297 u16 mem_base_lo, mem_limit_lo;
298 unsigned long base, limit;
299 struct resource *res;
300 int i;
301
302 if (!dev) /* It's a host bus, nothing to read */
303 return;
304
305 if (dev->transparent) {
306 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
307 for(i = 3; i < PCI_BUS_NUM_RESOURCES; i++)
308 child->resource[i] = child->parent->resource[i - 3];
309 }
310
311 for(i=0; i<3; i++)
312 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
313
314 res = child->resource[0];
315 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
316 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
317 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
318 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
319
320 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
321 u16 io_base_hi, io_limit_hi;
322 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
323 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
324 base |= (io_base_hi << 16);
325 limit |= (io_limit_hi << 16);
326 }
327
328 if (base <= limit) {
329 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
330 if (!res->start)
331 res->start = base;
332 if (!res->end)
333 res->end = limit + 0xfff;
334 }
335
336 res = child->resource[1];
337 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
338 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
339 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
340 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
341 if (base <= limit) {
342 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
343 res->start = base;
344 res->end = limit + 0xfffff;
345 }
346
347 res = child->resource[2];
348 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
349 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
350 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
351 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
352
353 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
354 u32 mem_base_hi, mem_limit_hi;
355 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
356 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
357
358 /*
359 * Some bridges set the base > limit by default, and some
360 * (broken) BIOSes do not initialize them. If we find
361 * this, just assume they are not being used.
362 */
363 if (mem_base_hi <= mem_limit_hi) {
364 #if BITS_PER_LONG == 64
365 base |= ((long) mem_base_hi) << 32;
366 limit |= ((long) mem_limit_hi) << 32;
367 #else
368 if (mem_base_hi || mem_limit_hi) {
369 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for bridge %s\n", pci_name(dev));
370 return;
371 }
372 #endif
373 }
374 }
375 if (base <= limit) {
376 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
377 res->start = base;
378 res->end = limit + 0xfffff;
379 }
380 }
381
382 static struct pci_bus * pci_alloc_bus(void)
383 {
384 struct pci_bus *b;
385
386 b = kzalloc(sizeof(*b), GFP_KERNEL);
387 if (b) {
388 INIT_LIST_HEAD(&b->node);
389 INIT_LIST_HEAD(&b->children);
390 INIT_LIST_HEAD(&b->devices);
391 }
392 return b;
393 }
394
395 static struct pci_bus * __devinit
396 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
397 {
398 struct pci_bus *child;
399 int i;
400
401 /*
402 * Allocate a new bus, and inherit stuff from the parent..
403 */
404 child = pci_alloc_bus();
405 if (!child)
406 return NULL;
407
408 child->self = bridge;
409 child->parent = parent;
410 child->ops = parent->ops;
411 child->sysdata = parent->sysdata;
412 child->bus_flags = parent->bus_flags;
413 child->bridge = get_device(&bridge->dev);
414
415 /* initialize some portions of the bus device, but don't register it
416 * now as the parent is not properly set up yet. This device will get
417 * registered later in pci_bus_add_devices()
418 */
419 child->dev.class = &pcibus_class;
420 sprintf(child->dev.bus_id, "%04x:%02x", pci_domain_nr(child), busnr);
421
422 /*
423 * Set up the primary, secondary and subordinate
424 * bus numbers.
425 */
426 child->number = child->secondary = busnr;
427 child->primary = parent->secondary;
428 child->subordinate = 0xff;
429
430 /* Set up default resource pointers and names.. */
431 for (i = 0; i < 4; i++) {
432 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
433 child->resource[i]->name = child->name;
434 }
435 bridge->subordinate = child;
436
437 return child;
438 }
439
440 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
441 {
442 struct pci_bus *child;
443
444 child = pci_alloc_child_bus(parent, dev, busnr);
445 if (child) {
446 down_write(&pci_bus_sem);
447 list_add_tail(&child->node, &parent->children);
448 up_write(&pci_bus_sem);
449 }
450 return child;
451 }
452
453 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
454 {
455 struct pci_bus *parent = child->parent;
456
457 /* Attempts to fix that up are really dangerous unless
458 we're going to re-assign all bus numbers. */
459 if (!pcibios_assign_all_busses())
460 return;
461
462 while (parent->parent && parent->subordinate < max) {
463 parent->subordinate = max;
464 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
465 parent = parent->parent;
466 }
467 }
468
469 /*
470 * If it's a bridge, configure it and scan the bus behind it.
471 * For CardBus bridges, we don't scan behind as the devices will
472 * be handled by the bridge driver itself.
473 *
474 * We need to process bridges in two passes -- first we scan those
475 * already configured by the BIOS and after we are done with all of
476 * them, we proceed to assigning numbers to the remaining buses in
477 * order to avoid overlaps between old and new bus numbers.
478 */
479 <<<<<<< HEAD:drivers/pci/probe.c
480 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
481 =======
482 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
483 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/pci/probe.c
484 {
485 struct pci_bus *child;
486 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
487 u32 buses, i, j = 0;
488 u16 bctl;
489
490 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
491
492 pr_debug("PCI: Scanning behind PCI bridge %s, config %06x, pass %d\n",
493 pci_name(dev), buses & 0xffffff, pass);
494
495 /* Disable MasterAbortMode during probing to avoid reporting
496 of bus errors (in some architectures) */
497 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
498 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
499 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
500
501 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
502 unsigned int cmax, busnr;
503 /*
504 * Bus already configured by firmware, process it in the first
505 * pass and just note the configuration.
506 */
507 if (pass)
508 goto out;
509 busnr = (buses >> 8) & 0xFF;
510
511 /*
512 * If we already got to this bus through a different bridge,
513 * ignore it. This can happen with the i450NX chipset.
514 */
515 if (pci_find_bus(pci_domain_nr(bus), busnr)) {
516 printk(KERN_INFO "PCI: Bus %04x:%02x already known\n",
517 pci_domain_nr(bus), busnr);
518 goto out;
519 }
520
521 child = pci_add_new_bus(bus, dev, busnr);
522 if (!child)
523 goto out;
524 child->primary = buses & 0xFF;
525 child->subordinate = (buses >> 16) & 0xFF;
526 child->bridge_ctl = bctl;
527
528 cmax = pci_scan_child_bus(child);
529 if (cmax > max)
530 max = cmax;
531 if (child->subordinate > max)
532 max = child->subordinate;
533 } else {
534 /*
535 * We need to assign a number to this bus which we always
536 * do in the second pass.
537 */
538 if (!pass) {
539 if (pcibios_assign_all_busses())
540 /* Temporarily disable forwarding of the
541 configuration cycles on all bridges in
542 this bus segment to avoid possible
543 conflicts in the second pass between two
544 bridges programmed with overlapping
545 bus ranges. */
546 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
547 buses & ~0xffffff);
548 goto out;
549 }
550
551 /* Clear errors */
552 pci_write_config_word(dev, PCI_STATUS, 0xffff);
553
554 /* Prevent assigning a bus number that already exists.
555 * This can happen when a bridge is hot-plugged */
556 if (pci_find_bus(pci_domain_nr(bus), max+1))
557 goto out;
558 child = pci_add_new_bus(bus, dev, ++max);
559 buses = (buses & 0xff000000)
560 | ((unsigned int)(child->primary) << 0)
561 | ((unsigned int)(child->secondary) << 8)
562 | ((unsigned int)(child->subordinate) << 16);
563
564 /*
565 * yenta.c forces a secondary latency timer of 176.
566 * Copy that behaviour here.
567 */
568 if (is_cardbus) {
569 buses &= ~0xff000000;
570 buses |= CARDBUS_LATENCY_TIMER << 24;
571 }
572
573 /*
574 * We need to blast all three values with a single write.
575 */
576 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
577
578 if (!is_cardbus) {
579 child->bridge_ctl = bctl;
580 /*
581 * Adjust subordinate busnr in parent buses.
582 * We do this before scanning for children because
583 * some devices may not be detected if the bios
584 * was lazy.
585 */
586 pci_fixup_parent_subordinate_busnr(child, max);
587 /* Now we can scan all subordinate buses... */
588 max = pci_scan_child_bus(child);
589 /*
590 * now fix it up again since we have found
591 * the real value of max.
592 */
593 pci_fixup_parent_subordinate_busnr(child, max);
594 } else {
595 /*
596 * For CardBus bridges, we leave 4 bus numbers
597 * as cards with a PCI-to-PCI bridge can be
598 * inserted later.
599 */
600 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
601 struct pci_bus *parent = bus;
602 if (pci_find_bus(pci_domain_nr(bus),
603 max+i+1))
604 break;
605 while (parent->parent) {
606 if ((!pcibios_assign_all_busses()) &&
607 (parent->subordinate > max) &&
608 (parent->subordinate <= max+i)) {
609 j = 1;
610 }
611 parent = parent->parent;
612 }
613 if (j) {
614 /*
615 * Often, there are two cardbus bridges
616 * -- try to leave one valid bus number
617 * for each one.
618 */
619 i /= 2;
620 break;
621 }
622 }
623 max += i;
624 pci_fixup_parent_subordinate_busnr(child, max);
625 }
626 /*
627 * Set the subordinate bus number to its real value.
628 */
629 child->subordinate = max;
630 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
631 }
632
633 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
634
635 /* Has only triggered on CardBus, fixup is in yenta_socket */
636 while (bus->parent) {
637 if ((child->subordinate > bus->subordinate) ||
638 (child->number > bus->subordinate) ||
639 (child->number < bus->number) ||
640 (child->subordinate < bus->number)) {
641 pr_debug("PCI: Bus #%02x (-#%02x) is %s "
642 "hidden behind%s bridge #%02x (-#%02x)\n",
643 child->number, child->subordinate,
644 (bus->number > child->subordinate &&
645 bus->subordinate < child->number) ?
646 "wholly" : "partially",
647 bus->self->transparent ? " transparent" : "",
648 bus->number, bus->subordinate);
649 }
650 bus = bus->parent;
651 }
652
653 out:
654 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
655
656 return max;
657 }
658
659 /*
660 * Read interrupt line and base address registers.
661 * The architecture-dependent code can tweak these, of course.
662 */
663 static void pci_read_irq(struct pci_dev *dev)
664 {
665 unsigned char irq;
666
667 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
668 dev->pin = irq;
669 if (irq)
670 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
671 dev->irq = irq;
672 }
673
674 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
675
676 /**
677 * pci_setup_device - fill in class and map information of a device
678 * @dev: the device structure to fill
679 *
680 * Initialize the device structure with information about the device's
681 * vendor,class,memory and IO-space addresses,IRQ lines etc.
682 * Called at initialisation of the PCI subsystem and by CardBus services.
683 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
684 * or CardBus).
685 */
686 static int pci_setup_device(struct pci_dev * dev)
687 {
688 u32 class;
689
690 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
691 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
692
693 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
694 dev->revision = class & 0xff;
695 class >>= 8; /* upper 3 bytes */
696 dev->class = class;
697 class >>= 8;
698
699 pr_debug("PCI: Found %s [%04x/%04x] %06x %02x\n", pci_name(dev),
700 dev->vendor, dev->device, class, dev->hdr_type);
701
702 /* "Unknown power state" */
703 dev->current_state = PCI_UNKNOWN;
704
705 /* Early fixups, before probing the BARs */
706 pci_fixup_device(pci_fixup_early, dev);
707 class = dev->class >> 8;
708
709 switch (dev->hdr_type) { /* header type */
710 case PCI_HEADER_TYPE_NORMAL: /* standard header */
711 if (class == PCI_CLASS_BRIDGE_PCI)
712 goto bad;
713 pci_read_irq(dev);
714 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
715 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
716 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
717
718 /*
719 * Do the ugly legacy mode stuff here rather than broken chip
720 * quirk code. Legacy mode ATA controllers have fixed
721 * addresses. These are not always echoed in BAR0-3, and
722 * BAR0-3 in a few cases contain junk!
723 */
724 if (class == PCI_CLASS_STORAGE_IDE) {
725 u8 progif;
726 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
727 if ((progif & 1) == 0) {
728 dev->resource[0].start = 0x1F0;
729 dev->resource[0].end = 0x1F7;
730 dev->resource[0].flags = LEGACY_IO_RESOURCE;
731 dev->resource[1].start = 0x3F6;
732 dev->resource[1].end = 0x3F6;
733 dev->resource[1].flags = LEGACY_IO_RESOURCE;
734 }
735 if ((progif & 4) == 0) {
736 dev->resource[2].start = 0x170;
737 dev->resource[2].end = 0x177;
738 dev->resource[2].flags = LEGACY_IO_RESOURCE;
739 dev->resource[3].start = 0x376;
740 dev->resource[3].end = 0x376;
741 dev->resource[3].flags = LEGACY_IO_RESOURCE;
742 }
743 }
744 break;
745
746 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
747 if (class != PCI_CLASS_BRIDGE_PCI)
748 goto bad;
749 /* The PCI-to-PCI bridge spec requires that subtractive
750 decoding (i.e. transparent) bridge must have programming
751 interface code of 0x01. */
752 pci_read_irq(dev);
753 dev->transparent = ((dev->class & 0xff) == 1);
754 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
755 break;
756
757 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
758 if (class != PCI_CLASS_BRIDGE_CARDBUS)
759 goto bad;
760 pci_read_irq(dev);
761 pci_read_bases(dev, 1, 0);
762 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
763 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
764 break;
765
766 default: /* unknown header */
767 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
768 pci_name(dev), dev->hdr_type);
769 return -1;
770
771 bad:
772 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
773 pci_name(dev), class, dev->hdr_type);
774 dev->class = PCI_CLASS_NOT_DEFINED;
775 }
776
777 /* We found a fine healthy device, go go go... */
778 return 0;
779 }
780
781 /**
782 * pci_release_dev - free a pci device structure when all users of it are finished.
783 * @dev: device that's been disconnected
784 *
785 * Will be called only by the device core when all users of this pci device are
786 * done.
787 */
788 static void pci_release_dev(struct device *dev)
789 {
790 struct pci_dev *pci_dev;
791
792 pci_dev = to_pci_dev(dev);
793 kfree(pci_dev);
794 }
795
796 static void set_pcie_port_type(struct pci_dev *pdev)
797 {
798 int pos;
799 u16 reg16;
800
801 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
802 if (!pos)
803 return;
804 pdev->is_pcie = 1;
805 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
806 pdev->pcie_type = (reg16 & PCI_EXP_FLAGS_TYPE) >> 4;
807 }
808
809 /**
810 * pci_cfg_space_size - get the configuration space size of the PCI device.
811 * @dev: PCI device
812 *
813 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
814 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
815 * access it. Maybe we don't have a way to generate extended config space
816 * accesses, or the device is behind a reverse Express bridge. So we try
817 * reading the dword at 0x100 which must either be 0 or a valid extended
818 * capability header.
819 */
820 int pci_cfg_space_size(struct pci_dev *dev)
821 {
822 int pos;
823 u32 status;
824
825 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
826 if (!pos) {
827 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
828 if (!pos)
829 goto fail;
830
831 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
832 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
833 goto fail;
834 }
835
836 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
837 goto fail;
838 if (status == 0xffffffff)
839 goto fail;
840
841 return PCI_CFG_SPACE_EXP_SIZE;
842
843 fail:
844 return PCI_CFG_SPACE_SIZE;
845 }
846
847 static void pci_release_bus_bridge_dev(struct device *dev)
848 {
849 kfree(dev);
850 }
851
852 struct pci_dev *alloc_pci_dev(void)
853 {
854 struct pci_dev *dev;
855
856 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
857 if (!dev)
858 return NULL;
859
860 INIT_LIST_HEAD(&dev->global_list);
861 INIT_LIST_HEAD(&dev->bus_list);
862
863 pci_msi_init_pci_dev(dev);
864
865 return dev;
866 }
867 EXPORT_SYMBOL(alloc_pci_dev);
868
869 /*
870 * Read the config data for a PCI device, sanity-check it
871 * and fill in the dev structure...
872 */
873 static struct pci_dev * __devinit
874 pci_scan_device(struct pci_bus *bus, int devfn)
875 {
876 struct pci_dev *dev;
877 u32 l;
878 u8 hdr_type;
879 int delay = 1;
880
881 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
882 return NULL;
883
884 /* some broken boards return 0 or ~0 if a slot is empty: */
885 if (l == 0xffffffff || l == 0x00000000 ||
886 l == 0x0000ffff || l == 0xffff0000)
887 return NULL;
888
889 /* Configuration request Retry Status */
890 while (l == 0xffff0001) {
891 msleep(delay);
892 delay *= 2;
893 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
894 return NULL;
895 /* Card hasn't responded in 60 seconds? Must be stuck. */
896 if (delay > 60 * 1000) {
897 printk(KERN_WARNING "Device %04x:%02x:%02x.%d not "
898 "responding\n", pci_domain_nr(bus),
899 bus->number, PCI_SLOT(devfn),
900 PCI_FUNC(devfn));
901 return NULL;
902 }
903 }
904
905 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
906 return NULL;
907
908 dev = alloc_pci_dev();
909 if (!dev)
910 return NULL;
911
912 dev->bus = bus;
913 dev->sysdata = bus->sysdata;
914 dev->dev.parent = bus->bridge;
915 dev->dev.bus = &pci_bus_type;
916 dev->devfn = devfn;
917 dev->hdr_type = hdr_type & 0x7f;
918 dev->multifunction = !!(hdr_type & 0x80);
919 dev->vendor = l & 0xffff;
920 dev->device = (l >> 16) & 0xffff;
921 dev->cfg_size = pci_cfg_space_size(dev);
922 dev->error_state = pci_channel_io_normal;
923 set_pcie_port_type(dev);
924
925 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
926 set this higher, assuming the system even supports it. */
927 dev->dma_mask = 0xffffffff;
928 if (pci_setup_device(dev) < 0) {
929 kfree(dev);
930 return NULL;
931 }
932
933 return dev;
934 }
935
936 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
937 {
938 device_initialize(&dev->dev);
939 dev->dev.release = pci_release_dev;
940 pci_dev_get(dev);
941
942 set_dev_node(&dev->dev, pcibus_to_node(bus));
943 dev->dev.dma_mask = &dev->dma_mask;
944 dev->dev.dma_parms = &dev->dma_parms;
945 dev->dev.coherent_dma_mask = 0xffffffffull;
946
947 pci_set_dma_max_seg_size(dev, 65536);
948 pci_set_dma_seg_boundary(dev, 0xffffffff);
949
950 /* Fix up broken headers */
951 pci_fixup_device(pci_fixup_header, dev);
952
953 /*
954 * Add the device to our list of discovered devices
955 * and the bus list for fixup functions, etc.
956 */
957 INIT_LIST_HEAD(&dev->global_list);
958 down_write(&pci_bus_sem);
959 list_add_tail(&dev->bus_list, &bus->devices);
960 up_write(&pci_bus_sem);
961 }
962
963 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
964 {
965 struct pci_dev *dev;
966
967 dev = pci_scan_device(bus, devfn);
968 if (!dev)
969 return NULL;
970
971 pci_device_add(dev, bus);
972
973 return dev;
974 }
975 EXPORT_SYMBOL(pci_scan_single_device);
976
977 /**
978 * pci_scan_slot - scan a PCI slot on a bus for devices.
979 * @bus: PCI bus to scan
980 * @devfn: slot number to scan (must have zero function.)
981 *
982 * Scan a PCI slot on the specified PCI bus for devices, adding
983 * discovered devices to the @bus->devices list. New devices
984 * will have an empty dev->global_list head.
985 */
986 int pci_scan_slot(struct pci_bus *bus, int devfn)
987 {
988 int func, nr = 0;
989 int scan_all_fns;
990
991 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
992
993 for (func = 0; func < 8; func++, devfn++) {
994 struct pci_dev *dev;
995
996 dev = pci_scan_single_device(bus, devfn);
997 if (dev) {
998 nr++;
999
1000 /*
1001 * If this is a single function device,
1002 * don't scan past the first function.
1003 */
1004 if (!dev->multifunction) {
1005 if (func > 0) {
1006 dev->multifunction = 1;
1007 } else {
1008 break;
1009 }
1010 }
1011 } else {
1012 if (func == 0 && !scan_all_fns)
1013 break;
1014 }
1015 }
1016 return nr;
1017 }
1018
1019 <<<<<<< HEAD:drivers/pci/probe.c
1020 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1021 =======
1022 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
1023 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/pci/probe.c
1024 {
1025 unsigned int devfn, pass, max = bus->secondary;
1026 struct pci_dev *dev;
1027
1028 pr_debug("PCI: Scanning bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1029
1030 /* Go find them, Rover! */
1031 for (devfn = 0; devfn < 0x100; devfn += 8)
1032 pci_scan_slot(bus, devfn);
1033
1034 /*
1035 * After performing arch-dependent fixup of the bus, look behind
1036 * all PCI-to-PCI bridges on this bus.
1037 */
1038 pr_debug("PCI: Fixups for bus %04x:%02x\n", pci_domain_nr(bus), bus->number);
1039 pcibios_fixup_bus(bus);
1040 for (pass=0; pass < 2; pass++)
1041 list_for_each_entry(dev, &bus->devices, bus_list) {
1042 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1043 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1044 max = pci_scan_bridge(bus, dev, max, pass);
1045 }
1046
1047 /*
1048 * We've scanned the bus and so we know all about what's on
1049 * the other side of any bridges that may be on this bus plus
1050 * any devices.
1051 *
1052 * Return how far we've got finding sub-buses.
1053 */
1054 pr_debug("PCI: Bus scan for %04x:%02x returning with max=%02x\n",
1055 pci_domain_nr(bus), bus->number, max);
1056 return max;
1057 }
1058
1059 struct pci_bus * pci_create_bus(struct device *parent,
1060 int bus, struct pci_ops *ops, void *sysdata)
1061 {
1062 int error;
1063 struct pci_bus *b;
1064 struct device *dev;
1065
1066 b = pci_alloc_bus();
1067 if (!b)
1068 return NULL;
1069
1070 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
1071 if (!dev){
1072 kfree(b);
1073 return NULL;
1074 }
1075
1076 b->sysdata = sysdata;
1077 b->ops = ops;
1078
1079 if (pci_find_bus(pci_domain_nr(b), bus)) {
1080 /* If we already got to this bus through a different bridge, ignore it */
1081 pr_debug("PCI: Bus %04x:%02x already known\n", pci_domain_nr(b), bus);
1082 goto err_out;
1083 }
1084
1085 down_write(&pci_bus_sem);
1086 list_add_tail(&b->node, &pci_root_buses);
1087 up_write(&pci_bus_sem);
1088
1089 memset(dev, 0, sizeof(*dev));
1090 dev->parent = parent;
1091 dev->release = pci_release_bus_bridge_dev;
1092 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
1093 error = device_register(dev);
1094 if (error)
1095 goto dev_reg_err;
1096 b->bridge = get_device(dev);
1097
1098 b->dev.class = &pcibus_class;
1099 b->dev.parent = b->bridge;
1100 sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
1101 error = device_register(&b->dev);
1102 if (error)
1103 goto class_dev_reg_err;
1104 error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
1105 if (error)
1106 goto dev_create_file_err;
1107
1108 /* Create legacy_io and legacy_mem files for this bus */
1109 pci_create_legacy_files(b);
1110
1111 b->number = b->secondary = bus;
1112 b->resource[0] = &ioport_resource;
1113 b->resource[1] = &iomem_resource;
1114
1115 return b;
1116
1117 dev_create_file_err:
1118 device_unregister(&b->dev);
1119 class_dev_reg_err:
1120 device_unregister(dev);
1121 dev_reg_err:
1122 down_write(&pci_bus_sem);
1123 list_del(&b->node);
1124 up_write(&pci_bus_sem);
1125 err_out:
1126 kfree(dev);
1127 kfree(b);
1128 return NULL;
1129 }
1130
1131 <<<<<<< HEAD:drivers/pci/probe.c
1132 struct pci_bus *pci_scan_bus_parented(struct device *parent,
1133 =======
1134 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent,
1135 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/pci/probe.c
1136 int bus, struct pci_ops *ops, void *sysdata)
1137 {
1138 struct pci_bus *b;
1139
1140 b = pci_create_bus(parent, bus, ops, sysdata);
1141 if (b)
1142 b->subordinate = pci_scan_child_bus(b);
1143 return b;
1144 }
1145 EXPORT_SYMBOL(pci_scan_bus_parented);
1146
1147 #ifdef CONFIG_HOTPLUG
1148 EXPORT_SYMBOL(pci_add_new_bus);
1149 EXPORT_SYMBOL(pci_scan_slot);
1150 EXPORT_SYMBOL(pci_scan_bridge);
1151 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1152 #endif
1153
1154 static int __init pci_sort_bf_cmp(const struct pci_dev *a, const struct pci_dev *b)
1155 {
1156 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1157 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1158
1159 if (a->bus->number < b->bus->number) return -1;
1160 else if (a->bus->number > b->bus->number) return 1;
1161
1162 if (a->devfn < b->devfn) return -1;
1163 else if (a->devfn > b->devfn) return 1;
1164
1165 return 0;
1166 }
1167
1168 /*
1169 * Yes, this forcably breaks the klist abstraction temporarily. It
1170 * just wants to sort the klist, not change reference counts and
1171 * take/drop locks rapidly in the process. It does all this while
1172 * holding the lock for the list, so objects can't otherwise be
1173 * added/removed while we're swizzling.
1174 */
1175 static void __init pci_insertion_sort_klist(struct pci_dev *a, struct list_head *list)
1176 {
1177 struct list_head *pos;
1178 struct klist_node *n;
1179 struct device *dev;
1180 struct pci_dev *b;
1181
1182 list_for_each(pos, list) {
1183 n = container_of(pos, struct klist_node, n_node);
1184 dev = container_of(n, struct device, knode_bus);
1185 b = to_pci_dev(dev);
1186 if (pci_sort_bf_cmp(a, b) <= 0) {
1187 list_move_tail(&a->dev.knode_bus.n_node, &b->dev.knode_bus.n_node);
1188 return;
1189 }
1190 }
1191 list_move_tail(&a->dev.knode_bus.n_node, list);
1192 }
1193
1194 static void __init pci_sort_breadthfirst_klist(void)
1195 {
1196 LIST_HEAD(sorted_devices);
1197 struct list_head *pos, *tmp;
1198 struct klist_node *n;
1199 struct device *dev;
1200 struct pci_dev *pdev;
1201 struct klist *device_klist;
1202
1203 device_klist = bus_get_device_klist(&pci_bus_type);
1204
1205 spin_lock(&device_klist->k_lock);
1206 list_for_each_safe(pos, tmp, &device_klist->k_list) {
1207 n = container_of(pos, struct klist_node, n_node);
1208 dev = container_of(n, struct device, knode_bus);
1209 pdev = to_pci_dev(dev);
1210 pci_insertion_sort_klist(pdev, &sorted_devices);
1211 }
1212 list_splice(&sorted_devices, &device_klist->k_list);
1213 spin_unlock(&device_klist->k_lock);
1214 }
1215
1216 static void __init pci_insertion_sort_devices(struct pci_dev *a, struct list_head *list)
1217 {
1218 struct pci_dev *b;
1219
1220 list_for_each_entry(b, list, global_list) {
1221 if (pci_sort_bf_cmp(a, b) <= 0) {
1222 list_move_tail(&a->global_list, &b->global_list);
1223 return;
1224 }
1225 }
1226 list_move_tail(&a->global_list, list);
1227 }
1228
1229 static void __init pci_sort_breadthfirst_devices(void)
1230 {
1231 LIST_HEAD(sorted_devices);
1232 struct pci_dev *dev, *tmp;
1233
1234 down_write(&pci_bus_sem);
1235 list_for_each_entry_safe(dev, tmp, &pci_devices, global_list) {
1236 pci_insertion_sort_devices(dev, &sorted_devices);
1237 }
1238 list_splice(&sorted_devices, &pci_devices);
1239 up_write(&pci_bus_sem);
1240 }
1241
1242 void __init pci_sort_breadthfirst(void)
1243 {
1244 pci_sort_breadthfirst_devices();
1245 pci_sort_breadthfirst_klist();
1246 }
1247
WRT350N Kernel Patches