Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / net / mv643xx_eth.c
blob25d92256ae6bd4c7745e358bf2051572e39957a6
1 /*
2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 rabeeh@galileo.co.il
8 * Copyright (C) 2003 PMC-Sierra, Inc.,
9 * written by Manish Lachwani
11 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
13 * Copyright (C) 2004-2006 MontaVista Software, Inc.
14 * Dale Farnsworth <dale@farnsworth.org>
16 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
17 * <sjhill@realitydiluted.com>
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version 2
22 * of the License, or (at your option) any later version.
24 * This program is distributed in the hope that it will be useful,
25 * but WITHOUT ANY WARRANTY; without even the implied warranty of
26 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
27 * GNU General Public License for more details.
29 * You should have received a copy of the GNU General Public License
30 * along with this program; if not, write to the Free Software
31 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
33 #include <linux/init.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/in.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/udp.h>
39 #include <linux/etherdevice.h>
41 #include <linux/bitops.h>
42 #include <linux/delay.h>
43 #include <linux/ethtool.h>
44 #include <linux/platform_device.h>
46 #include <linux/module.h>
47 #include <linux/kernel.h>
48 #include <linux/spinlock.h>
49 #include <linux/workqueue.h>
50 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/io.h>
55 #include <asm/types.h>
56 #include <asm/pgtable.h>
57 #include <asm/system.h>
58 #include <asm/delay.h>
59 #include <asm/dma-mapping.h>
61 #define MV643XX_CHECKSUM_OFFLOAD_TX
62 #define MV643XX_NAPI
63 #define MV643XX_TX_FAST_REFILL
64 #undef MV643XX_COAL
67 * Number of RX / TX descriptors on RX / TX rings.
68 * Note that allocating RX descriptors is done by allocating the RX
69 * ring AND a preallocated RX buffers (skb's) for each descriptor.
70 * The TX descriptors only allocates the TX descriptors ring,
71 * with no pre allocated TX buffers (skb's are allocated by higher layers.
74 /* Default TX ring size is 1000 descriptors */
75 #define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
77 /* Default RX ring size is 400 descriptors */
78 #define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
80 #define MV643XX_TX_COAL 100
81 #ifdef MV643XX_COAL
82 #define MV643XX_RX_COAL 100
83 #endif
85 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
86 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
87 #else
88 #define MAX_DESCS_PER_SKB 1
89 #endif
91 #define ETH_VLAN_HLEN 4
92 #define ETH_FCS_LEN 4
93 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
94 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
95 ETH_VLAN_HLEN + ETH_FCS_LEN)
96 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
97 dma_get_cache_alignment())
100 * Registers shared between all ports.
102 #define PHY_ADDR_REG 0x0000
103 #define SMI_REG 0x0004
106 * Per-port registers.
108 #define PORT_CONFIG_REG(p) (0x0400 + ((p) << 10))
109 #define PORT_CONFIG_EXTEND_REG(p) (0x0404 + ((p) << 10))
110 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
111 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
112 #define SDMA_CONFIG_REG(p) (0x041c + ((p) << 10))
113 #define PORT_SERIAL_CONTROL_REG(p) (0x043c + ((p) << 10))
114 #define PORT_STATUS_REG(p) (0x0444 + ((p) << 10))
115 #define TRANSMIT_QUEUE_COMMAND_REG(p) (0x0448 + ((p) << 10))
116 #define MAXIMUM_TRANSMIT_UNIT(p) (0x0458 + ((p) << 10))
117 #define INTERRUPT_CAUSE_REG(p) (0x0460 + ((p) << 10))
118 #define INTERRUPT_CAUSE_EXTEND_REG(p) (0x0464 + ((p) << 10))
119 #define INTERRUPT_MASK_REG(p) (0x0468 + ((p) << 10))
120 #define INTERRUPT_EXTEND_MASK_REG(p) (0x046c + ((p) << 10))
121 #define TX_FIFO_URGENT_THRESHOLD_REG(p) (0x0474 + ((p) << 10))
122 #define RX_CURRENT_QUEUE_DESC_PTR_0(p) (0x060c + ((p) << 10))
123 #define RECEIVE_QUEUE_COMMAND_REG(p) (0x0680 + ((p) << 10))
124 #define TX_CURRENT_QUEUE_DESC_PTR_0(p) (0x06c0 + ((p) << 10))
125 #define MIB_COUNTERS_BASE(p) (0x1000 + ((p) << 7))
126 #define DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(p) (0x1400 + ((p) << 10))
127 #define DA_FILTER_OTHER_MULTICAST_TABLE_BASE(p) (0x1500 + ((p) << 10))
128 #define DA_FILTER_UNICAST_TABLE_BASE(p) (0x1600 + ((p) << 10))
130 /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
131 #define UNICAST_NORMAL_MODE (0 << 0)
132 #define UNICAST_PROMISCUOUS_MODE (1 << 0)
133 #define DEFAULT_RX_QUEUE(queue) ((queue) << 1)
134 #define DEFAULT_RX_ARP_QUEUE(queue) ((queue) << 4)
135 #define RECEIVE_BC_IF_NOT_IP_OR_ARP (0 << 7)
136 #define REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
137 #define RECEIVE_BC_IF_IP (0 << 8)
138 #define REJECT_BC_IF_IP (1 << 8)
139 #define RECEIVE_BC_IF_ARP (0 << 9)
140 #define REJECT_BC_IF_ARP (1 << 9)
141 #define TX_AM_NO_UPDATE_ERROR_SUMMARY (1 << 12)
142 #define CAPTURE_TCP_FRAMES_DIS (0 << 14)
143 #define CAPTURE_TCP_FRAMES_EN (1 << 14)
144 #define CAPTURE_UDP_FRAMES_DIS (0 << 15)
145 #define CAPTURE_UDP_FRAMES_EN (1 << 15)
146 #define DEFAULT_RX_TCP_QUEUE(queue) ((queue) << 16)
147 #define DEFAULT_RX_UDP_QUEUE(queue) ((queue) << 19)
148 #define DEFAULT_RX_BPDU_QUEUE(queue) ((queue) << 22)
150 #define PORT_CONFIG_DEFAULT_VALUE \
151 UNICAST_NORMAL_MODE | \
152 DEFAULT_RX_QUEUE(0) | \
153 DEFAULT_RX_ARP_QUEUE(0) | \
154 RECEIVE_BC_IF_NOT_IP_OR_ARP | \
155 RECEIVE_BC_IF_IP | \
156 RECEIVE_BC_IF_ARP | \
157 CAPTURE_TCP_FRAMES_DIS | \
158 CAPTURE_UDP_FRAMES_DIS | \
159 DEFAULT_RX_TCP_QUEUE(0) | \
160 DEFAULT_RX_UDP_QUEUE(0) | \
161 DEFAULT_RX_BPDU_QUEUE(0)
163 /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
164 #define CLASSIFY_EN (1 << 0)
165 #define SPAN_BPDU_PACKETS_AS_NORMAL (0 << 1)
166 #define SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1 << 1)
167 #define PARTITION_DISABLE (0 << 2)
168 #define PARTITION_ENABLE (1 << 2)
170 #define PORT_CONFIG_EXTEND_DEFAULT_VALUE \
171 SPAN_BPDU_PACKETS_AS_NORMAL | \
172 PARTITION_DISABLE
174 /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
175 #define RIFB (1 << 0)
176 #define RX_BURST_SIZE_1_64BIT (0 << 1)
177 #define RX_BURST_SIZE_2_64BIT (1 << 1)
178 #define RX_BURST_SIZE_4_64BIT (2 << 1)
179 #define RX_BURST_SIZE_8_64BIT (3 << 1)
180 #define RX_BURST_SIZE_16_64BIT (4 << 1)
181 #define BLM_RX_NO_SWAP (1 << 4)
182 #define BLM_RX_BYTE_SWAP (0 << 4)
183 #define BLM_TX_NO_SWAP (1 << 5)
184 #define BLM_TX_BYTE_SWAP (0 << 5)
185 #define DESCRIPTORS_BYTE_SWAP (1 << 6)
186 #define DESCRIPTORS_NO_SWAP (0 << 6)
187 #define IPG_INT_RX(value) (((value) & 0x3fff) << 8)
188 #define TX_BURST_SIZE_1_64BIT (0 << 22)
189 #define TX_BURST_SIZE_2_64BIT (1 << 22)
190 #define TX_BURST_SIZE_4_64BIT (2 << 22)
191 #define TX_BURST_SIZE_8_64BIT (3 << 22)
192 #define TX_BURST_SIZE_16_64BIT (4 << 22)
194 #if defined(__BIG_ENDIAN)
195 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
196 RX_BURST_SIZE_4_64BIT | \
197 IPG_INT_RX(0) | \
198 TX_BURST_SIZE_4_64BIT
199 #elif defined(__LITTLE_ENDIAN)
200 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
201 RX_BURST_SIZE_4_64BIT | \
202 BLM_RX_NO_SWAP | \
203 BLM_TX_NO_SWAP | \
204 IPG_INT_RX(0) | \
205 TX_BURST_SIZE_4_64BIT
206 #else
207 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
208 #endif
210 /* These macros describe Ethernet Port serial control reg (PSCR) bits */
211 #define SERIAL_PORT_DISABLE (0 << 0)
212 #define SERIAL_PORT_ENABLE (1 << 0)
213 #define DO_NOT_FORCE_LINK_PASS (0 << 1)
214 #define FORCE_LINK_PASS (1 << 1)
215 #define ENABLE_AUTO_NEG_FOR_DUPLX (0 << 2)
216 #define DISABLE_AUTO_NEG_FOR_DUPLX (1 << 2)
217 #define ENABLE_AUTO_NEG_FOR_FLOW_CTRL (0 << 3)
218 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
219 #define ADV_NO_FLOW_CTRL (0 << 4)
220 #define ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
221 #define FORCE_FC_MODE_NO_PAUSE_DIS_TX (0 << 5)
222 #define FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
223 #define FORCE_BP_MODE_NO_JAM (0 << 7)
224 #define FORCE_BP_MODE_JAM_TX (1 << 7)
225 #define FORCE_BP_MODE_JAM_TX_ON_RX_ERR (2 << 7)
226 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
227 #define FORCE_LINK_FAIL (0 << 10)
228 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
229 #define RETRANSMIT_16_ATTEMPTS (0 << 11)
230 #define RETRANSMIT_FOREVER (1 << 11)
231 #define ENABLE_AUTO_NEG_SPEED_GMII (0 << 13)
232 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
233 #define DTE_ADV_0 (0 << 14)
234 #define DTE_ADV_1 (1 << 14)
235 #define DISABLE_AUTO_NEG_BYPASS (0 << 15)
236 #define ENABLE_AUTO_NEG_BYPASS (1 << 15)
237 #define AUTO_NEG_NO_CHANGE (0 << 16)
238 #define RESTART_AUTO_NEG (1 << 16)
239 #define MAX_RX_PACKET_1518BYTE (0 << 17)
240 #define MAX_RX_PACKET_1522BYTE (1 << 17)
241 #define MAX_RX_PACKET_1552BYTE (2 << 17)
242 #define MAX_RX_PACKET_9022BYTE (3 << 17)
243 #define MAX_RX_PACKET_9192BYTE (4 << 17)
244 #define MAX_RX_PACKET_9700BYTE (5 << 17)
245 #define MAX_RX_PACKET_MASK (7 << 17)
246 #define CLR_EXT_LOOPBACK (0 << 20)
247 #define SET_EXT_LOOPBACK (1 << 20)
248 #define SET_HALF_DUPLEX_MODE (0 << 21)
249 #define SET_FULL_DUPLEX_MODE (1 << 21)
250 #define DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (0 << 22)
251 #define ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
252 #define SET_GMII_SPEED_TO_10_100 (0 << 23)
253 #define SET_GMII_SPEED_TO_1000 (1 << 23)
254 #define SET_MII_SPEED_TO_10 (0 << 24)
255 #define SET_MII_SPEED_TO_100 (1 << 24)
257 #define PORT_SERIAL_CONTROL_DEFAULT_VALUE \
258 DO_NOT_FORCE_LINK_PASS | \
259 ENABLE_AUTO_NEG_FOR_DUPLX | \
260 DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
261 ADV_SYMMETRIC_FLOW_CTRL | \
262 FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
263 FORCE_BP_MODE_NO_JAM | \
264 (1 << 9) /* reserved */ | \
265 DO_NOT_FORCE_LINK_FAIL | \
266 RETRANSMIT_16_ATTEMPTS | \
267 ENABLE_AUTO_NEG_SPEED_GMII | \
268 DTE_ADV_0 | \
269 DISABLE_AUTO_NEG_BYPASS | \
270 AUTO_NEG_NO_CHANGE | \
271 MAX_RX_PACKET_9700BYTE | \
272 CLR_EXT_LOOPBACK | \
273 SET_FULL_DUPLEX_MODE | \
274 ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
276 /* These macros describe Ethernet Serial Status reg (PSR) bits */
277 #define PORT_STATUS_MODE_10_BIT (1 << 0)
278 #define PORT_STATUS_LINK_UP (1 << 1)
279 #define PORT_STATUS_FULL_DUPLEX (1 << 2)
280 #define PORT_STATUS_FLOW_CONTROL (1 << 3)
281 #define PORT_STATUS_GMII_1000 (1 << 4)
282 #define PORT_STATUS_MII_100 (1 << 5)
283 /* PSR bit 6 is undocumented */
284 #define PORT_STATUS_TX_IN_PROGRESS (1 << 7)
285 #define PORT_STATUS_AUTONEG_BYPASSED (1 << 8)
286 #define PORT_STATUS_PARTITION (1 << 9)
287 #define PORT_STATUS_TX_FIFO_EMPTY (1 << 10)
288 /* PSR bits 11-31 are reserved */
290 #define PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
291 #define PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
293 #define DESC_SIZE 64
295 #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */
296 #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */
298 #define ETH_INT_CAUSE_RX_DONE (ETH_RX_QUEUES_ENABLED << 2)
299 #define ETH_INT_CAUSE_RX_ERROR (ETH_RX_QUEUES_ENABLED << 9)
300 #define ETH_INT_CAUSE_RX (ETH_INT_CAUSE_RX_DONE | ETH_INT_CAUSE_RX_ERROR)
301 #define ETH_INT_CAUSE_EXT 0x00000002
302 #define ETH_INT_UNMASK_ALL (ETH_INT_CAUSE_RX | ETH_INT_CAUSE_EXT)
304 #define ETH_INT_CAUSE_TX_DONE (ETH_TX_QUEUES_ENABLED << 0)
305 #define ETH_INT_CAUSE_TX_ERROR (ETH_TX_QUEUES_ENABLED << 8)
306 #define ETH_INT_CAUSE_TX (ETH_INT_CAUSE_TX_DONE | ETH_INT_CAUSE_TX_ERROR)
307 #define ETH_INT_CAUSE_PHY 0x00010000
308 #define ETH_INT_CAUSE_STATE 0x00100000
309 #define ETH_INT_UNMASK_ALL_EXT (ETH_INT_CAUSE_TX | ETH_INT_CAUSE_PHY | \
310 ETH_INT_CAUSE_STATE)
312 #define ETH_INT_MASK_ALL 0x00000000
313 #define ETH_INT_MASK_ALL_EXT 0x00000000
315 #define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
316 #define PHY_WAIT_MICRO_SECONDS 10
318 /* Buffer offset from buffer pointer */
319 #define RX_BUF_OFFSET 0x2
321 /* Gigabit Ethernet Unit Global Registers */
323 /* MIB Counters register definitions */
324 #define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
325 #define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
326 #define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
327 #define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
328 #define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
329 #define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
330 #define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
331 #define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
332 #define ETH_MIB_FRAMES_64_OCTETS 0x20
333 #define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
334 #define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
335 #define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
336 #define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
337 #define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
338 #define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
339 #define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
340 #define ETH_MIB_GOOD_FRAMES_SENT 0x40
341 #define ETH_MIB_EXCESSIVE_COLLISION 0x44
342 #define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
343 #define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
344 #define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
345 #define ETH_MIB_FC_SENT 0x54
346 #define ETH_MIB_GOOD_FC_RECEIVED 0x58
347 #define ETH_MIB_BAD_FC_RECEIVED 0x5c
348 #define ETH_MIB_UNDERSIZE_RECEIVED 0x60
349 #define ETH_MIB_FRAGMENTS_RECEIVED 0x64
350 #define ETH_MIB_OVERSIZE_RECEIVED 0x68
351 #define ETH_MIB_JABBER_RECEIVED 0x6c
352 #define ETH_MIB_MAC_RECEIVE_ERROR 0x70
353 #define ETH_MIB_BAD_CRC_EVENT 0x74
354 #define ETH_MIB_COLLISION 0x78
355 #define ETH_MIB_LATE_COLLISION 0x7c
357 /* Port serial status reg (PSR) */
358 #define ETH_INTERFACE_PCM 0x00000001
359 #define ETH_LINK_IS_UP 0x00000002
360 #define ETH_PORT_AT_FULL_DUPLEX 0x00000004
361 #define ETH_RX_FLOW_CTRL_ENABLED 0x00000008
362 #define ETH_GMII_SPEED_1000 0x00000010
363 #define ETH_MII_SPEED_100 0x00000020
364 #define ETH_TX_IN_PROGRESS 0x00000080
365 #define ETH_BYPASS_ACTIVE 0x00000100
366 #define ETH_PORT_AT_PARTITION_STATE 0x00000200
367 #define ETH_PORT_TX_FIFO_EMPTY 0x00000400
369 /* SMI reg */
370 #define ETH_SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
371 #define ETH_SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
372 #define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read */
373 #define ETH_SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
375 /* Interrupt Cause Register Bit Definitions */
377 /* SDMA command status fields macros */
379 /* Tx & Rx descriptors status */
380 #define ETH_ERROR_SUMMARY 0x00000001
382 /* Tx & Rx descriptors command */
383 #define ETH_BUFFER_OWNED_BY_DMA 0x80000000
385 /* Tx descriptors status */
386 #define ETH_LC_ERROR 0
387 #define ETH_UR_ERROR 0x00000002
388 #define ETH_RL_ERROR 0x00000004
389 #define ETH_LLC_SNAP_FORMAT 0x00000200
391 /* Rx descriptors status */
392 #define ETH_OVERRUN_ERROR 0x00000002
393 #define ETH_MAX_FRAME_LENGTH_ERROR 0x00000004
394 #define ETH_RESOURCE_ERROR 0x00000006
395 #define ETH_VLAN_TAGGED 0x00080000
396 #define ETH_BPDU_FRAME 0x00100000
397 #define ETH_UDP_FRAME_OVER_IP_V_4 0x00200000
398 #define ETH_OTHER_FRAME_TYPE 0x00400000
399 #define ETH_LAYER_2_IS_ETH_V_2 0x00800000
400 #define ETH_FRAME_TYPE_IP_V_4 0x01000000
401 #define ETH_FRAME_HEADER_OK 0x02000000
402 #define ETH_RX_LAST_DESC 0x04000000
403 #define ETH_RX_FIRST_DESC 0x08000000
404 #define ETH_UNKNOWN_DESTINATION_ADDR 0x10000000
405 #define ETH_RX_ENABLE_INTERRUPT 0x20000000
406 #define ETH_LAYER_4_CHECKSUM_OK 0x40000000
408 /* Rx descriptors byte count */
409 #define ETH_FRAME_FRAGMENTED 0x00000004
411 /* Tx descriptors command */
412 #define ETH_LAYER_4_CHECKSUM_FIRST_DESC 0x00000400
413 #define ETH_FRAME_SET_TO_VLAN 0x00008000
414 #define ETH_UDP_FRAME 0x00010000
415 #define ETH_GEN_TCP_UDP_CHECKSUM 0x00020000
416 #define ETH_GEN_IP_V_4_CHECKSUM 0x00040000
417 #define ETH_ZERO_PADDING 0x00080000
418 #define ETH_TX_LAST_DESC 0x00100000
419 #define ETH_TX_FIRST_DESC 0x00200000
420 #define ETH_GEN_CRC 0x00400000
421 #define ETH_TX_ENABLE_INTERRUPT 0x00800000
422 #define ETH_AUTO_MODE 0x40000000
424 #define ETH_TX_IHL_SHIFT 11
426 /* typedefs */
428 typedef enum _eth_func_ret_status {
429 ETH_OK, /* Returned as expected. */
430 ETH_ERROR, /* Fundamental error. */
431 ETH_RETRY, /* Could not process request. Try later.*/
432 ETH_END_OF_JOB, /* Ring has nothing to process. */
433 ETH_QUEUE_FULL, /* Ring resource error. */
434 ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
435 } ETH_FUNC_RET_STATUS;
437 typedef enum _eth_target {
438 ETH_TARGET_DRAM,
439 ETH_TARGET_DEVICE,
440 ETH_TARGET_CBS,
441 ETH_TARGET_PCI0,
442 ETH_TARGET_PCI1
443 } ETH_TARGET;
445 /* These are for big-endian machines. Little endian needs different
446 * definitions.
448 #if defined(__BIG_ENDIAN)
449 struct eth_rx_desc {
450 u16 byte_cnt; /* Descriptor buffer byte count */
451 u16 buf_size; /* Buffer size */
452 u32 cmd_sts; /* Descriptor command status */
453 u32 next_desc_ptr; /* Next descriptor pointer */
454 u32 buf_ptr; /* Descriptor buffer pointer */
457 struct eth_tx_desc {
458 u16 byte_cnt; /* buffer byte count */
459 u16 l4i_chk; /* CPU provided TCP checksum */
460 u32 cmd_sts; /* Command/status field */
461 u32 next_desc_ptr; /* Pointer to next descriptor */
462 u32 buf_ptr; /* pointer to buffer for this descriptor*/
464 #elif defined(__LITTLE_ENDIAN)
465 struct eth_rx_desc {
466 u32 cmd_sts; /* Descriptor command status */
467 u16 buf_size; /* Buffer size */
468 u16 byte_cnt; /* Descriptor buffer byte count */
469 u32 buf_ptr; /* Descriptor buffer pointer */
470 u32 next_desc_ptr; /* Next descriptor pointer */
473 struct eth_tx_desc {
474 u32 cmd_sts; /* Command/status field */
475 u16 l4i_chk; /* CPU provided TCP checksum */
476 u16 byte_cnt; /* buffer byte count */
477 u32 buf_ptr; /* pointer to buffer for this descriptor*/
478 u32 next_desc_ptr; /* Pointer to next descriptor */
480 #else
481 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
482 #endif
484 /* Unified struct for Rx and Tx operations. The user is not required to */
485 /* be familier with neither Tx nor Rx descriptors. */
486 struct pkt_info {
487 unsigned short byte_cnt; /* Descriptor buffer byte count */
488 unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
489 unsigned int cmd_sts; /* Descriptor command status */
490 dma_addr_t buf_ptr; /* Descriptor buffer pointer */
491 struct sk_buff *return_info; /* User resource return information */
494 /* Ethernet port specific information */
495 struct mv643xx_mib_counters {
496 u64 good_octets_received;
497 u32 bad_octets_received;
498 u32 internal_mac_transmit_err;
499 u32 good_frames_received;
500 u32 bad_frames_received;
501 u32 broadcast_frames_received;
502 u32 multicast_frames_received;
503 u32 frames_64_octets;
504 u32 frames_65_to_127_octets;
505 u32 frames_128_to_255_octets;
506 u32 frames_256_to_511_octets;
507 u32 frames_512_to_1023_octets;
508 u32 frames_1024_to_max_octets;
509 u64 good_octets_sent;
510 u32 good_frames_sent;
511 u32 excessive_collision;
512 u32 multicast_frames_sent;
513 u32 broadcast_frames_sent;
514 u32 unrec_mac_control_received;
515 u32 fc_sent;
516 u32 good_fc_received;
517 u32 bad_fc_received;
518 u32 undersize_received;
519 u32 fragments_received;
520 u32 oversize_received;
521 u32 jabber_received;
522 u32 mac_receive_error;
523 u32 bad_crc_event;
524 u32 collision;
525 u32 late_collision;
528 struct mv643xx_private {
529 int port_num; /* User Ethernet port number */
531 u32 rx_sram_addr; /* Base address of rx sram area */
532 u32 rx_sram_size; /* Size of rx sram area */
533 u32 tx_sram_addr; /* Base address of tx sram area */
534 u32 tx_sram_size; /* Size of tx sram area */
536 int rx_resource_err; /* Rx ring resource error flag */
538 /* Tx/Rx rings managment indexes fields. For driver use */
540 /* Next available and first returning Rx resource */
541 int rx_curr_desc_q, rx_used_desc_q;
543 /* Next available and first returning Tx resource */
544 int tx_curr_desc_q, tx_used_desc_q;
546 #ifdef MV643XX_TX_FAST_REFILL
547 u32 tx_clean_threshold;
548 #endif
550 struct eth_rx_desc *p_rx_desc_area;
551 dma_addr_t rx_desc_dma;
552 int rx_desc_area_size;
553 struct sk_buff **rx_skb;
555 struct eth_tx_desc *p_tx_desc_area;
556 dma_addr_t tx_desc_dma;
557 int tx_desc_area_size;
558 struct sk_buff **tx_skb;
560 struct work_struct tx_timeout_task;
562 struct net_device *dev;
563 struct napi_struct napi;
564 struct net_device_stats stats;
565 struct mv643xx_mib_counters mib_counters;
566 spinlock_t lock;
567 /* Size of Tx Ring per queue */
568 int tx_ring_size;
569 /* Number of tx descriptors in use */
570 int tx_desc_count;
571 /* Size of Rx Ring per queue */
572 int rx_ring_size;
573 /* Number of rx descriptors in use */
574 int rx_desc_count;
577 * Used in case RX Ring is empty, which can be caused when
578 * system does not have resources (skb's)
580 struct timer_list timeout;
582 u32 rx_int_coal;
583 u32 tx_int_coal;
584 struct mii_if_info mii;
587 /* Static function declarations */
588 static void eth_port_init(struct mv643xx_private *mp);
589 static void eth_port_reset(unsigned int eth_port_num);
590 static void eth_port_start(struct net_device *dev);
592 static void ethernet_phy_reset(unsigned int eth_port_num);
594 static void eth_port_write_smi_reg(unsigned int eth_port_num,
595 unsigned int phy_reg, unsigned int value);
597 static void eth_port_read_smi_reg(unsigned int eth_port_num,
598 unsigned int phy_reg, unsigned int *value);
600 static void eth_clear_mib_counters(unsigned int eth_port_num);
602 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
603 struct pkt_info *p_pkt_info);
604 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
605 struct pkt_info *p_pkt_info);
607 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr);
608 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr);
609 static void eth_port_set_multicast_list(struct net_device *);
610 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
611 unsigned int queues);
612 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
613 unsigned int queues);
614 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num);
615 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num);
616 static int mv643xx_eth_open(struct net_device *);
617 static int mv643xx_eth_stop(struct net_device *);
618 static int mv643xx_eth_change_mtu(struct net_device *, int);
619 static void eth_port_init_mac_tables(unsigned int eth_port_num);
620 #ifdef MV643XX_NAPI
621 static int mv643xx_poll(struct napi_struct *napi, int budget);
622 #endif
623 static int ethernet_phy_get(unsigned int eth_port_num);
624 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
625 static int ethernet_phy_detect(unsigned int eth_port_num);
626 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location);
627 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val);
628 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
629 static const struct ethtool_ops mv643xx_ethtool_ops;
631 static char mv643xx_driver_name[] = "mv643xx_eth";
632 static char mv643xx_driver_version[] = "1.0";
634 static void __iomem *mv643xx_eth_base;
636 /* used to protect SMI_REG, which is shared across ports */
637 static DEFINE_SPINLOCK(mv643xx_eth_phy_lock);
639 static inline u32 mv_read(int offset)
641 return readl(mv643xx_eth_base + offset);
644 static inline void mv_write(int offset, u32 data)
646 writel(data, mv643xx_eth_base + offset);
650 * Changes MTU (maximum transfer unit) of the gigabit ethenret port
652 * Input : pointer to ethernet interface network device structure
653 * new mtu size
654 * Output : 0 upon success, -EINVAL upon failure
656 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
658 if ((new_mtu > 9500) || (new_mtu < 64))
659 return -EINVAL;
661 dev->mtu = new_mtu;
663 * Stop then re-open the interface. This will allocate RX skb's with
664 * the new MTU.
665 * There is a possible danger that the open will not successed, due
666 * to memory is full, which might fail the open function.
668 if (netif_running(dev)) {
669 mv643xx_eth_stop(dev);
670 if (mv643xx_eth_open(dev))
671 printk(KERN_ERR
672 "%s: Fatal error on opening device\n",
673 dev->name);
676 return 0;
680 * mv643xx_eth_rx_refill_descs
682 * Fills / refills RX queue on a certain gigabit ethernet port
684 * Input : pointer to ethernet interface network device structure
685 * Output : N/A
687 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
689 struct mv643xx_private *mp = netdev_priv(dev);
690 struct pkt_info pkt_info;
691 struct sk_buff *skb;
692 int unaligned;
694 while (mp->rx_desc_count < mp->rx_ring_size) {
695 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
696 if (!skb)
697 break;
698 mp->rx_desc_count++;
699 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
700 if (unaligned)
701 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
702 pkt_info.cmd_sts = ETH_RX_ENABLE_INTERRUPT;
703 pkt_info.byte_cnt = ETH_RX_SKB_SIZE;
704 pkt_info.buf_ptr = dma_map_single(NULL, skb->data,
705 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
706 pkt_info.return_info = skb;
707 if (eth_rx_return_buff(mp, &pkt_info) != ETH_OK) {
708 printk(KERN_ERR
709 "%s: Error allocating RX Ring\n", dev->name);
710 break;
712 skb_reserve(skb, ETH_HW_IP_ALIGN);
715 * If RX ring is empty of SKB, set a timer to try allocating
716 * again at a later time.
718 if (mp->rx_desc_count == 0) {
719 printk(KERN_INFO "%s: Rx ring is empty\n", dev->name);
720 mp->timeout.expires = jiffies + (HZ / 10); /* 100 mSec */
721 add_timer(&mp->timeout);
726 * mv643xx_eth_rx_refill_descs_timer_wrapper
728 * Timer routine to wake up RX queue filling task. This function is
729 * used only in case the RX queue is empty, and all alloc_skb has
730 * failed (due to out of memory event).
732 * Input : pointer to ethernet interface network device structure
733 * Output : N/A
735 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
737 mv643xx_eth_rx_refill_descs((struct net_device *)data);
741 * mv643xx_eth_update_mac_address
743 * Update the MAC address of the port in the address table
745 * Input : pointer to ethernet interface network device structure
746 * Output : N/A
748 static void mv643xx_eth_update_mac_address(struct net_device *dev)
750 struct mv643xx_private *mp = netdev_priv(dev);
751 unsigned int port_num = mp->port_num;
753 eth_port_init_mac_tables(port_num);
754 eth_port_uc_addr_set(port_num, dev->dev_addr);
758 * mv643xx_eth_set_rx_mode
760 * Change from promiscuos to regular rx mode
762 * Input : pointer to ethernet interface network device structure
763 * Output : N/A
765 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
767 struct mv643xx_private *mp = netdev_priv(dev);
768 u32 config_reg;
770 config_reg = mv_read(PORT_CONFIG_REG(mp->port_num));
771 if (dev->flags & IFF_PROMISC)
772 config_reg |= (u32) UNICAST_PROMISCUOUS_MODE;
773 else
774 config_reg &= ~(u32) UNICAST_PROMISCUOUS_MODE;
775 mv_write(PORT_CONFIG_REG(mp->port_num), config_reg);
777 eth_port_set_multicast_list(dev);
781 * mv643xx_eth_set_mac_address
783 * Change the interface's mac address.
784 * No special hardware thing should be done because interface is always
785 * put in promiscuous mode.
787 * Input : pointer to ethernet interface network device structure and
788 * a pointer to the designated entry to be added to the cache.
789 * Output : zero upon success, negative upon failure
791 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
793 int i;
795 for (i = 0; i < 6; i++)
796 /* +2 is for the offset of the HW addr type */
797 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
798 mv643xx_eth_update_mac_address(dev);
799 return 0;
803 * mv643xx_eth_tx_timeout
805 * Called upon a timeout on transmitting a packet
807 * Input : pointer to ethernet interface network device structure.
808 * Output : N/A
810 static void mv643xx_eth_tx_timeout(struct net_device *dev)
812 struct mv643xx_private *mp = netdev_priv(dev);
814 printk(KERN_INFO "%s: TX timeout ", dev->name);
816 /* Do the reset outside of interrupt context */
817 schedule_work(&mp->tx_timeout_task);
821 * mv643xx_eth_tx_timeout_task
823 * Actual routine to reset the adapter when a timeout on Tx has occurred
825 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
827 struct mv643xx_private *mp = container_of(ugly, struct mv643xx_private,
828 tx_timeout_task);
829 struct net_device *dev = mp->mii.dev; /* yuck */
831 if (!netif_running(dev))
832 return;
834 netif_stop_queue(dev);
836 eth_port_reset(mp->port_num);
837 eth_port_start(dev);
839 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
840 netif_wake_queue(dev);
844 * mv643xx_eth_free_tx_descs - Free the tx desc data for completed descriptors
846 * If force is non-zero, frees uncompleted descriptors as well
848 int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
850 struct mv643xx_private *mp = netdev_priv(dev);
851 struct eth_tx_desc *desc;
852 u32 cmd_sts;
853 struct sk_buff *skb;
854 unsigned long flags;
855 int tx_index;
856 dma_addr_t addr;
857 int count;
858 int released = 0;
860 while (mp->tx_desc_count > 0) {
861 spin_lock_irqsave(&mp->lock, flags);
863 /* tx_desc_count might have changed before acquiring the lock */
864 if (mp->tx_desc_count <= 0) {
865 spin_unlock_irqrestore(&mp->lock, flags);
866 return released;
869 tx_index = mp->tx_used_desc_q;
870 desc = &mp->p_tx_desc_area[tx_index];
871 cmd_sts = desc->cmd_sts;
873 if (!force && (cmd_sts & ETH_BUFFER_OWNED_BY_DMA)) {
874 spin_unlock_irqrestore(&mp->lock, flags);
875 return released;
878 mp->tx_used_desc_q = (tx_index + 1) % mp->tx_ring_size;
879 mp->tx_desc_count--;
881 addr = desc->buf_ptr;
882 count = desc->byte_cnt;
883 skb = mp->tx_skb[tx_index];
884 if (skb)
885 mp->tx_skb[tx_index] = NULL;
887 if (cmd_sts & ETH_ERROR_SUMMARY) {
888 printk("%s: Error in TX\n", dev->name);
889 dev->stats.tx_errors++;
892 spin_unlock_irqrestore(&mp->lock, flags);
894 if (cmd_sts & ETH_TX_FIRST_DESC)
895 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
896 else
897 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
899 if (skb)
900 dev_kfree_skb_irq(skb);
902 released = 1;
905 return released;
908 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
910 struct mv643xx_private *mp = netdev_priv(dev);
912 if (mv643xx_eth_free_tx_descs(dev, 0) &&
913 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
914 netif_wake_queue(dev);
917 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
919 mv643xx_eth_free_tx_descs(dev, 1);
923 * mv643xx_eth_receive
925 * This function is forward packets that are received from the port's
926 * queues toward kernel core or FastRoute them to another interface.
928 * Input : dev - a pointer to the required interface
929 * max - maximum number to receive (0 means unlimted)
931 * Output : number of served packets
933 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
935 struct mv643xx_private *mp = netdev_priv(dev);
936 struct net_device_stats *stats = &dev->stats;
937 unsigned int received_packets = 0;
938 struct sk_buff *skb;
939 struct pkt_info pkt_info;
941 while (budget-- > 0 && eth_port_receive(mp, &pkt_info) == ETH_OK) {
942 dma_unmap_single(NULL, pkt_info.buf_ptr, ETH_RX_SKB_SIZE,
943 DMA_FROM_DEVICE);
944 mp->rx_desc_count--;
945 received_packets++;
948 * Update statistics.
949 * Note byte count includes 4 byte CRC count
951 stats->rx_packets++;
952 stats->rx_bytes += pkt_info.byte_cnt;
953 skb = pkt_info.return_info;
955 * In case received a packet without first / last bits on OR
956 * the error summary bit is on, the packets needs to be dropeed.
958 if (((pkt_info.cmd_sts
959 & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) !=
960 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC))
961 || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) {
962 stats->rx_dropped++;
963 if ((pkt_info.cmd_sts & (ETH_RX_FIRST_DESC |
964 ETH_RX_LAST_DESC)) !=
965 (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) {
966 if (net_ratelimit())
967 printk(KERN_ERR
968 "%s: Received packet spread "
969 "on multiple descriptors\n",
970 dev->name);
972 if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)
973 stats->rx_errors++;
975 dev_kfree_skb_irq(skb);
976 } else {
978 * The -4 is for the CRC in the trailer of the
979 * received packet
981 skb_put(skb, pkt_info.byte_cnt - 4);
983 if (pkt_info.cmd_sts & ETH_LAYER_4_CHECKSUM_OK) {
984 skb->ip_summed = CHECKSUM_UNNECESSARY;
985 skb->csum = htons(
986 (pkt_info.cmd_sts & 0x0007fff8) >> 3);
988 skb->protocol = eth_type_trans(skb, dev);
989 #ifdef MV643XX_NAPI
990 netif_receive_skb(skb);
991 #else
992 netif_rx(skb);
993 #endif
995 dev->last_rx = jiffies;
997 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
999 return received_packets;
1002 /* Set the mv643xx port configuration register for the speed/duplex mode. */
1003 static void mv643xx_eth_update_pscr(struct net_device *dev,
1004 struct ethtool_cmd *ecmd)
1006 struct mv643xx_private *mp = netdev_priv(dev);
1007 int port_num = mp->port_num;
1008 u32 o_pscr, n_pscr;
1009 unsigned int queues;
1011 o_pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
1012 n_pscr = o_pscr;
1014 /* clear speed, duplex and rx buffer size fields */
1015 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1016 SET_GMII_SPEED_TO_1000 |
1017 SET_FULL_DUPLEX_MODE |
1018 MAX_RX_PACKET_MASK);
1020 if (ecmd->duplex == DUPLEX_FULL)
1021 n_pscr |= SET_FULL_DUPLEX_MODE;
1023 if (ecmd->speed == SPEED_1000)
1024 n_pscr |= SET_GMII_SPEED_TO_1000 |
1025 MAX_RX_PACKET_9700BYTE;
1026 else {
1027 if (ecmd->speed == SPEED_100)
1028 n_pscr |= SET_MII_SPEED_TO_100;
1029 n_pscr |= MAX_RX_PACKET_1522BYTE;
1032 if (n_pscr != o_pscr) {
1033 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1034 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1035 else {
1036 queues = mv643xx_eth_port_disable_tx(port_num);
1038 o_pscr &= ~SERIAL_PORT_ENABLE;
1039 mv_write(PORT_SERIAL_CONTROL_REG(port_num), o_pscr);
1040 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1041 mv_write(PORT_SERIAL_CONTROL_REG(port_num), n_pscr);
1042 if (queues)
1043 mv643xx_eth_port_enable_tx(port_num, queues);
1049 * mv643xx_eth_int_handler
1051 * Main interrupt handler for the gigbit ethernet ports
1053 * Input : irq - irq number (not used)
1054 * dev_id - a pointer to the required interface's data structure
1055 * regs - not used
1056 * Output : N/A
1059 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1061 struct net_device *dev = (struct net_device *)dev_id;
1062 struct mv643xx_private *mp = netdev_priv(dev);
1063 u32 eth_int_cause, eth_int_cause_ext = 0;
1064 unsigned int port_num = mp->port_num;
1066 /* Read interrupt cause registers */
1067 eth_int_cause = mv_read(INTERRUPT_CAUSE_REG(port_num)) &
1068 ETH_INT_UNMASK_ALL;
1069 if (eth_int_cause & ETH_INT_CAUSE_EXT) {
1070 eth_int_cause_ext = mv_read(
1071 INTERRUPT_CAUSE_EXTEND_REG(port_num)) &
1072 ETH_INT_UNMASK_ALL_EXT;
1073 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num),
1074 ~eth_int_cause_ext);
1077 /* PHY status changed */
1078 if (eth_int_cause_ext & (ETH_INT_CAUSE_PHY | ETH_INT_CAUSE_STATE)) {
1079 struct ethtool_cmd cmd;
1081 if (mii_link_ok(&mp->mii)) {
1082 mii_ethtool_gset(&mp->mii, &cmd);
1083 mv643xx_eth_update_pscr(dev, &cmd);
1084 mv643xx_eth_port_enable_tx(port_num,
1085 ETH_TX_QUEUES_ENABLED);
1086 if (!netif_carrier_ok(dev)) {
1087 netif_carrier_on(dev);
1088 if (mp->tx_ring_size - mp->tx_desc_count >=
1089 MAX_DESCS_PER_SKB)
1090 netif_wake_queue(dev);
1092 } else if (netif_carrier_ok(dev)) {
1093 netif_stop_queue(dev);
1094 netif_carrier_off(dev);
1098 #ifdef MV643XX_NAPI
1099 if (eth_int_cause & ETH_INT_CAUSE_RX) {
1100 /* schedule the NAPI poll routine to maintain port */
1101 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1103 /* wait for previous write to complete */
1104 mv_read(INTERRUPT_MASK_REG(port_num));
1106 netif_rx_schedule(dev, &mp->napi);
1108 #else
1109 if (eth_int_cause & ETH_INT_CAUSE_RX)
1110 mv643xx_eth_receive_queue(dev, INT_MAX);
1111 #endif
1112 if (eth_int_cause_ext & ETH_INT_CAUSE_TX)
1113 mv643xx_eth_free_completed_tx_descs(dev);
1116 * If no real interrupt occured, exit.
1117 * This can happen when using gigE interrupt coalescing mechanism.
1119 if ((eth_int_cause == 0x0) && (eth_int_cause_ext == 0x0))
1120 return IRQ_NONE;
1122 return IRQ_HANDLED;
1125 #ifdef MV643XX_COAL
1128 * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path
1130 * DESCRIPTION:
1131 * This routine sets the RX coalescing interrupt mechanism parameter.
1132 * This parameter is a timeout counter, that counts in 64 t_clk
1133 * chunks ; that when timeout event occurs a maskable interrupt
1134 * occurs.
1135 * The parameter is calculated using the tClk of the MV-643xx chip
1136 * , and the required delay of the interrupt in usec.
1138 * INPUT:
1139 * unsigned int eth_port_num Ethernet port number
1140 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1141 * unsigned int delay Delay in usec
1143 * OUTPUT:
1144 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1146 * RETURN:
1147 * The interrupt coalescing value set in the gigE port.
1150 static unsigned int eth_port_set_rx_coal(unsigned int eth_port_num,
1151 unsigned int t_clk, unsigned int delay)
1153 unsigned int coal = ((t_clk / 1000000) * delay) / 64;
1155 /* Set RX Coalescing mechanism */
1156 mv_write(SDMA_CONFIG_REG(eth_port_num),
1157 ((coal & 0x3fff) << 8) |
1158 (mv_read(SDMA_CONFIG_REG(eth_port_num))
1159 & 0xffc000ff));
1161 return coal;
1163 #endif
1166 * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path
1168 * DESCRIPTION:
1169 * This routine sets the TX coalescing interrupt mechanism parameter.
1170 * This parameter is a timeout counter, that counts in 64 t_clk
1171 * chunks ; that when timeout event occurs a maskable interrupt
1172 * occurs.
1173 * The parameter is calculated using the t_cLK frequency of the
1174 * MV-643xx chip and the required delay in the interrupt in uSec
1176 * INPUT:
1177 * unsigned int eth_port_num Ethernet port number
1178 * unsigned int t_clk t_clk of the MV-643xx chip in HZ units
1179 * unsigned int delay Delay in uSeconds
1181 * OUTPUT:
1182 * Interrupt coalescing mechanism value is set in MV-643xx chip.
1184 * RETURN:
1185 * The interrupt coalescing value set in the gigE port.
1188 static unsigned int eth_port_set_tx_coal(unsigned int eth_port_num,
1189 unsigned int t_clk, unsigned int delay)
1191 unsigned int coal;
1192 coal = ((t_clk / 1000000) * delay) / 64;
1193 /* Set TX Coalescing mechanism */
1194 mv_write(TX_FIFO_URGENT_THRESHOLD_REG(eth_port_num), coal << 4);
1195 return coal;
1199 * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
1201 * DESCRIPTION:
1202 * This function prepares a Rx chained list of descriptors and packet
1203 * buffers in a form of a ring. The routine must be called after port
1204 * initialization routine and before port start routine.
1205 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1206 * devices in the system (i.e. DRAM). This function uses the ethernet
1207 * struct 'virtual to physical' routine (set by the user) to set the ring
1208 * with physical addresses.
1210 * INPUT:
1211 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1213 * OUTPUT:
1214 * The routine updates the Ethernet port control struct with information
1215 * regarding the Rx descriptors and buffers.
1217 * RETURN:
1218 * None.
1220 static void ether_init_rx_desc_ring(struct mv643xx_private *mp)
1222 volatile struct eth_rx_desc *p_rx_desc;
1223 int rx_desc_num = mp->rx_ring_size;
1224 int i;
1226 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1227 p_rx_desc = (struct eth_rx_desc *)mp->p_rx_desc_area;
1228 for (i = 0; i < rx_desc_num; i++) {
1229 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1230 ((i + 1) % rx_desc_num) * sizeof(struct eth_rx_desc);
1233 /* Save Rx desc pointer to driver struct. */
1234 mp->rx_curr_desc_q = 0;
1235 mp->rx_used_desc_q = 0;
1237 mp->rx_desc_area_size = rx_desc_num * sizeof(struct eth_rx_desc);
1241 * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory.
1243 * DESCRIPTION:
1244 * This function prepares a Tx chained list of descriptors and packet
1245 * buffers in a form of a ring. The routine must be called after port
1246 * initialization routine and before port start routine.
1247 * The Ethernet SDMA engine uses CPU bus addresses to access the various
1248 * devices in the system (i.e. DRAM). This function uses the ethernet
1249 * struct 'virtual to physical' routine (set by the user) to set the ring
1250 * with physical addresses.
1252 * INPUT:
1253 * struct mv643xx_private *mp Ethernet Port Control srtuct.
1255 * OUTPUT:
1256 * The routine updates the Ethernet port control struct with information
1257 * regarding the Tx descriptors and buffers.
1259 * RETURN:
1260 * None.
1262 static void ether_init_tx_desc_ring(struct mv643xx_private *mp)
1264 int tx_desc_num = mp->tx_ring_size;
1265 struct eth_tx_desc *p_tx_desc;
1266 int i;
1268 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1269 p_tx_desc = (struct eth_tx_desc *)mp->p_tx_desc_area;
1270 for (i = 0; i < tx_desc_num; i++) {
1271 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1272 ((i + 1) % tx_desc_num) * sizeof(struct eth_tx_desc);
1275 mp->tx_curr_desc_q = 0;
1276 mp->tx_used_desc_q = 0;
1278 mp->tx_desc_area_size = tx_desc_num * sizeof(struct eth_tx_desc);
1281 static int mv643xx_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1283 struct mv643xx_private *mp = netdev_priv(dev);
1284 int err;
1286 spin_lock_irq(&mp->lock);
1287 err = mii_ethtool_sset(&mp->mii, cmd);
1288 spin_unlock_irq(&mp->lock);
1290 return err;
1293 static int mv643xx_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1295 struct mv643xx_private *mp = netdev_priv(dev);
1296 int err;
1298 spin_lock_irq(&mp->lock);
1299 err = mii_ethtool_gset(&mp->mii, cmd);
1300 spin_unlock_irq(&mp->lock);
1302 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
1303 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1304 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1306 return err;
1310 * mv643xx_eth_open
1312 * This function is called when openning the network device. The function
1313 * should initialize all the hardware, initialize cyclic Rx/Tx
1314 * descriptors chain and buffers and allocate an IRQ to the network
1315 * device.
1317 * Input : a pointer to the network device structure
1319 * Output : zero of success , nonzero if fails.
1322 static int mv643xx_eth_open(struct net_device *dev)
1324 struct mv643xx_private *mp = netdev_priv(dev);
1325 unsigned int port_num = mp->port_num;
1326 unsigned int size;
1327 int err;
1329 /* Clear any pending ethernet port interrupts */
1330 mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
1331 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1332 /* wait for previous write to complete */
1333 mv_read (INTERRUPT_CAUSE_EXTEND_REG(port_num));
1335 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1336 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1337 if (err) {
1338 printk(KERN_ERR "Can not assign IRQ number to MV643XX_eth%d\n",
1339 port_num);
1340 return -EAGAIN;
1343 eth_port_init(mp);
1345 memset(&mp->timeout, 0, sizeof(struct timer_list));
1346 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1347 mp->timeout.data = (unsigned long)dev;
1349 /* Allocate RX and TX skb rings */
1350 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
1351 GFP_KERNEL);
1352 if (!mp->rx_skb) {
1353 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1354 err = -ENOMEM;
1355 goto out_free_irq;
1357 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1358 GFP_KERNEL);
1359 if (!mp->tx_skb) {
1360 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1361 err = -ENOMEM;
1362 goto out_free_rx_skb;
1365 /* Allocate TX ring */
1366 mp->tx_desc_count = 0;
1367 size = mp->tx_ring_size * sizeof(struct eth_tx_desc);
1368 mp->tx_desc_area_size = size;
1370 if (mp->tx_sram_size) {
1371 mp->p_tx_desc_area = ioremap(mp->tx_sram_addr,
1372 mp->tx_sram_size);
1373 mp->tx_desc_dma = mp->tx_sram_addr;
1374 } else
1375 mp->p_tx_desc_area = dma_alloc_coherent(NULL, size,
1376 &mp->tx_desc_dma,
1377 GFP_KERNEL);
1379 if (!mp->p_tx_desc_area) {
1380 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1381 dev->name, size);
1382 err = -ENOMEM;
1383 goto out_free_tx_skb;
1385 BUG_ON((u32) mp->p_tx_desc_area & 0xf); /* check 16-byte alignment */
1386 memset((void *)mp->p_tx_desc_area, 0, mp->tx_desc_area_size);
1388 ether_init_tx_desc_ring(mp);
1390 /* Allocate RX ring */
1391 mp->rx_desc_count = 0;
1392 size = mp->rx_ring_size * sizeof(struct eth_rx_desc);
1393 mp->rx_desc_area_size = size;
1395 if (mp->rx_sram_size) {
1396 mp->p_rx_desc_area = ioremap(mp->rx_sram_addr,
1397 mp->rx_sram_size);
1398 mp->rx_desc_dma = mp->rx_sram_addr;
1399 } else
1400 mp->p_rx_desc_area = dma_alloc_coherent(NULL, size,
1401 &mp->rx_desc_dma,
1402 GFP_KERNEL);
1404 if (!mp->p_rx_desc_area) {
1405 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
1406 dev->name, size);
1407 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1408 dev->name);
1409 if (mp->rx_sram_size)
1410 iounmap(mp->p_tx_desc_area);
1411 else
1412 dma_free_coherent(NULL, mp->tx_desc_area_size,
1413 mp->p_tx_desc_area, mp->tx_desc_dma);
1414 err = -ENOMEM;
1415 goto out_free_tx_skb;
1417 memset((void *)mp->p_rx_desc_area, 0, size);
1419 ether_init_rx_desc_ring(mp);
1421 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1423 #ifdef MV643XX_NAPI
1424 napi_enable(&mp->napi);
1425 #endif
1427 eth_port_start(dev);
1429 /* Interrupt Coalescing */
1431 #ifdef MV643XX_COAL
1432 mp->rx_int_coal =
1433 eth_port_set_rx_coal(port_num, 133000000, MV643XX_RX_COAL);
1434 #endif
1436 mp->tx_int_coal =
1437 eth_port_set_tx_coal(port_num, 133000000, MV643XX_TX_COAL);
1439 /* Unmask phy and link status changes interrupts */
1440 mv_write(INTERRUPT_EXTEND_MASK_REG(port_num), ETH_INT_UNMASK_ALL_EXT);
1442 /* Unmask RX buffer and TX end interrupt */
1443 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1445 return 0;
1447 out_free_tx_skb:
1448 kfree(mp->tx_skb);
1449 out_free_rx_skb:
1450 kfree(mp->rx_skb);
1451 out_free_irq:
1452 free_irq(dev->irq, dev);
1454 return err;
1457 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1459 struct mv643xx_private *mp = netdev_priv(dev);
1461 /* Stop Tx Queues */
1462 mv643xx_eth_port_disable_tx(mp->port_num);
1464 /* Free outstanding skb's on TX ring */
1465 mv643xx_eth_free_all_tx_descs(dev);
1467 BUG_ON(mp->tx_used_desc_q != mp->tx_curr_desc_q);
1469 /* Free TX ring */
1470 if (mp->tx_sram_size)
1471 iounmap(mp->p_tx_desc_area);
1472 else
1473 dma_free_coherent(NULL, mp->tx_desc_area_size,
1474 mp->p_tx_desc_area, mp->tx_desc_dma);
1477 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1479 struct mv643xx_private *mp = netdev_priv(dev);
1480 unsigned int port_num = mp->port_num;
1481 int curr;
1483 /* Stop RX Queues */
1484 mv643xx_eth_port_disable_rx(port_num);
1486 /* Free preallocated skb's on RX rings */
1487 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1488 if (mp->rx_skb[curr]) {
1489 dev_kfree_skb(mp->rx_skb[curr]);
1490 mp->rx_desc_count--;
1494 if (mp->rx_desc_count)
1495 printk(KERN_ERR
1496 "%s: Error in freeing Rx Ring. %d skb's still"
1497 " stuck in RX Ring - ignoring them\n", dev->name,
1498 mp->rx_desc_count);
1499 /* Free RX ring */
1500 if (mp->rx_sram_size)
1501 iounmap(mp->p_rx_desc_area);
1502 else
1503 dma_free_coherent(NULL, mp->rx_desc_area_size,
1504 mp->p_rx_desc_area, mp->rx_desc_dma);
1508 * mv643xx_eth_stop
1510 * This function is used when closing the network device.
1511 * It updates the hardware,
1512 * release all memory that holds buffers and descriptors and release the IRQ.
1513 * Input : a pointer to the device structure
1514 * Output : zero if success , nonzero if fails
1517 static int mv643xx_eth_stop(struct net_device *dev)
1519 struct mv643xx_private *mp = netdev_priv(dev);
1520 unsigned int port_num = mp->port_num;
1522 /* Mask all interrupts on ethernet port */
1523 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1524 /* wait for previous write to complete */
1525 mv_read(INTERRUPT_MASK_REG(port_num));
1527 #ifdef MV643XX_NAPI
1528 napi_disable(&mp->napi);
1529 #endif
1530 netif_carrier_off(dev);
1531 netif_stop_queue(dev);
1533 eth_port_reset(mp->port_num);
1535 mv643xx_eth_free_tx_rings(dev);
1536 mv643xx_eth_free_rx_rings(dev);
1538 free_irq(dev->irq, dev);
1540 return 0;
1543 #ifdef MV643XX_NAPI
1545 * mv643xx_poll
1547 * This function is used in case of NAPI
1549 static int mv643xx_poll(struct napi_struct *napi, int budget)
1551 struct mv643xx_private *mp = container_of(napi, struct mv643xx_private, napi);
1552 struct net_device *dev = mp->dev;
1553 unsigned int port_num = mp->port_num;
1554 int work_done;
1556 #ifdef MV643XX_TX_FAST_REFILL
1557 if (++mp->tx_clean_threshold > 5) {
1558 mv643xx_eth_free_completed_tx_descs(dev);
1559 mp->tx_clean_threshold = 0;
1561 #endif
1563 work_done = 0;
1564 if ((mv_read(RX_CURRENT_QUEUE_DESC_PTR_0(port_num)))
1565 != (u32) mp->rx_used_desc_q)
1566 work_done = mv643xx_eth_receive_queue(dev, budget);
1568 if (work_done < budget) {
1569 netif_rx_complete(dev, napi);
1570 mv_write(INTERRUPT_CAUSE_REG(port_num), 0);
1571 mv_write(INTERRUPT_CAUSE_EXTEND_REG(port_num), 0);
1572 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1575 return work_done;
1577 #endif
1580 * has_tiny_unaligned_frags - check if skb has any small, unaligned fragments
1582 * Hardware can't handle unaligned fragments smaller than 9 bytes.
1583 * This helper function detects that case.
1586 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
1588 unsigned int frag;
1589 skb_frag_t *fragp;
1591 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1592 fragp = &skb_shinfo(skb)->frags[frag];
1593 if (fragp->size <= 8 && fragp->page_offset & 0x7)
1594 return 1;
1596 return 0;
1600 * eth_alloc_tx_desc_index - return the index of the next available tx desc
1602 static int eth_alloc_tx_desc_index(struct mv643xx_private *mp)
1604 int tx_desc_curr;
1606 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
1608 tx_desc_curr = mp->tx_curr_desc_q;
1609 mp->tx_curr_desc_q = (tx_desc_curr + 1) % mp->tx_ring_size;
1611 BUG_ON(mp->tx_curr_desc_q == mp->tx_used_desc_q);
1613 return tx_desc_curr;
1617 * eth_tx_fill_frag_descs - fill tx hw descriptors for an skb's fragments.
1619 * Ensure the data for each fragment to be transmitted is mapped properly,
1620 * then fill in descriptors in the tx hw queue.
1622 static void eth_tx_fill_frag_descs(struct mv643xx_private *mp,
1623 struct sk_buff *skb)
1625 int frag;
1626 int tx_index;
1627 struct eth_tx_desc *desc;
1629 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1630 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1632 tx_index = eth_alloc_tx_desc_index(mp);
1633 desc = &mp->p_tx_desc_area[tx_index];
1635 desc->cmd_sts = ETH_BUFFER_OWNED_BY_DMA;
1636 /* Last Frag enables interrupt and frees the skb */
1637 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
1638 desc->cmd_sts |= ETH_ZERO_PADDING |
1639 ETH_TX_LAST_DESC |
1640 ETH_TX_ENABLE_INTERRUPT;
1641 mp->tx_skb[tx_index] = skb;
1642 } else
1643 mp->tx_skb[tx_index] = NULL;
1645 desc = &mp->p_tx_desc_area[tx_index];
1646 desc->l4i_chk = 0;
1647 desc->byte_cnt = this_frag->size;
1648 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
1649 this_frag->page_offset,
1650 this_frag->size,
1651 DMA_TO_DEVICE);
1655 static inline __be16 sum16_as_be(__sum16 sum)
1657 return (__force __be16)sum;
1661 * eth_tx_submit_descs_for_skb - submit data from an skb to the tx hw
1663 * Ensure the data for an skb to be transmitted is mapped properly,
1664 * then fill in descriptors in the tx hw queue and start the hardware.
1666 static void eth_tx_submit_descs_for_skb(struct mv643xx_private *mp,
1667 struct sk_buff *skb)
1669 int tx_index;
1670 struct eth_tx_desc *desc;
1671 u32 cmd_sts;
1672 int length;
1673 int nr_frags = skb_shinfo(skb)->nr_frags;
1675 cmd_sts = ETH_TX_FIRST_DESC | ETH_GEN_CRC | ETH_BUFFER_OWNED_BY_DMA;
1677 tx_index = eth_alloc_tx_desc_index(mp);
1678 desc = &mp->p_tx_desc_area[tx_index];
1680 if (nr_frags) {
1681 eth_tx_fill_frag_descs(mp, skb);
1683 length = skb_headlen(skb);
1684 mp->tx_skb[tx_index] = NULL;
1685 } else {
1686 cmd_sts |= ETH_ZERO_PADDING |
1687 ETH_TX_LAST_DESC |
1688 ETH_TX_ENABLE_INTERRUPT;
1689 length = skb->len;
1690 mp->tx_skb[tx_index] = skb;
1693 desc->byte_cnt = length;
1694 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
1696 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1697 BUG_ON(skb->protocol != htons(ETH_P_IP));
1699 cmd_sts |= ETH_GEN_TCP_UDP_CHECKSUM |
1700 ETH_GEN_IP_V_4_CHECKSUM |
1701 ip_hdr(skb)->ihl << ETH_TX_IHL_SHIFT;
1703 switch (ip_hdr(skb)->protocol) {
1704 case IPPROTO_UDP:
1705 cmd_sts |= ETH_UDP_FRAME;
1706 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
1707 break;
1708 case IPPROTO_TCP:
1709 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
1710 break;
1711 default:
1712 BUG();
1714 } else {
1715 /* Errata BTS #50, IHL must be 5 if no HW checksum */
1716 cmd_sts |= 5 << ETH_TX_IHL_SHIFT;
1717 desc->l4i_chk = 0;
1720 /* ensure all other descriptors are written before first cmd_sts */
1721 wmb();
1722 desc->cmd_sts = cmd_sts;
1724 /* ensure all descriptors are written before poking hardware */
1725 wmb();
1726 mv643xx_eth_port_enable_tx(mp->port_num, ETH_TX_QUEUES_ENABLED);
1728 mp->tx_desc_count += nr_frags + 1;
1732 * mv643xx_eth_start_xmit - queue an skb to the hardware for transmission
1735 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
1737 struct mv643xx_private *mp = netdev_priv(dev);
1738 struct net_device_stats *stats = &dev->stats;
1739 unsigned long flags;
1741 BUG_ON(netif_queue_stopped(dev));
1742 BUG_ON(skb == NULL);
1744 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
1745 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
1746 netif_stop_queue(dev);
1747 return 1;
1750 if (has_tiny_unaligned_frags(skb)) {
1751 if (__skb_linearize(skb)) {
1752 stats->tx_dropped++;
1753 printk(KERN_DEBUG "%s: failed to linearize tiny "
1754 "unaligned fragment\n", dev->name);
1755 return 1;
1759 spin_lock_irqsave(&mp->lock, flags);
1761 eth_tx_submit_descs_for_skb(mp, skb);
1762 stats->tx_bytes += skb->len;
1763 stats->tx_packets++;
1764 dev->trans_start = jiffies;
1766 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
1767 netif_stop_queue(dev);
1769 spin_unlock_irqrestore(&mp->lock, flags);
1771 return 0; /* success */
1774 #ifdef CONFIG_NET_POLL_CONTROLLER
1775 static void mv643xx_netpoll(struct net_device *netdev)
1777 struct mv643xx_private *mp = netdev_priv(netdev);
1778 int port_num = mp->port_num;
1780 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_MASK_ALL);
1781 /* wait for previous write to complete */
1782 mv_read(INTERRUPT_MASK_REG(port_num));
1784 mv643xx_eth_int_handler(netdev->irq, netdev);
1786 mv_write(INTERRUPT_MASK_REG(port_num), ETH_INT_UNMASK_ALL);
1788 #endif
1790 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
1791 int speed, int duplex,
1792 struct ethtool_cmd *cmd)
1794 struct mv643xx_private *mp = netdev_priv(dev);
1796 memset(cmd, 0, sizeof(*cmd));
1798 cmd->port = PORT_MII;
1799 cmd->transceiver = XCVR_INTERNAL;
1800 cmd->phy_address = phy_address;
1802 if (speed == 0) {
1803 cmd->autoneg = AUTONEG_ENABLE;
1804 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
1805 cmd->speed = SPEED_100;
1806 cmd->advertising = ADVERTISED_10baseT_Half |
1807 ADVERTISED_10baseT_Full |
1808 ADVERTISED_100baseT_Half |
1809 ADVERTISED_100baseT_Full;
1810 if (mp->mii.supports_gmii)
1811 cmd->advertising |= ADVERTISED_1000baseT_Full;
1812 } else {
1813 cmd->autoneg = AUTONEG_DISABLE;
1814 cmd->speed = speed;
1815 cmd->duplex = duplex;
1820 * mv643xx_eth_probe
1822 * First function called after registering the network device.
1823 * It's purpose is to initialize the device as an ethernet device,
1824 * fill the ethernet device structure with pointers * to functions,
1825 * and set the MAC address of the interface
1827 * Input : struct device *
1828 * Output : -ENOMEM if failed , 0 if success
1830 static int mv643xx_eth_probe(struct platform_device *pdev)
1832 struct mv643xx_eth_platform_data *pd;
1833 int port_num;
1834 struct mv643xx_private *mp;
1835 struct net_device *dev;
1836 u8 *p;
1837 struct resource *res;
1838 int err;
1839 struct ethtool_cmd cmd;
1840 int duplex = DUPLEX_HALF;
1841 int speed = 0; /* default to auto-negotiation */
1842 DECLARE_MAC_BUF(mac);
1844 pd = pdev->dev.platform_data;
1845 if (pd == NULL) {
1846 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
1847 return -ENODEV;
1850 dev = alloc_etherdev(sizeof(struct mv643xx_private));
1851 if (!dev)
1852 return -ENOMEM;
1854 platform_set_drvdata(pdev, dev);
1856 mp = netdev_priv(dev);
1857 mp->dev = dev;
1858 #ifdef MV643XX_NAPI
1859 netif_napi_add(dev, &mp->napi, mv643xx_poll, 64);
1860 #endif
1862 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1863 BUG_ON(!res);
1864 dev->irq = res->start;
1866 dev->open = mv643xx_eth_open;
1867 dev->stop = mv643xx_eth_stop;
1868 dev->hard_start_xmit = mv643xx_eth_start_xmit;
1869 dev->set_mac_address = mv643xx_eth_set_mac_address;
1870 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
1872 /* No need to Tx Timeout */
1873 dev->tx_timeout = mv643xx_eth_tx_timeout;
1875 #ifdef CONFIG_NET_POLL_CONTROLLER
1876 dev->poll_controller = mv643xx_netpoll;
1877 #endif
1879 dev->watchdog_timeo = 2 * HZ;
1880 dev->base_addr = 0;
1881 dev->change_mtu = mv643xx_eth_change_mtu;
1882 dev->do_ioctl = mv643xx_eth_do_ioctl;
1883 SET_ETHTOOL_OPS(dev, &mv643xx_ethtool_ops);
1885 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1886 #ifdef MAX_SKB_FRAGS
1888 * Zero copy can only work if we use Discovery II memory. Else, we will
1889 * have to map the buffers to ISA memory which is only 16 MB
1891 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
1892 #endif
1893 #endif
1895 /* Configure the timeout task */
1896 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
1898 spin_lock_init(&mp->lock);
1900 port_num = mp->port_num = pd->port_number;
1902 /* set default config values */
1903 eth_port_uc_addr_get(port_num, dev->dev_addr);
1904 mp->rx_ring_size = PORT_DEFAULT_RECEIVE_QUEUE_SIZE;
1905 mp->tx_ring_size = PORT_DEFAULT_TRANSMIT_QUEUE_SIZE;
1907 if (is_valid_ether_addr(pd->mac_addr))
1908 memcpy(dev->dev_addr, pd->mac_addr, 6);
1910 if (pd->phy_addr || pd->force_phy_addr)
1911 ethernet_phy_set(port_num, pd->phy_addr);
1913 if (pd->rx_queue_size)
1914 mp->rx_ring_size = pd->rx_queue_size;
1916 if (pd->tx_queue_size)
1917 mp->tx_ring_size = pd->tx_queue_size;
1919 if (pd->tx_sram_size) {
1920 mp->tx_sram_size = pd->tx_sram_size;
1921 mp->tx_sram_addr = pd->tx_sram_addr;
1924 if (pd->rx_sram_size) {
1925 mp->rx_sram_size = pd->rx_sram_size;
1926 mp->rx_sram_addr = pd->rx_sram_addr;
1929 duplex = pd->duplex;
1930 speed = pd->speed;
1932 /* Hook up MII support for ethtool */
1933 mp->mii.dev = dev;
1934 mp->mii.mdio_read = mv643xx_mdio_read;
1935 mp->mii.mdio_write = mv643xx_mdio_write;
1936 mp->mii.phy_id = ethernet_phy_get(port_num);
1937 mp->mii.phy_id_mask = 0x3f;
1938 mp->mii.reg_num_mask = 0x1f;
1940 err = ethernet_phy_detect(port_num);
1941 if (err) {
1942 pr_debug("MV643xx ethernet port %d: "
1943 "No PHY detected at addr %d\n",
1944 port_num, ethernet_phy_get(port_num));
1945 goto out;
1948 ethernet_phy_reset(port_num);
1949 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
1950 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
1951 mv643xx_eth_update_pscr(dev, &cmd);
1952 mv643xx_set_settings(dev, &cmd);
1954 SET_NETDEV_DEV(dev, &pdev->dev);
1955 err = register_netdev(dev);
1956 if (err)
1957 goto out;
1959 p = dev->dev_addr;
1960 printk(KERN_NOTICE
1961 "%s: port %d with MAC address %s\n",
1962 dev->name, port_num, print_mac(mac, p));
1964 if (dev->features & NETIF_F_SG)
1965 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
1967 if (dev->features & NETIF_F_IP_CSUM)
1968 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
1969 dev->name);
1971 #ifdef MV643XX_CHECKSUM_OFFLOAD_TX
1972 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
1973 #endif
1975 #ifdef MV643XX_COAL
1976 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
1977 dev->name);
1978 #endif
1980 #ifdef MV643XX_NAPI
1981 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
1982 #endif
1984 if (mp->tx_sram_size > 0)
1985 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
1987 return 0;
1989 out:
1990 free_netdev(dev);
1992 return err;
1995 static int mv643xx_eth_remove(struct platform_device *pdev)
1997 struct net_device *dev = platform_get_drvdata(pdev);
1999 unregister_netdev(dev);
2000 flush_scheduled_work();
2002 free_netdev(dev);
2003 platform_set_drvdata(pdev, NULL);
2004 return 0;
2007 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2009 struct resource *res;
2011 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
2013 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2014 if (res == NULL)
2015 return -ENODEV;
2017 mv643xx_eth_base = ioremap(res->start, res->end - res->start + 1);
2018 if (mv643xx_eth_base == NULL)
2019 return -ENOMEM;
2021 return 0;
2025 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2027 iounmap(mv643xx_eth_base);
2028 mv643xx_eth_base = NULL;
2030 return 0;
2033 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2035 struct net_device *dev = platform_get_drvdata(pdev);
2036 struct mv643xx_private *mp = netdev_priv(dev);
2037 unsigned int port_num = mp->port_num;
2039 /* Mask all interrupts on ethernet port */
2040 mv_write(INTERRUPT_MASK_REG(port_num), 0);
2041 mv_read (INTERRUPT_MASK_REG(port_num));
2043 eth_port_reset(port_num);
2046 static struct platform_driver mv643xx_eth_driver = {
2047 .probe = mv643xx_eth_probe,
2048 .remove = mv643xx_eth_remove,
2049 .shutdown = mv643xx_eth_shutdown,
2050 .driver = {
2051 .name = MV643XX_ETH_NAME,
2055 static struct platform_driver mv643xx_eth_shared_driver = {
2056 .probe = mv643xx_eth_shared_probe,
2057 .remove = mv643xx_eth_shared_remove,
2058 .driver = {
2059 .name = MV643XX_ETH_SHARED_NAME,
2064 * mv643xx_init_module
2066 * Registers the network drivers into the Linux kernel
2068 * Input : N/A
2070 * Output : N/A
2072 static int __init mv643xx_init_module(void)
2074 int rc;
2076 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2077 if (!rc) {
2078 rc = platform_driver_register(&mv643xx_eth_driver);
2079 if (rc)
2080 platform_driver_unregister(&mv643xx_eth_shared_driver);
2082 return rc;
2086 * mv643xx_cleanup_module
2088 * Registers the network drivers into the Linux kernel
2090 * Input : N/A
2092 * Output : N/A
2094 static void __exit mv643xx_cleanup_module(void)
2096 platform_driver_unregister(&mv643xx_eth_driver);
2097 platform_driver_unregister(&mv643xx_eth_shared_driver);
2100 module_init(mv643xx_init_module);
2101 module_exit(mv643xx_cleanup_module);
2103 MODULE_LICENSE("GPL");
2104 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2105 " and Dale Farnsworth");
2106 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2107 <<<<<<< HEAD:drivers/net/mv643xx_eth.c
2108 =======
2109 MODULE_ALIAS("platform:mv643xx_eth");
2110 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/net/mv643xx_eth.c
2113 * The second part is the low level driver of the gigE ethernet ports.
2117 * Marvell's Gigabit Ethernet controller low level driver
2119 * DESCRIPTION:
2120 * This file introduce low level API to Marvell's Gigabit Ethernet
2121 * controller. This Gigabit Ethernet Controller driver API controls
2122 * 1) Operations (i.e. port init, start, reset etc').
2123 * 2) Data flow (i.e. port send, receive etc').
2124 * Each Gigabit Ethernet port is controlled via
2125 * struct mv643xx_private.
2126 * This struct includes user configuration information as well as
2127 * driver internal data needed for its operations.
2129 * Supported Features:
2130 * - This low level driver is OS independent. Allocating memory for
2131 * the descriptor rings and buffers are not within the scope of
2132 * this driver.
2133 * - The user is free from Rx/Tx queue managing.
2134 * - This low level driver introduce functionality API that enable
2135 * the to operate Marvell's Gigabit Ethernet Controller in a
2136 * convenient way.
2137 * - Simple Gigabit Ethernet port operation API.
2138 * - Simple Gigabit Ethernet port data flow API.
2139 * - Data flow and operation API support per queue functionality.
2140 * - Support cached descriptors for better performance.
2141 * - Enable access to all four DRAM banks and internal SRAM memory
2142 * spaces.
2143 * - PHY access and control API.
2144 * - Port control register configuration API.
2145 * - Full control over Unicast and Multicast MAC configurations.
2147 * Operation flow:
2149 * Initialization phase
2150 * This phase complete the initialization of the the
2151 * mv643xx_private struct.
2152 * User information regarding port configuration has to be set
2153 * prior to calling the port initialization routine.
2155 * In this phase any port Tx/Rx activity is halted, MIB counters
2156 * are cleared, PHY address is set according to user parameter and
2157 * access to DRAM and internal SRAM memory spaces.
2159 * Driver ring initialization
2160 * Allocating memory for the descriptor rings and buffers is not
2161 * within the scope of this driver. Thus, the user is required to
2162 * allocate memory for the descriptors ring and buffers. Those
2163 * memory parameters are used by the Rx and Tx ring initialization
2164 * routines in order to curve the descriptor linked list in a form
2165 * of a ring.
2166 * Note: Pay special attention to alignment issues when using
2167 * cached descriptors/buffers. In this phase the driver store
2168 * information in the mv643xx_private struct regarding each queue
2169 * ring.
2171 * Driver start
2172 * This phase prepares the Ethernet port for Rx and Tx activity.
2173 * It uses the information stored in the mv643xx_private struct to
2174 * initialize the various port registers.
2176 * Data flow:
2177 * All packet references to/from the driver are done using
2178 * struct pkt_info.
2179 * This struct is a unified struct used with Rx and Tx operations.
2180 * This way the user is not required to be familiar with neither
2181 * Tx nor Rx descriptors structures.
2182 * The driver's descriptors rings are management by indexes.
2183 * Those indexes controls the ring resources and used to indicate
2184 * a SW resource error:
2185 * 'current'
2186 * This index points to the current available resource for use. For
2187 * example in Rx process this index will point to the descriptor
2188 * that will be passed to the user upon calling the receive
2189 * routine. In Tx process, this index will point to the descriptor
2190 * that will be assigned with the user packet info and transmitted.
2191 * 'used'
2192 * This index points to the descriptor that need to restore its
2193 * resources. For example in Rx process, using the Rx buffer return
2194 * API will attach the buffer returned in packet info to the
2195 * descriptor pointed by 'used'. In Tx process, using the Tx
2196 * descriptor return will merely return the user packet info with
2197 * the command status of the transmitted buffer pointed by the
2198 * 'used' index. Nevertheless, it is essential to use this routine
2199 * to update the 'used' index.
2200 * 'first'
2201 * This index supports Tx Scatter-Gather. It points to the first
2202 * descriptor of a packet assembled of multiple buffers. For
2203 * example when in middle of Such packet we have a Tx resource
2204 * error the 'curr' index get the value of 'first' to indicate
2205 * that the ring returned to its state before trying to transmit
2206 * this packet.
2208 * Receive operation:
2209 * The eth_port_receive API set the packet information struct,
2210 * passed by the caller, with received information from the
2211 * 'current' SDMA descriptor.
2212 * It is the user responsibility to return this resource back
2213 * to the Rx descriptor ring to enable the reuse of this source.
2214 * Return Rx resource is done using the eth_rx_return_buff API.
2216 * Prior to calling the initialization routine eth_port_init() the user
2217 * must set the following fields under mv643xx_private struct:
2218 * port_num User Ethernet port number.
2219 * port_config User port configuration value.
2220 * port_config_extend User port config extend value.
2221 * port_sdma_config User port SDMA config value.
2222 * port_serial_control User port serial control value.
2224 * This driver data flow is done using the struct pkt_info which
2225 * is a unified struct for Rx and Tx operations:
2227 * byte_cnt Tx/Rx descriptor buffer byte count.
2228 * l4i_chk CPU provided TCP Checksum. For Tx operation
2229 * only.
2230 * cmd_sts Tx/Rx descriptor command status.
2231 * buf_ptr Tx/Rx descriptor buffer pointer.
2232 * return_info Tx/Rx user resource return information.
2235 /* PHY routines */
2236 static int ethernet_phy_get(unsigned int eth_port_num);
2237 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr);
2239 /* Ethernet Port routines */
2240 static void eth_port_set_filter_table_entry(int table, unsigned char entry);
2243 * eth_port_init - Initialize the Ethernet port driver
2245 * DESCRIPTION:
2246 * This function prepares the ethernet port to start its activity:
2247 * 1) Completes the ethernet port driver struct initialization toward port
2248 * start routine.
2249 * 2) Resets the device to a quiescent state in case of warm reboot.
2250 * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM.
2251 * 4) Clean MAC tables. The reset status of those tables is unknown.
2252 * 5) Set PHY address.
2253 * Note: Call this routine prior to eth_port_start routine and after
2254 * setting user values in the user fields of Ethernet port control
2255 * struct.
2257 * INPUT:
2258 * struct mv643xx_private *mp Ethernet port control struct
2260 * OUTPUT:
2261 * See description.
2263 * RETURN:
2264 * None.
2266 static void eth_port_init(struct mv643xx_private *mp)
2268 mp->rx_resource_err = 0;
2270 eth_port_reset(mp->port_num);
2272 eth_port_init_mac_tables(mp->port_num);
2276 * eth_port_start - Start the Ethernet port activity.
2278 * DESCRIPTION:
2279 * This routine prepares the Ethernet port for Rx and Tx activity:
2280 * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that
2281 * has been initialized a descriptor's ring (using
2282 * ether_init_tx_desc_ring for Tx and ether_init_rx_desc_ring for Rx)
2283 * 2. Initialize and enable the Ethernet configuration port by writing to
2284 * the port's configuration and command registers.
2285 * 3. Initialize and enable the SDMA by writing to the SDMA's
2286 * configuration and command registers. After completing these steps,
2287 * the ethernet port SDMA can starts to perform Rx and Tx activities.
2289 * Note: Each Rx and Tx queue descriptor's list must be initialized prior
2290 * to calling this function (use ether_init_tx_desc_ring for Tx queues
2291 * and ether_init_rx_desc_ring for Rx queues).
2293 * INPUT:
2294 * dev - a pointer to the required interface
2296 * OUTPUT:
2297 * Ethernet port is ready to receive and transmit.
2299 * RETURN:
2300 * None.
2302 static void eth_port_start(struct net_device *dev)
2304 struct mv643xx_private *mp = netdev_priv(dev);
2305 unsigned int port_num = mp->port_num;
2306 int tx_curr_desc, rx_curr_desc;
2307 u32 pscr;
2308 struct ethtool_cmd ethtool_cmd;
2310 /* Assignment of Tx CTRP of given queue */
2311 tx_curr_desc = mp->tx_curr_desc_q;
2312 mv_write(TX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2313 (u32)((struct eth_tx_desc *)mp->tx_desc_dma + tx_curr_desc));
2315 /* Assignment of Rx CRDP of given queue */
2316 rx_curr_desc = mp->rx_curr_desc_q;
2317 mv_write(RX_CURRENT_QUEUE_DESC_PTR_0(port_num),
2318 (u32)((struct eth_rx_desc *)mp->rx_desc_dma + rx_curr_desc));
2320 /* Add the assigned Ethernet address to the port's address table */
2321 eth_port_uc_addr_set(port_num, dev->dev_addr);
2323 /* Assign port configuration and command. */
2324 mv_write(PORT_CONFIG_REG(port_num),
2325 PORT_CONFIG_DEFAULT_VALUE);
2327 mv_write(PORT_CONFIG_EXTEND_REG(port_num),
2328 PORT_CONFIG_EXTEND_DEFAULT_VALUE);
2330 pscr = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
2332 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
2333 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
2335 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
2336 DISABLE_AUTO_NEG_SPEED_GMII |
2337 DISABLE_AUTO_NEG_FOR_DUPLX |
2338 DO_NOT_FORCE_LINK_FAIL |
2339 SERIAL_PORT_CONTROL_RESERVED;
2341 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
2343 pscr |= SERIAL_PORT_ENABLE;
2344 mv_write(PORT_SERIAL_CONTROL_REG(port_num), pscr);
2346 /* Assign port SDMA configuration */
2347 mv_write(SDMA_CONFIG_REG(port_num),
2348 PORT_SDMA_CONFIG_DEFAULT_VALUE);
2350 /* Enable port Rx. */
2351 mv643xx_eth_port_enable_rx(port_num, ETH_RX_QUEUES_ENABLED);
2353 /* Disable port bandwidth limits by clearing MTU register */
2354 mv_write(MAXIMUM_TRANSMIT_UNIT(port_num), 0);
2356 /* save phy settings across reset */
2357 mv643xx_get_settings(dev, &ethtool_cmd);
2358 ethernet_phy_reset(mp->port_num);
2359 mv643xx_set_settings(dev, &ethtool_cmd);
2363 * eth_port_uc_addr_set - Write a MAC address into the port's hw registers
2365 static void eth_port_uc_addr_set(unsigned int port_num, unsigned char *p_addr)
2367 unsigned int mac_h;
2368 unsigned int mac_l;
2369 int table;
2371 mac_l = (p_addr[4] << 8) | (p_addr[5]);
2372 mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
2373 (p_addr[3] << 0);
2375 mv_write(MAC_ADDR_LOW(port_num), mac_l);
2376 mv_write(MAC_ADDR_HIGH(port_num), mac_h);
2378 /* Accept frames with this address */
2379 table = DA_FILTER_UNICAST_TABLE_BASE(port_num);
2380 eth_port_set_filter_table_entry(table, p_addr[5] & 0x0f);
2384 * eth_port_uc_addr_get - Read the MAC address from the port's hw registers
2386 static void eth_port_uc_addr_get(unsigned int port_num, unsigned char *p_addr)
2388 unsigned int mac_h;
2389 unsigned int mac_l;
2391 mac_h = mv_read(MAC_ADDR_HIGH(port_num));
2392 mac_l = mv_read(MAC_ADDR_LOW(port_num));
2394 p_addr[0] = (mac_h >> 24) & 0xff;
2395 p_addr[1] = (mac_h >> 16) & 0xff;
2396 p_addr[2] = (mac_h >> 8) & 0xff;
2397 p_addr[3] = mac_h & 0xff;
2398 p_addr[4] = (mac_l >> 8) & 0xff;
2399 p_addr[5] = mac_l & 0xff;
2403 * The entries in each table are indexed by a hash of a packet's MAC
2404 * address. One bit in each entry determines whether the packet is
2405 * accepted. There are 4 entries (each 8 bits wide) in each register
2406 * of the table. The bits in each entry are defined as follows:
2407 * 0 Accept=1, Drop=0
2408 * 3-1 Queue (ETH_Q0=0)
2409 * 7-4 Reserved = 0;
2411 static void eth_port_set_filter_table_entry(int table, unsigned char entry)
2413 unsigned int table_reg;
2414 unsigned int tbl_offset;
2415 unsigned int reg_offset;
2417 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
2418 reg_offset = entry % 4; /* Entry offset within the register */
2420 /* Set "accepts frame bit" at specified table entry */
2421 table_reg = mv_read(table + tbl_offset);
2422 table_reg |= 0x01 << (8 * reg_offset);
2423 mv_write(table + tbl_offset, table_reg);
2427 * eth_port_mc_addr - Multicast address settings.
2429 * The MV device supports multicast using two tables:
2430 * 1) Special Multicast Table for MAC addresses of the form
2431 * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_FF).
2432 * The MAC DA[7:0] bits are used as a pointer to the Special Multicast
2433 * Table entries in the DA-Filter table.
2434 * 2) Other Multicast Table for multicast of another type. A CRC-8bit
2435 * is used as an index to the Other Multicast Table entries in the
2436 * DA-Filter table. This function calculates the CRC-8bit value.
2437 * In either case, eth_port_set_filter_table_entry() is then called
2438 * to set to set the actual table entry.
2440 static void eth_port_mc_addr(unsigned int eth_port_num, unsigned char *p_addr)
2442 unsigned int mac_h;
2443 unsigned int mac_l;
2444 unsigned char crc_result = 0;
2445 int table;
2446 int mac_array[48];
2447 int crc[8];
2448 int i;
2450 if ((p_addr[0] == 0x01) && (p_addr[1] == 0x00) &&
2451 (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) {
2452 table = DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2453 (eth_port_num);
2454 eth_port_set_filter_table_entry(table, p_addr[5]);
2455 return;
2458 /* Calculate CRC-8 out of the given address */
2459 mac_h = (p_addr[0] << 8) | (p_addr[1]);
2460 mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) |
2461 (p_addr[4] << 8) | (p_addr[5] << 0);
2463 for (i = 0; i < 32; i++)
2464 mac_array[i] = (mac_l >> i) & 0x1;
2465 for (i = 32; i < 48; i++)
2466 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
2468 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
2469 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
2470 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
2471 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
2472 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
2474 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2475 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
2476 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
2477 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
2478 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
2479 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
2480 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
2482 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
2483 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
2484 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
2485 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
2486 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
2487 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
2489 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
2490 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
2491 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
2492 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
2493 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
2494 mac_array[3] ^ mac_array[2] ^ mac_array[1];
2496 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
2497 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
2498 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
2499 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
2500 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
2501 mac_array[3] ^ mac_array[2];
2503 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
2504 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
2505 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
2506 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
2507 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
2508 mac_array[4] ^ mac_array[3];
2510 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
2511 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
2512 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
2513 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
2514 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
2515 mac_array[4];
2517 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
2518 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
2519 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
2520 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
2521 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
2523 for (i = 0; i < 8; i++)
2524 crc_result = crc_result | (crc[i] << i);
2526 table = DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num);
2527 eth_port_set_filter_table_entry(table, crc_result);
2531 * Set the entire multicast list based on dev->mc_list.
2533 static void eth_port_set_multicast_list(struct net_device *dev)
2536 struct dev_mc_list *mc_list;
2537 int i;
2538 int table_index;
2539 struct mv643xx_private *mp = netdev_priv(dev);
2540 unsigned int eth_port_num = mp->port_num;
2542 /* If the device is in promiscuous mode or in all multicast mode,
2543 * we will fully populate both multicast tables with accept.
2544 * This is guaranteed to yield a match on all multicast addresses...
2546 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
2547 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2548 /* Set all entries in DA filter special multicast
2549 * table (Ex_dFSMT)
2550 * Set for ETH_Q0 for now
2551 * Bits
2552 * 0 Accept=1, Drop=0
2553 * 3-1 Queue ETH_Q0=0
2554 * 7-4 Reserved = 0;
2556 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2558 /* Set all entries in DA filter other multicast
2559 * table (Ex_dFOMT)
2560 * Set for ETH_Q0 for now
2561 * Bits
2562 * 0 Accept=1, Drop=0
2563 * 3-1 Queue ETH_Q0=0
2564 * 7-4 Reserved = 0;
2566 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE(eth_port_num) + table_index, 0x01010101);
2568 return;
2571 /* We will clear out multicast tables every time we get the list.
2572 * Then add the entire new list...
2574 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2575 /* Clear DA filter special multicast table (Ex_dFSMT) */
2576 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2577 (eth_port_num) + table_index, 0);
2579 /* Clear DA filter other multicast table (Ex_dFOMT) */
2580 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2581 (eth_port_num) + table_index, 0);
2584 /* Get pointer to net_device multicast list and add each one... */
2585 for (i = 0, mc_list = dev->mc_list;
2586 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
2587 i++, mc_list = mc_list->next)
2588 if (mc_list->dmi_addrlen == 6)
2589 eth_port_mc_addr(eth_port_num, mc_list->dmi_addr);
2593 * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
2595 * DESCRIPTION:
2596 * Go through all the DA filter tables (Unicast, Special Multicast &
2597 * Other Multicast) and set each entry to 0.
2599 * INPUT:
2600 * unsigned int eth_port_num Ethernet Port number.
2602 * OUTPUT:
2603 * Multicast and Unicast packets are rejected.
2605 * RETURN:
2606 * None.
2608 static void eth_port_init_mac_tables(unsigned int eth_port_num)
2610 int table_index;
2612 /* Clear DA filter unicast table (Ex_dFUT) */
2613 for (table_index = 0; table_index <= 0xC; table_index += 4)
2614 mv_write(DA_FILTER_UNICAST_TABLE_BASE
2615 (eth_port_num) + table_index, 0);
2617 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
2618 /* Clear DA filter special multicast table (Ex_dFSMT) */
2619 mv_write(DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE
2620 (eth_port_num) + table_index, 0);
2621 /* Clear DA filter other multicast table (Ex_dFOMT) */
2622 mv_write(DA_FILTER_OTHER_MULTICAST_TABLE_BASE
2623 (eth_port_num) + table_index, 0);
2628 * eth_clear_mib_counters - Clear all MIB counters
2630 * DESCRIPTION:
2631 * This function clears all MIB counters of a specific ethernet port.
2632 * A read from the MIB counter will reset the counter.
2634 * INPUT:
2635 * unsigned int eth_port_num Ethernet Port number.
2637 * OUTPUT:
2638 * After reading all MIB counters, the counters resets.
2640 * RETURN:
2641 * MIB counter value.
2644 static void eth_clear_mib_counters(unsigned int eth_port_num)
2646 int i;
2648 /* Perform dummy reads from MIB counters */
2649 for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION;
2650 i += 4)
2651 mv_read(MIB_COUNTERS_BASE(eth_port_num) + i);
2654 static inline u32 read_mib(struct mv643xx_private *mp, int offset)
2656 return mv_read(MIB_COUNTERS_BASE(mp->port_num) + offset);
2659 static void eth_update_mib_counters(struct mv643xx_private *mp)
2661 struct mv643xx_mib_counters *p = &mp->mib_counters;
2662 int offset;
2664 p->good_octets_received +=
2665 read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_LOW);
2666 p->good_octets_received +=
2667 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32;
2669 for (offset = ETH_MIB_BAD_OCTETS_RECEIVED;
2670 offset <= ETH_MIB_FRAMES_1024_TO_MAX_OCTETS;
2671 offset += 4)
2672 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2674 p->good_octets_sent += read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_LOW);
2675 p->good_octets_sent +=
2676 (u64)read_mib(mp, ETH_MIB_GOOD_OCTETS_SENT_HIGH) << 32;
2678 for (offset = ETH_MIB_GOOD_FRAMES_SENT;
2679 offset <= ETH_MIB_LATE_COLLISION;
2680 offset += 4)
2681 *(u32 *)((char *)p + offset) += read_mib(mp, offset);
2685 * ethernet_phy_detect - Detect whether a phy is present
2687 * DESCRIPTION:
2688 * This function tests whether there is a PHY present on
2689 * the specified port.
2691 * INPUT:
2692 * unsigned int eth_port_num Ethernet Port number.
2694 * OUTPUT:
2695 * None
2697 * RETURN:
2698 * 0 on success
2699 * -ENODEV on failure
2702 static int ethernet_phy_detect(unsigned int port_num)
2704 unsigned int phy_reg_data0;
2705 int auto_neg;
2707 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2708 auto_neg = phy_reg_data0 & 0x1000;
2709 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2710 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2712 eth_port_read_smi_reg(port_num, 0, &phy_reg_data0);
2713 if ((phy_reg_data0 & 0x1000) == auto_neg)
2714 return -ENODEV; /* change didn't take */
2716 phy_reg_data0 ^= 0x1000;
2717 eth_port_write_smi_reg(port_num, 0, phy_reg_data0);
2718 return 0;
2722 * ethernet_phy_get - Get the ethernet port PHY address.
2724 * DESCRIPTION:
2725 * This routine returns the given ethernet port PHY address.
2727 * INPUT:
2728 * unsigned int eth_port_num Ethernet Port number.
2730 * OUTPUT:
2731 * None.
2733 * RETURN:
2734 * PHY address.
2737 static int ethernet_phy_get(unsigned int eth_port_num)
2739 unsigned int reg_data;
2741 reg_data = mv_read(PHY_ADDR_REG);
2743 return ((reg_data >> (5 * eth_port_num)) & 0x1f);
2747 * ethernet_phy_set - Set the ethernet port PHY address.
2749 * DESCRIPTION:
2750 * This routine sets the given ethernet port PHY address.
2752 * INPUT:
2753 * unsigned int eth_port_num Ethernet Port number.
2754 * int phy_addr PHY address.
2756 * OUTPUT:
2757 * None.
2759 * RETURN:
2760 * None.
2763 static void ethernet_phy_set(unsigned int eth_port_num, int phy_addr)
2765 u32 reg_data;
2766 int addr_shift = 5 * eth_port_num;
2768 reg_data = mv_read(PHY_ADDR_REG);
2769 reg_data &= ~(0x1f << addr_shift);
2770 reg_data |= (phy_addr & 0x1f) << addr_shift;
2771 mv_write(PHY_ADDR_REG, reg_data);
2775 * ethernet_phy_reset - Reset Ethernet port PHY.
2777 * DESCRIPTION:
2778 * This routine utilizes the SMI interface to reset the ethernet port PHY.
2780 * INPUT:
2781 * unsigned int eth_port_num Ethernet Port number.
2783 * OUTPUT:
2784 * The PHY is reset.
2786 * RETURN:
2787 * None.
2790 static void ethernet_phy_reset(unsigned int eth_port_num)
2792 unsigned int phy_reg_data;
2794 /* Reset the PHY */
2795 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2796 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
2797 eth_port_write_smi_reg(eth_port_num, 0, phy_reg_data);
2799 /* wait for PHY to come out of reset */
2800 do {
2801 udelay(1);
2802 eth_port_read_smi_reg(eth_port_num, 0, &phy_reg_data);
2803 } while (phy_reg_data & 0x8000);
2806 static void mv643xx_eth_port_enable_tx(unsigned int port_num,
2807 unsigned int queues)
2809 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), queues);
2812 static void mv643xx_eth_port_enable_rx(unsigned int port_num,
2813 unsigned int queues)
2815 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), queues);
2818 static unsigned int mv643xx_eth_port_disable_tx(unsigned int port_num)
2820 u32 queues;
2822 /* Stop Tx port activity. Check port Tx activity. */
2823 queues = mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF;
2824 if (queues) {
2825 /* Issue stop command for active queues only */
2826 mv_write(TRANSMIT_QUEUE_COMMAND_REG(port_num), (queues << 8));
2828 /* Wait for all Tx activity to terminate. */
2829 /* Check port cause register that all Tx queues are stopped */
2830 while (mv_read(TRANSMIT_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2831 udelay(PHY_WAIT_MICRO_SECONDS);
2833 /* Wait for Tx FIFO to empty */
2834 while (mv_read(PORT_STATUS_REG(port_num)) &
2835 ETH_PORT_TX_FIFO_EMPTY)
2836 udelay(PHY_WAIT_MICRO_SECONDS);
2839 return queues;
2842 static unsigned int mv643xx_eth_port_disable_rx(unsigned int port_num)
2844 u32 queues;
2846 /* Stop Rx port activity. Check port Rx activity. */
2847 queues = mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF;
2848 if (queues) {
2849 /* Issue stop command for active queues only */
2850 mv_write(RECEIVE_QUEUE_COMMAND_REG(port_num), (queues << 8));
2852 /* Wait for all Rx activity to terminate. */
2853 /* Check port cause register that all Rx queues are stopped */
2854 while (mv_read(RECEIVE_QUEUE_COMMAND_REG(port_num)) & 0xFF)
2855 udelay(PHY_WAIT_MICRO_SECONDS);
2858 return queues;
2862 * eth_port_reset - Reset Ethernet port
2864 * DESCRIPTION:
2865 * This routine resets the chip by aborting any SDMA engine activity and
2866 * clearing the MIB counters. The Receiver and the Transmit unit are in
2867 * idle state after this command is performed and the port is disabled.
2869 * INPUT:
2870 * unsigned int eth_port_num Ethernet Port number.
2872 * OUTPUT:
2873 * Channel activity is halted.
2875 * RETURN:
2876 * None.
2879 static void eth_port_reset(unsigned int port_num)
2881 unsigned int reg_data;
2883 mv643xx_eth_port_disable_tx(port_num);
2884 mv643xx_eth_port_disable_rx(port_num);
2886 /* Clear all MIB counters */
2887 eth_clear_mib_counters(port_num);
2889 /* Reset the Enable bit in the Configuration Register */
2890 reg_data = mv_read(PORT_SERIAL_CONTROL_REG(port_num));
2891 reg_data &= ~(SERIAL_PORT_ENABLE |
2892 DO_NOT_FORCE_LINK_FAIL |
2893 FORCE_LINK_PASS);
2894 mv_write(PORT_SERIAL_CONTROL_REG(port_num), reg_data);
2899 * eth_port_read_smi_reg - Read PHY registers
2901 * DESCRIPTION:
2902 * This routine utilize the SMI interface to interact with the PHY in
2903 * order to perform PHY register read.
2905 * INPUT:
2906 * unsigned int port_num Ethernet Port number.
2907 * unsigned int phy_reg PHY register address offset.
2908 * unsigned int *value Register value buffer.
2910 * OUTPUT:
2911 * Write the value of a specified PHY register into given buffer.
2913 * RETURN:
2914 * false if the PHY is busy or read data is not in valid state.
2915 * true otherwise.
2918 static void eth_port_read_smi_reg(unsigned int port_num,
2919 unsigned int phy_reg, unsigned int *value)
2921 int phy_addr = ethernet_phy_get(port_num);
2922 unsigned long flags;
2923 int i;
2925 /* the SMI register is a shared resource */
2926 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2928 /* wait for the SMI register to become available */
2929 for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) {
2930 if (i == PHY_WAIT_ITERATIONS) {
2931 printk("mv643xx PHY busy timeout, port %d\n", port_num);
2932 goto out;
2934 udelay(PHY_WAIT_MICRO_SECONDS);
2937 mv_write(SMI_REG,
2938 (phy_addr << 16) | (phy_reg << 21) | ETH_SMI_OPCODE_READ);
2940 /* now wait for the data to be valid */
2941 for (i = 0; !(mv_read(SMI_REG) & ETH_SMI_READ_VALID); i++) {
2942 if (i == PHY_WAIT_ITERATIONS) {
2943 printk("mv643xx PHY read timeout, port %d\n", port_num);
2944 goto out;
2946 udelay(PHY_WAIT_MICRO_SECONDS);
2949 *value = mv_read(SMI_REG) & 0xffff;
2950 out:
2951 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
2955 * eth_port_write_smi_reg - Write to PHY registers
2957 * DESCRIPTION:
2958 * This routine utilize the SMI interface to interact with the PHY in
2959 * order to perform writes to PHY registers.
2961 * INPUT:
2962 * unsigned int eth_port_num Ethernet Port number.
2963 * unsigned int phy_reg PHY register address offset.
2964 * unsigned int value Register value.
2966 * OUTPUT:
2967 * Write the given value to the specified PHY register.
2969 * RETURN:
2970 * false if the PHY is busy.
2971 * true otherwise.
2974 static void eth_port_write_smi_reg(unsigned int eth_port_num,
2975 unsigned int phy_reg, unsigned int value)
2977 int phy_addr;
2978 int i;
2979 unsigned long flags;
2981 phy_addr = ethernet_phy_get(eth_port_num);
2983 /* the SMI register is a shared resource */
2984 spin_lock_irqsave(&mv643xx_eth_phy_lock, flags);
2986 /* wait for the SMI register to become available */
2987 for (i = 0; mv_read(SMI_REG) & ETH_SMI_BUSY; i++) {
2988 if (i == PHY_WAIT_ITERATIONS) {
2989 printk("mv643xx PHY busy timeout, port %d\n",
2990 eth_port_num);
2991 goto out;
2993 udelay(PHY_WAIT_MICRO_SECONDS);
2996 mv_write(SMI_REG, (phy_addr << 16) | (phy_reg << 21) |
2997 ETH_SMI_OPCODE_WRITE | (value & 0xffff));
2998 out:
2999 spin_unlock_irqrestore(&mv643xx_eth_phy_lock, flags);
3003 * Wrappers for MII support library.
3005 static int mv643xx_mdio_read(struct net_device *dev, int phy_id, int location)
3007 int val;
3008 struct mv643xx_private *mp = netdev_priv(dev);
3010 eth_port_read_smi_reg(mp->port_num, location, &val);
3011 return val;
3014 static void mv643xx_mdio_write(struct net_device *dev, int phy_id, int location, int val)
3016 struct mv643xx_private *mp = netdev_priv(dev);
3017 eth_port_write_smi_reg(mp->port_num, location, val);
3021 * eth_port_receive - Get received information from Rx ring.
3023 * DESCRIPTION:
3024 * This routine returns the received data to the caller. There is no
3025 * data copying during routine operation. All information is returned
3026 * using pointer to packet information struct passed from the caller.
3027 * If the routine exhausts Rx ring resources then the resource error flag
3028 * is set.
3030 * INPUT:
3031 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3032 * struct pkt_info *p_pkt_info User packet buffer.
3034 * OUTPUT:
3035 * Rx ring current and used indexes are updated.
3037 * RETURN:
3038 * ETH_ERROR in case the routine can not access Rx desc ring.
3039 * ETH_QUEUE_FULL if Rx ring resources are exhausted.
3040 * ETH_END_OF_JOB if there is no received data.
3041 * ETH_OK otherwise.
3043 static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
3044 struct pkt_info *p_pkt_info)
3046 int rx_next_curr_desc, rx_curr_desc, rx_used_desc;
3047 volatile struct eth_rx_desc *p_rx_desc;
3048 unsigned int command_status;
3049 unsigned long flags;
3051 /* Do not process Rx ring in case of Rx ring resource error */
3052 if (mp->rx_resource_err)
3053 return ETH_QUEUE_FULL;
3055 spin_lock_irqsave(&mp->lock, flags);
3057 /* Get the Rx Desc ring 'curr and 'used' indexes */
3058 rx_curr_desc = mp->rx_curr_desc_q;
3059 rx_used_desc = mp->rx_used_desc_q;
3061 p_rx_desc = &mp->p_rx_desc_area[rx_curr_desc];
3063 /* The following parameters are used to save readings from memory */
3064 command_status = p_rx_desc->cmd_sts;
3065 rmb();
3067 /* Nothing to receive... */
3068 if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) {
3069 spin_unlock_irqrestore(&mp->lock, flags);
3070 return ETH_END_OF_JOB;
3073 p_pkt_info->byte_cnt = (p_rx_desc->byte_cnt) - RX_BUF_OFFSET;
3074 p_pkt_info->cmd_sts = command_status;
3075 p_pkt_info->buf_ptr = (p_rx_desc->buf_ptr) + RX_BUF_OFFSET;
3076 p_pkt_info->return_info = mp->rx_skb[rx_curr_desc];
3077 p_pkt_info->l4i_chk = p_rx_desc->buf_size;
3080 * Clean the return info field to indicate that the
3081 * packet has been moved to the upper layers
3083 mp->rx_skb[rx_curr_desc] = NULL;
3085 /* Update current index in data structure */
3086 rx_next_curr_desc = (rx_curr_desc + 1) % mp->rx_ring_size;
3087 mp->rx_curr_desc_q = rx_next_curr_desc;
3089 /* Rx descriptors exhausted. Set the Rx ring resource error flag */
3090 if (rx_next_curr_desc == rx_used_desc)
3091 mp->rx_resource_err = 1;
3093 spin_unlock_irqrestore(&mp->lock, flags);
3095 return ETH_OK;
3099 * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring.
3101 * DESCRIPTION:
3102 * This routine returns a Rx buffer back to the Rx ring. It retrieves the
3103 * next 'used' descriptor and attached the returned buffer to it.
3104 * In case the Rx ring was in "resource error" condition, where there are
3105 * no available Rx resources, the function resets the resource error flag.
3107 * INPUT:
3108 * struct mv643xx_private *mp Ethernet Port Control srtuct.
3109 * struct pkt_info *p_pkt_info Information on returned buffer.
3111 * OUTPUT:
3112 * New available Rx resource in Rx descriptor ring.
3114 * RETURN:
3115 * ETH_ERROR in case the routine can not access Rx desc ring.
3116 * ETH_OK otherwise.
3118 static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
3119 struct pkt_info *p_pkt_info)
3121 int used_rx_desc; /* Where to return Rx resource */
3122 volatile struct eth_rx_desc *p_used_rx_desc;
3123 unsigned long flags;
3125 spin_lock_irqsave(&mp->lock, flags);
3127 /* Get 'used' Rx descriptor */
3128 used_rx_desc = mp->rx_used_desc_q;
3129 p_used_rx_desc = &mp->p_rx_desc_area[used_rx_desc];
3131 p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr;
3132 p_used_rx_desc->buf_size = p_pkt_info->byte_cnt;
3133 mp->rx_skb[used_rx_desc] = p_pkt_info->return_info;
3135 /* Flush the write pipe */
3137 /* Return the descriptor to DMA ownership */
3138 wmb();
3139 p_used_rx_desc->cmd_sts =
3140 ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT;
3141 wmb();
3143 /* Move the used descriptor pointer to the next descriptor */
3144 mp->rx_used_desc_q = (used_rx_desc + 1) % mp->rx_ring_size;
3146 /* Any Rx return cancels the Rx resource error status */
3147 mp->rx_resource_err = 0;
3149 spin_unlock_irqrestore(&mp->lock, flags);
3151 return ETH_OK;
3154 /************* Begin ethtool support *************************/
3156 struct mv643xx_stats {
3157 char stat_string[ETH_GSTRING_LEN];
3158 int sizeof_stat;
3159 int stat_offset;
3162 #define MV643XX_STAT(m) sizeof(((struct mv643xx_private *)0)->m), \
3163 offsetof(struct mv643xx_private, m)
3165 static const struct mv643xx_stats mv643xx_gstrings_stats[] = {
3166 { "rx_packets", MV643XX_STAT(stats.rx_packets) },
3167 { "tx_packets", MV643XX_STAT(stats.tx_packets) },
3168 { "rx_bytes", MV643XX_STAT(stats.rx_bytes) },
3169 { "tx_bytes", MV643XX_STAT(stats.tx_bytes) },
3170 { "rx_errors", MV643XX_STAT(stats.rx_errors) },
3171 { "tx_errors", MV643XX_STAT(stats.tx_errors) },
3172 { "rx_dropped", MV643XX_STAT(stats.rx_dropped) },
3173 { "tx_dropped", MV643XX_STAT(stats.tx_dropped) },
3174 { "good_octets_received", MV643XX_STAT(mib_counters.good_octets_received) },
3175 { "bad_octets_received", MV643XX_STAT(mib_counters.bad_octets_received) },
3176 { "internal_mac_transmit_err", MV643XX_STAT(mib_counters.internal_mac_transmit_err) },
3177 { "good_frames_received", MV643XX_STAT(mib_counters.good_frames_received) },
3178 { "bad_frames_received", MV643XX_STAT(mib_counters.bad_frames_received) },
3179 { "broadcast_frames_received", MV643XX_STAT(mib_counters.broadcast_frames_received) },
3180 { "multicast_frames_received", MV643XX_STAT(mib_counters.multicast_frames_received) },
3181 { "frames_64_octets", MV643XX_STAT(mib_counters.frames_64_octets) },
3182 { "frames_65_to_127_octets", MV643XX_STAT(mib_counters.frames_65_to_127_octets) },
3183 { "frames_128_to_255_octets", MV643XX_STAT(mib_counters.frames_128_to_255_octets) },
3184 { "frames_256_to_511_octets", MV643XX_STAT(mib_counters.frames_256_to_511_octets) },
3185 { "frames_512_to_1023_octets", MV643XX_STAT(mib_counters.frames_512_to_1023_octets) },
3186 { "frames_1024_to_max_octets", MV643XX_STAT(mib_counters.frames_1024_to_max_octets) },
3187 { "good_octets_sent", MV643XX_STAT(mib_counters.good_octets_sent) },
3188 { "good_frames_sent", MV643XX_STAT(mib_counters.good_frames_sent) },
3189 { "excessive_collision", MV643XX_STAT(mib_counters.excessive_collision) },
3190 { "multicast_frames_sent", MV643XX_STAT(mib_counters.multicast_frames_sent) },
3191 { "broadcast_frames_sent", MV643XX_STAT(mib_counters.broadcast_frames_sent) },
3192 { "unrec_mac_control_received", MV643XX_STAT(mib_counters.unrec_mac_control_received) },
3193 { "fc_sent", MV643XX_STAT(mib_counters.fc_sent) },
3194 { "good_fc_received", MV643XX_STAT(mib_counters.good_fc_received) },
3195 { "bad_fc_received", MV643XX_STAT(mib_counters.bad_fc_received) },
3196 { "undersize_received", MV643XX_STAT(mib_counters.undersize_received) },
3197 { "fragments_received", MV643XX_STAT(mib_counters.fragments_received) },
3198 { "oversize_received", MV643XX_STAT(mib_counters.oversize_received) },
3199 { "jabber_received", MV643XX_STAT(mib_counters.jabber_received) },
3200 { "mac_receive_error", MV643XX_STAT(mib_counters.mac_receive_error) },
3201 { "bad_crc_event", MV643XX_STAT(mib_counters.bad_crc_event) },
3202 { "collision", MV643XX_STAT(mib_counters.collision) },
3203 { "late_collision", MV643XX_STAT(mib_counters.late_collision) },
3206 #define MV643XX_STATS_LEN ARRAY_SIZE(mv643xx_gstrings_stats)
3208 static void mv643xx_get_drvinfo(struct net_device *netdev,
3209 struct ethtool_drvinfo *drvinfo)
3211 strncpy(drvinfo->driver, mv643xx_driver_name, 32);
3212 strncpy(drvinfo->version, mv643xx_driver_version, 32);
3213 strncpy(drvinfo->fw_version, "N/A", 32);
3214 strncpy(drvinfo->bus_info, "mv643xx", 32);
3215 drvinfo->n_stats = MV643XX_STATS_LEN;
3218 static int mv643xx_get_sset_count(struct net_device *netdev, int sset)
3220 switch (sset) {
3221 case ETH_SS_STATS:
3222 return MV643XX_STATS_LEN;
3223 default:
3224 return -EOPNOTSUPP;
3228 static void mv643xx_get_ethtool_stats(struct net_device *netdev,
3229 struct ethtool_stats *stats, uint64_t *data)
3231 struct mv643xx_private *mp = netdev->priv;
3232 int i;
3234 eth_update_mib_counters(mp);
3236 for (i = 0; i < MV643XX_STATS_LEN; i++) {
3237 char *p = (char *)mp+mv643xx_gstrings_stats[i].stat_offset;
3238 data[i] = (mv643xx_gstrings_stats[i].sizeof_stat ==
3239 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
3243 static void mv643xx_get_strings(struct net_device *netdev, uint32_t stringset,
3244 uint8_t *data)
3246 int i;
3248 switch(stringset) {
3249 case ETH_SS_STATS:
3250 for (i=0; i < MV643XX_STATS_LEN; i++) {
3251 memcpy(data + i * ETH_GSTRING_LEN,
3252 mv643xx_gstrings_stats[i].stat_string,
3253 ETH_GSTRING_LEN);
3255 break;
3259 static u32 mv643xx_eth_get_link(struct net_device *dev)
3261 struct mv643xx_private *mp = netdev_priv(dev);
3263 return mii_link_ok(&mp->mii);
3266 static int mv643xx_eth_nway_restart(struct net_device *dev)
3268 struct mv643xx_private *mp = netdev_priv(dev);
3270 return mii_nway_restart(&mp->mii);
3273 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3275 struct mv643xx_private *mp = netdev_priv(dev);
3277 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
3280 static const struct ethtool_ops mv643xx_ethtool_ops = {
3281 .get_settings = mv643xx_get_settings,
3282 .set_settings = mv643xx_set_settings,
3283 .get_drvinfo = mv643xx_get_drvinfo,
3284 .get_link = mv643xx_eth_get_link,
3285 .set_sg = ethtool_op_set_sg,
3286 .get_sset_count = mv643xx_get_sset_count,
3287 .get_ethtool_stats = mv643xx_get_ethtool_stats,
3288 .get_strings = mv643xx_get_strings,
3289 .nway_reset = mv643xx_eth_nway_restart,
3292 /************* End ethtool support *************************/