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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / drivers / i2c / busses / i2c-pmcmsp.c
blobf93bf8894a9647ba61a0e2468340d2fcb8b0afed
1 /*
2 * Specific bus support for PMC-TWI compliant implementation on MSP71xx.
3 *
4 * Copyright 2005-2007 PMC-Sierra, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/init.h>
30 #include <linux/platform_device.h>
31 #include <linux/i2c.h>
32 #include <linux/interrupt.h>
33 #include <linux/completion.h>
34 #include <linux/mutex.h>
35 #include <linux/delay.h>
36 #include <asm/io.h>
37
38 #define DRV_NAME "pmcmsptwi"
39
40 #define MSP_TWI_SF_CLK_REG_OFFSET 0x00
41 #define MSP_TWI_HS_CLK_REG_OFFSET 0x04
42 #define MSP_TWI_CFG_REG_OFFSET 0x08
43 #define MSP_TWI_CMD_REG_OFFSET 0x0c
44 #define MSP_TWI_ADD_REG_OFFSET 0x10
45 #define MSP_TWI_DAT_0_REG_OFFSET 0x14
46 #define MSP_TWI_DAT_1_REG_OFFSET 0x18
47 #define MSP_TWI_INT_STS_REG_OFFSET 0x1c
48 #define MSP_TWI_INT_MSK_REG_OFFSET 0x20
49 #define MSP_TWI_BUSY_REG_OFFSET 0x24
50
51 #define MSP_TWI_INT_STS_DONE (1 << 0)
52 #define MSP_TWI_INT_STS_LOST_ARBITRATION (1 << 1)
53 #define MSP_TWI_INT_STS_NO_RESPONSE (1 << 2)
54 #define MSP_TWI_INT_STS_DATA_COLLISION (1 << 3)
55 #define MSP_TWI_INT_STS_BUSY (1 << 4)
56 #define MSP_TWI_INT_STS_ALL 0x1f
57
58 #define MSP_MAX_BYTES_PER_RW 8
59 #define MSP_MAX_POLL 5
60 #define MSP_POLL_DELAY 10
61 #define MSP_IRQ_TIMEOUT (MSP_MAX_POLL * MSP_POLL_DELAY)
62
63 /* IO Operation macros */
64 #define pmcmsptwi_readl __raw_readl
65 #define pmcmsptwi_writel __raw_writel
66
67 /* TWI command type */
68 enum pmcmsptwi_cmd_type {
69 MSP_TWI_CMD_WRITE = 0, /* Write only */
70 MSP_TWI_CMD_READ = 1, /* Read only */
71 MSP_TWI_CMD_WRITE_READ = 2, /* Write then Read */
72 };
73
74 /* The possible results of the xferCmd */
75 enum pmcmsptwi_xfer_result {
76 MSP_TWI_XFER_OK = 0,
77 MSP_TWI_XFER_TIMEOUT,
78 MSP_TWI_XFER_BUSY,
79 MSP_TWI_XFER_DATA_COLLISION,
80 MSP_TWI_XFER_NO_RESPONSE,
81 MSP_TWI_XFER_LOST_ARBITRATION,
82 };
83
84 /* Corresponds to a PMCTWI clock configuration register */
85 struct pmcmsptwi_clock {
86 u8 filter; /* Bits 15:12, default = 0x03 */
87 u16 clock; /* Bits 9:0, default = 0x001f */
88 };
89
90 struct pmcmsptwi_clockcfg {
91 struct pmcmsptwi_clock standard; /* The standard/fast clock config */
92 struct pmcmsptwi_clock highspeed; /* The highspeed clock config */
93 };
94
95 /* Corresponds to the main TWI configuration register */
96 struct pmcmsptwi_cfg {
97 u8 arbf; /* Bits 15:12, default=0x03 */
98 u8 nak; /* Bits 11:8, default=0x03 */
99 u8 add10; /* Bit 7, default=0x00 */
100 u8 mst_code; /* Bits 6:4, default=0x00 */
101 u8 arb; /* Bit 1, default=0x01 */
102 u8 highspeed; /* Bit 0, default=0x00 */
103 };
104
105 /* A single pmctwi command to issue */
106 struct pmcmsptwi_cmd {
107 u16 addr; /* The slave address (7 or 10 bits) */
108 enum pmcmsptwi_cmd_type type; /* The command type */
109 u8 write_len; /* Number of bytes in the write buffer */
110 u8 read_len; /* Number of bytes in the read buffer */
111 u8 *write_data; /* Buffer of characters to send */
112 u8 *read_data; /* Buffer to fill with incoming data */
113 };
114
115 /* The private data */
116 struct pmcmsptwi_data {
117 void __iomem *iobase; /* iomapped base for IO */
118 int irq; /* IRQ to use (0 disables) */
119 struct completion wait; /* Completion for xfer */
120 struct mutex lock; /* Used for threadsafeness */
121 enum pmcmsptwi_xfer_result last_result; /* result of last xfer */
122 };
123
124 /* The default settings */
125 <<<<<<< HEAD:drivers/i2c/busses/i2c-pmcmsp.c
126 const static struct pmcmsptwi_clockcfg pmcmsptwi_defclockcfg = {
127 =======
128 static const struct pmcmsptwi_clockcfg pmcmsptwi_defclockcfg = {
129 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pmcmsp.c
130 .standard = {
131 .filter = 0x3,
132 .clock = 0x1f,
133 },
134 .highspeed = {
135 .filter = 0x3,
136 .clock = 0x1f,
137 },
138 };
139
140 <<<<<<< HEAD:drivers/i2c/busses/i2c-pmcmsp.c
141 const static struct pmcmsptwi_cfg pmcmsptwi_defcfg = {
142 =======
143 static const struct pmcmsptwi_cfg pmcmsptwi_defcfg = {
144 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:drivers/i2c/busses/i2c-pmcmsp.c
145 .arbf = 0x03,
146 .nak = 0x03,
147 .add10 = 0x00,
148 .mst_code = 0x00,
149 .arb = 0x01,
150 .highspeed = 0x00,
151 };
152
153 static struct pmcmsptwi_data pmcmsptwi_data;
154
155 static struct i2c_adapter pmcmsptwi_adapter;
156
157 /* inline helper functions */
158 static inline u32 pmcmsptwi_clock_to_reg(
159 const struct pmcmsptwi_clock *clock)
160 {
161 return ((clock->filter & 0xf) << 12) | (clock->clock & 0x03ff);
162 }
163
164 static inline void pmcmsptwi_reg_to_clock(
165 u32 reg, struct pmcmsptwi_clock *clock)
166 {
167 clock->filter = (reg >> 12) & 0xf;
168 clock->clock = reg & 0x03ff;
169 }
170
171 static inline u32 pmcmsptwi_cfg_to_reg(const struct pmcmsptwi_cfg *cfg)
172 {
173 return ((cfg->arbf & 0xf) << 12) |
174 ((cfg->nak & 0xf) << 8) |
175 ((cfg->add10 & 0x1) << 7) |
176 ((cfg->mst_code & 0x7) << 4) |
177 ((cfg->arb & 0x1) << 1) |
178 (cfg->highspeed & 0x1);
179 }
180
181 static inline void pmcmsptwi_reg_to_cfg(u32 reg, struct pmcmsptwi_cfg *cfg)
182 {
183 cfg->arbf = (reg >> 12) & 0xf;
184 cfg->nak = (reg >> 8) & 0xf;
185 cfg->add10 = (reg >> 7) & 0x1;
186 cfg->mst_code = (reg >> 4) & 0x7;
187 cfg->arb = (reg >> 1) & 0x1;
188 cfg->highspeed = reg & 0x1;
189 }
190
191 /*
192 * Sets the current clock configuration
193 */
194 static void pmcmsptwi_set_clock_config(const struct pmcmsptwi_clockcfg *cfg,
195 struct pmcmsptwi_data *data)
196 {
197 mutex_lock(&data->lock);
198 pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->standard),
199 data->iobase + MSP_TWI_SF_CLK_REG_OFFSET);
200 pmcmsptwi_writel(pmcmsptwi_clock_to_reg(&cfg->highspeed),
201 data->iobase + MSP_TWI_HS_CLK_REG_OFFSET);
202 mutex_unlock(&data->lock);
203 }
204
205 /*
206 * Gets the current TWI bus configuration
207 */
208 static void pmcmsptwi_get_twi_config(struct pmcmsptwi_cfg *cfg,
209 struct pmcmsptwi_data *data)
210 {
211 mutex_lock(&data->lock);
212 pmcmsptwi_reg_to_cfg(pmcmsptwi_readl(
213 data->iobase + MSP_TWI_CFG_REG_OFFSET), cfg);
214 mutex_unlock(&data->lock);
215 }
216
217 /*
218 * Sets the current TWI bus configuration
219 */
220 static void pmcmsptwi_set_twi_config(const struct pmcmsptwi_cfg *cfg,
221 struct pmcmsptwi_data *data)
222 {
223 mutex_lock(&data->lock);
224 pmcmsptwi_writel(pmcmsptwi_cfg_to_reg(cfg),
225 data->iobase + MSP_TWI_CFG_REG_OFFSET);
226 mutex_unlock(&data->lock);
227 }
228
229 /*
230 * Parses the 'int_sts' register and returns a well-defined error code
231 */
232 static enum pmcmsptwi_xfer_result pmcmsptwi_get_result(u32 reg)
233 {
234 if (reg & MSP_TWI_INT_STS_LOST_ARBITRATION) {
235 dev_dbg(&pmcmsptwi_adapter.dev,
236 "Result: Lost arbitration\n");
237 return MSP_TWI_XFER_LOST_ARBITRATION;
238 } else if (reg & MSP_TWI_INT_STS_NO_RESPONSE) {
239 dev_dbg(&pmcmsptwi_adapter.dev,
240 "Result: No response\n");
241 return MSP_TWI_XFER_NO_RESPONSE;
242 } else if (reg & MSP_TWI_INT_STS_DATA_COLLISION) {
243 dev_dbg(&pmcmsptwi_adapter.dev,
244 "Result: Data collision\n");
245 return MSP_TWI_XFER_DATA_COLLISION;
246 } else if (reg & MSP_TWI_INT_STS_BUSY) {
247 dev_dbg(&pmcmsptwi_adapter.dev,
248 "Result: Bus busy\n");
249 return MSP_TWI_XFER_BUSY;
250 }
251
252 dev_dbg(&pmcmsptwi_adapter.dev, "Result: Operation succeeded\n");
253 return MSP_TWI_XFER_OK;
254 }
255
256 /*
257 * In interrupt mode, handle the interrupt.
258 * NOTE: Assumes data->lock is held.
259 */
260 static irqreturn_t pmcmsptwi_interrupt(int irq, void *ptr)
261 {
262 struct pmcmsptwi_data *data = ptr;
263
264 u32 reason = pmcmsptwi_readl(data->iobase +
265 MSP_TWI_INT_STS_REG_OFFSET);
266 pmcmsptwi_writel(reason, data->iobase + MSP_TWI_INT_STS_REG_OFFSET);
267
268 dev_dbg(&pmcmsptwi_adapter.dev, "Got interrupt 0x%08x\n", reason);
269 if (!(reason & MSP_TWI_INT_STS_DONE))
270 return IRQ_NONE;
271
272 data->last_result = pmcmsptwi_get_result(reason);
273 complete(&data->wait);
274
275 return IRQ_HANDLED;
276 }
277
278 /*
279 * Probe for and register the device and return 0 if there is one.
280 */
281 static int __devinit pmcmsptwi_probe(struct platform_device *pldev)
282 {
283 struct resource *res;
284 int rc = -ENODEV;
285
286 /* get the static platform resources */
287 res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
288 if (!res) {
289 dev_err(&pldev->dev, "IOMEM resource not found\n");
290 goto ret_err;
291 }
292
293 /* reserve the memory region */
294 if (!request_mem_region(res->start, res->end - res->start + 1,
295 pldev->name)) {
296 dev_err(&pldev->dev,
297 "Unable to get memory/io address region 0x%08x\n",
298 res->start);
299 rc = -EBUSY;
300 goto ret_err;
301 }
302
303 /* remap the memory */
304 pmcmsptwi_data.iobase = ioremap_nocache(res->start,
305 res->end - res->start + 1);
306 if (!pmcmsptwi_data.iobase) {
307 dev_err(&pldev->dev,
308 "Unable to ioremap address 0x%08x\n", res->start);
309 rc = -EIO;
310 goto ret_unreserve;
311 }
312
313 /* request the irq */
314 pmcmsptwi_data.irq = platform_get_irq(pldev, 0);
315 if (pmcmsptwi_data.irq) {
316 rc = request_irq(pmcmsptwi_data.irq, &pmcmsptwi_interrupt,
317 IRQF_SHARED | IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
318 pldev->name, &pmcmsptwi_data);
319 if (rc == 0) {
320 /*
321 * Enable 'DONE' interrupt only.
322 *
323 * If you enable all interrupts, you will get one on
324 * error and another when the operation completes.
325 * This way you only have to handle one interrupt,
326 * but you can still check all result flags.
327 */
328 pmcmsptwi_writel(MSP_TWI_INT_STS_DONE,
329 pmcmsptwi_data.iobase +
330 MSP_TWI_INT_MSK_REG_OFFSET);
331 } else {
332 dev_warn(&pldev->dev,
333 "Could not assign TWI IRQ handler "
334 "to irq %d (continuing with poll)\n",
335 pmcmsptwi_data.irq);
336 pmcmsptwi_data.irq = 0;
337 }
338 }
339
340 init_completion(&pmcmsptwi_data.wait);
341 mutex_init(&pmcmsptwi_data.lock);
342
343 pmcmsptwi_set_clock_config(&pmcmsptwi_defclockcfg, &pmcmsptwi_data);
344 pmcmsptwi_set_twi_config(&pmcmsptwi_defcfg, &pmcmsptwi_data);
345
346 printk(KERN_INFO DRV_NAME ": Registering MSP71xx I2C adapter\n");
347
348 pmcmsptwi_adapter.dev.parent = &pldev->dev;
349 platform_set_drvdata(pldev, &pmcmsptwi_adapter);
350 i2c_set_adapdata(&pmcmsptwi_adapter, &pmcmsptwi_data);
351
352 rc = i2c_add_adapter(&pmcmsptwi_adapter);
353 if (rc) {
354 dev_err(&pldev->dev, "Unable to register I2C adapter\n");
355 goto ret_unmap;
356 }
357
358 return 0;
359
360 ret_unmap:
361 platform_set_drvdata(pldev, NULL);
362 if (pmcmsptwi_data.irq) {
363 pmcmsptwi_writel(0,
364 pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
365 free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
366 }
367
368 iounmap(pmcmsptwi_data.iobase);
369
370 ret_unreserve:
371 release_mem_region(res->start, res->end - res->start + 1);
372
373 ret_err:
374 return rc;
375 }
376
377 /*
378 * Release the device and return 0 if there is one.
379 */
380 static int __devexit pmcmsptwi_remove(struct platform_device *pldev)
381 {
382 struct resource *res;
383
384 i2c_del_adapter(&pmcmsptwi_adapter);
385
386 platform_set_drvdata(pldev, NULL);
387 if (pmcmsptwi_data.irq) {
388 pmcmsptwi_writel(0,
389 pmcmsptwi_data.iobase + MSP_TWI_INT_MSK_REG_OFFSET);
390 free_irq(pmcmsptwi_data.irq, &pmcmsptwi_data);
391 }
392
393 iounmap(pmcmsptwi_data.iobase);
394
395 res = platform_get_resource(pldev, IORESOURCE_MEM, 0);
396 release_mem_region(res->start, res->end - res->start + 1);
397
398 return 0;
399 }
400
401 /*
402 * Polls the 'busy' register until the command is complete.
403 * NOTE: Assumes data->lock is held.
404 */
405 static void pmcmsptwi_poll_complete(struct pmcmsptwi_data *data)
406 {
407 int i;
408
409 for (i = 0; i < MSP_MAX_POLL; i++) {
410 u32 val = pmcmsptwi_readl(data->iobase +
411 MSP_TWI_BUSY_REG_OFFSET);
412 if (val == 0) {
413 u32 reason = pmcmsptwi_readl(data->iobase +
414 MSP_TWI_INT_STS_REG_OFFSET);
415 pmcmsptwi_writel(reason, data->iobase +
416 MSP_TWI_INT_STS_REG_OFFSET);
417 data->last_result = pmcmsptwi_get_result(reason);
418 return;
419 }
420 udelay(MSP_POLL_DELAY);
421 }
422
423 dev_dbg(&pmcmsptwi_adapter.dev, "Result: Poll timeout\n");
424 data->last_result = MSP_TWI_XFER_TIMEOUT;
425 }
426
427 /*
428 * Do the transfer (low level):
429 * May use interrupt-driven or polling, depending on if an IRQ is
430 * presently registered.
431 * NOTE: Assumes data->lock is held.
432 */
433 static enum pmcmsptwi_xfer_result pmcmsptwi_do_xfer(
434 u32 reg, struct pmcmsptwi_data *data)
435 {
436 dev_dbg(&pmcmsptwi_adapter.dev, "Writing cmd reg 0x%08x\n", reg);
437 pmcmsptwi_writel(reg, data->iobase + MSP_TWI_CMD_REG_OFFSET);
438 if (data->irq) {
439 unsigned long timeleft = wait_for_completion_timeout(
440 &data->wait, MSP_IRQ_TIMEOUT);
441 if (timeleft == 0) {
442 dev_dbg(&pmcmsptwi_adapter.dev,
443 "Result: IRQ timeout\n");
444 complete(&data->wait);
445 data->last_result = MSP_TWI_XFER_TIMEOUT;
446 }
447 } else
448 pmcmsptwi_poll_complete(data);
449
450 return data->last_result;
451 }
452
453 /*
454 * Helper routine, converts 'pmctwi_cmd' struct to register format
455 */
456 static inline u32 pmcmsptwi_cmd_to_reg(const struct pmcmsptwi_cmd *cmd)
457 {
458 return ((cmd->type & 0x3) << 8) |
459 (((cmd->write_len - 1) & 0x7) << 4) |
460 ((cmd->read_len - 1) & 0x7);
461 }
462
463 /*
464 * Do the transfer (high level)
465 */
466 static enum pmcmsptwi_xfer_result pmcmsptwi_xfer_cmd(
467 struct pmcmsptwi_cmd *cmd,
468 struct pmcmsptwi_data *data)
469 {
470 enum pmcmsptwi_xfer_result retval;
471
472 if ((cmd->type == MSP_TWI_CMD_WRITE && cmd->write_len == 0) ||
473 (cmd->type == MSP_TWI_CMD_READ && cmd->read_len == 0) ||
474 (cmd->type == MSP_TWI_CMD_WRITE_READ &&
475 (cmd->read_len == 0 || cmd->write_len == 0))) {
476 dev_err(&pmcmsptwi_adapter.dev,
477 "%s: Cannot transfer less than 1 byte\n",
478 __FUNCTION__);
479 return -EINVAL;
480 }
481
482 if (cmd->read_len > MSP_MAX_BYTES_PER_RW ||
483 cmd->write_len > MSP_MAX_BYTES_PER_RW) {
484 dev_err(&pmcmsptwi_adapter.dev,
485 "%s: Cannot transfer more than %d bytes\n",
486 __FUNCTION__, MSP_MAX_BYTES_PER_RW);
487 return -EINVAL;
488 }
489
490 mutex_lock(&data->lock);
491 dev_dbg(&pmcmsptwi_adapter.dev,
492 "Setting address to 0x%04x\n", cmd->addr);
493 pmcmsptwi_writel(cmd->addr, data->iobase + MSP_TWI_ADD_REG_OFFSET);
494
495 if (cmd->type == MSP_TWI_CMD_WRITE ||
496 cmd->type == MSP_TWI_CMD_WRITE_READ) {
497 __be64 tmp = cpu_to_be64p((u64 *)cmd->write_data);
498 tmp >>= (MSP_MAX_BYTES_PER_RW - cmd->write_len) * 8;
499 dev_dbg(&pmcmsptwi_adapter.dev, "Writing 0x%016llx\n", tmp);
500 pmcmsptwi_writel(tmp & 0x00000000ffffffffLL,
501 data->iobase + MSP_TWI_DAT_0_REG_OFFSET);
502 if (cmd->write_len > 4)
503 pmcmsptwi_writel(tmp >> 32,
504 data->iobase + MSP_TWI_DAT_1_REG_OFFSET);
505 }
506
507 retval = pmcmsptwi_do_xfer(pmcmsptwi_cmd_to_reg(cmd), data);
508 if (retval != MSP_TWI_XFER_OK)
509 goto xfer_err;
510
511 if (cmd->type == MSP_TWI_CMD_READ ||
512 cmd->type == MSP_TWI_CMD_WRITE_READ) {
513 int i;
514 u64 rmsk = ~(0xffffffffffffffffLL << (cmd->read_len * 8));
515 u64 tmp = (u64)pmcmsptwi_readl(data->iobase +
516 MSP_TWI_DAT_0_REG_OFFSET);
517 if (cmd->read_len > 4)
518 tmp |= (u64)pmcmsptwi_readl(data->iobase +
519 MSP_TWI_DAT_1_REG_OFFSET) << 32;
520 tmp &= rmsk;
521 dev_dbg(&pmcmsptwi_adapter.dev, "Read 0x%016llx\n", tmp);
522
523 for (i = 0; i < cmd->read_len; i++)
524 cmd->read_data[i] = tmp >> i;
525 }
526
527 xfer_err:
528 mutex_unlock(&data->lock);
529
530 return retval;
531 }
532
533 /* -- Algorithm functions -- */
534
535 /*
536 * Sends an i2c command out on the adapter
537 */
538 static int pmcmsptwi_master_xfer(struct i2c_adapter *adap,
539 struct i2c_msg *msg, int num)
540 {
541 struct pmcmsptwi_data *data = i2c_get_adapdata(adap);
542 struct pmcmsptwi_cmd cmd;
543 struct pmcmsptwi_cfg oldcfg, newcfg;
544 int ret;
545
546 if (num > 2) {
547 dev_dbg(&adap->dev, "%d messages unsupported\n", num);
548 return -EINVAL;
549 } else if (num == 2) {
550 /* Check for a dual write-then-read command */
551 struct i2c_msg *nextmsg = msg + 1;
552 if (!(msg->flags & I2C_M_RD) &&
553 (nextmsg->flags & I2C_M_RD) &&
554 msg->addr == nextmsg->addr) {
555 cmd.type = MSP_TWI_CMD_WRITE_READ;
556 cmd.write_len = msg->len;
557 cmd.write_data = msg->buf;
558 cmd.read_len = nextmsg->len;
559 cmd.read_data = nextmsg->buf;
560 } else {
561 dev_dbg(&adap->dev,
562 "Non write-read dual messages unsupported\n");
563 return -EINVAL;
564 }
565 } else if (msg->flags & I2C_M_RD) {
566 cmd.type = MSP_TWI_CMD_READ;
567 cmd.read_len = msg->len;
568 cmd.read_data = msg->buf;
569 cmd.write_len = 0;
570 cmd.write_data = NULL;
571 } else {
572 cmd.type = MSP_TWI_CMD_WRITE;
573 cmd.read_len = 0;
574 cmd.read_data = NULL;
575 cmd.write_len = msg->len;
576 cmd.write_data = msg->buf;
577 }
578
579 if (msg->len == 0) {
580 dev_err(&adap->dev, "Zero-byte messages unsupported\n");
581 return -EINVAL;
582 }
583
584 cmd.addr = msg->addr;
585
586 if (msg->flags & I2C_M_TEN) {
587 pmcmsptwi_get_twi_config(&newcfg, data);
588 memcpy(&oldcfg, &newcfg, sizeof(oldcfg));
589
590 /* Set the special 10-bit address flag */
591 newcfg.add10 = 1;
592
593 pmcmsptwi_set_twi_config(&newcfg, data);
594 }
595
596 /* Execute the command */
597 ret = pmcmsptwi_xfer_cmd(&cmd, data);
598
599 if (msg->flags & I2C_M_TEN)
600 pmcmsptwi_set_twi_config(&oldcfg, data);
601
602 dev_dbg(&adap->dev, "I2C %s of %d bytes %s\n",
603 (msg->flags & I2C_M_RD) ? "read" : "write", msg->len,
604 (ret == MSP_TWI_XFER_OK) ? "succeeded" : "failed");
605
606 if (ret != MSP_TWI_XFER_OK) {
607 /*
608 * TODO: We could potentially loop and retry in the case
609 * of MSP_TWI_XFER_TIMEOUT.
610 */
611 return -1;
612 }
613
614 return 0;
615 }
616
617 static u32 pmcmsptwi_i2c_func(struct i2c_adapter *adapter)
618 {
619 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR |
620 I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA |
621 I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_PROC_CALL;
622 }
623
624 /* -- Initialization -- */
625
626 static struct i2c_algorithm pmcmsptwi_algo = {
627 .master_xfer = pmcmsptwi_master_xfer,
628 .functionality = pmcmsptwi_i2c_func,
629 };
630
631 static struct i2c_adapter pmcmsptwi_adapter = {
632 .owner = THIS_MODULE,
633 .class = I2C_CLASS_HWMON,
634 .algo = &pmcmsptwi_algo,
635 .name = DRV_NAME,
636 };
637
638 static struct platform_driver pmcmsptwi_driver = {
639 .probe = pmcmsptwi_probe,
640 .remove = __devexit_p(pmcmsptwi_remove),
641 .driver = {
642 .name = DRV_NAME,
643 .owner = THIS_MODULE,
644 },
645 };
646
647 static int __init pmcmsptwi_init(void)
648 {
649 return platform_driver_register(&pmcmsptwi_driver);
650 }
651
652 static void __exit pmcmsptwi_exit(void)
653 {
654 platform_driver_unregister(&pmcmsptwi_driver);
655 }
656
657 MODULE_DESCRIPTION("PMC MSP TWI/SMBus/I2C driver");
658 MODULE_LICENSE("GPL");
659
660 module_init(pmcmsptwi_init);
661 module_exit(pmcmsptwi_exit);
WRT350N Kernel Patches