arch/mips/mm/pg-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2003, 04, 05 Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2007  Maciej W. Rozycki
   8  */
   9 #include <linux/init.h>
  10 #include <linux/kernel.h>
  11 #include <linux/sched.h>
  12 #include <linux/mm.h>
  13 #include <linux/module.h>
  14 #include <linux/proc_fs.h>
  15
  16 #include <asm/bugs.h>
  17 #include <asm/cacheops.h>
  18 #include <asm/inst.h>
  19 #include <asm/io.h>
  20 #include <asm/page.h>
  21 #include <asm/pgtable.h>
  22 #include <asm/prefetch.h>
  23 #include <asm/system.h>
  24 #include <asm/bootinfo.h>
  25 #include <asm/mipsregs.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/cpu.h>
  28 #include <asm/war.h>
  29
  30 #define half_scache_line_size() (cpu_scache_line_size() >> 1)
  31 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  32 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  33
  34
  35 /*
  36  * Maximum sizes:
  37  *
  38  * R4000 128 bytes S-cache:             0x58 bytes
  39  * R4600 v1.7:                          0x5c bytes
  40  * R4600 v2.0:                          0x60 bytes
  41  * With prefetching, 16 byte strides    0xa0 bytes
  42  */
  43
  44 static unsigned int clear_page_array[0x130 / 4];
  45
  46 void clear_page(void * page) __attribute__((alias("clear_page_array")));
  47
  48 EXPORT_SYMBOL(clear_page);
  49
  50 /*
  51  * Maximum sizes:
  52  *
  53  * R4000 128 bytes S-cache:             0x11c bytes
  54  * R4600 v1.7:                          0x080 bytes
  55  * R4600 v2.0:                          0x07c bytes
  56  * With prefetching, 16 byte strides    0x0b8 bytes
  57  */
  58 static unsigned int copy_page_array[0x148 / 4];
  59
  60 void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
  61
  62 EXPORT_SYMBOL(copy_page);
  63
  64 /*
  65  * This is suboptimal for 32-bit kernels; we assume that R10000 is only used
  66  * with 64-bit kernels.  The prefetch offsets have been experimentally tuned
  67  * an Origin 200.
  68  */
  69 <<<<<<< HEAD:arch/mips/mm/pg-r4k.c
  70 static int pref_offset_clear __initdata = 512;
  71 static int pref_offset_copy  __initdata = 256;
  72 =======
  73 static int pref_offset_clear __cpuinitdata = 512;
  74 static int pref_offset_copy  __cpuinitdata = 256;
  75 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/pg-r4k.c
  76
  77 <<<<<<< HEAD:arch/mips/mm/pg-r4k.c
  78 static unsigned int pref_src_mode __initdata;
  79 static unsigned int pref_dst_mode __initdata;
  80 =======
  81 static unsigned int pref_src_mode __cpuinitdata;
  82 static unsigned int pref_dst_mode __cpuinitdata;
  83 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/pg-r4k.c
  84
  85 <<<<<<< HEAD:arch/mips/mm/pg-r4k.c
  86 static int load_offset __initdata;
  87 static int store_offset __initdata;
  88 =======
  89 static int load_offset __cpuinitdata;
  90 static int store_offset __cpuinitdata;
  91 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/pg-r4k.c
  92
  93 <<<<<<< HEAD:arch/mips/mm/pg-r4k.c
  94 static unsigned int __initdata *dest, *epc;
  95 =======
  96 static unsigned int __cpuinitdata *dest, *epc;
  97 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/pg-r4k.c
  98
  99 static unsigned int instruction_pending;
 100 static union mips_instruction delayed_mi;
 101
 102 <<<<<<< HEAD:arch/mips/mm/pg-r4k.c
 103 static void __init emit_instruction(union mips_instruction mi)
 104 =======
 105 static void __cpuinit emit_instruction(union mips_instruction mi)
 106 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/pg-r4k.c
 107 {
 108         if (instruction_pending)
 109                 *epc++ = delayed_mi.word;
 110
 111         instruction_pending = 1;
 112         delayed_mi = mi;
 113 }
 114
 115 static inline void flush_delay_slot_or_nop(void)
 116 {
 117         if (instruction_pending) {
 118                 *epc++ = delayed_mi.word;
 119                 instruction_pending = 0;
 120                 return;
 121         }
 122
 123         *epc++ = 0;
 124 }
 125
 126 static inline unsigned int *label(void)
 127 {
 128         if (instruction_pending) {
 129                 *epc++ = delayed_mi.word;
 130                 instruction_pending = 0;
 131         }
 132
 133         return epc;
 134 }
 135
 136 static inline void build_insn_word(unsigned int word)
 137 {
 138         union mips_instruction mi;
 139
 140         mi.word          = word;
 141
 142         emit_instruction(mi);
 143 }
 144
 145 static inline void build_nop(void)
 146 {
 147         build_insn_word(0);                     /* nop */
 148 }
 149
 150 static inline void build_src_pref(int advance)
 151 {
 152         if (!(load_offset & (cpu_dcache_line_size() - 1)) && advance) {
 153                 union mips_instruction mi;
 154
 155                 mi.i_format.opcode     = pref_op;
 156                 mi.i_format.rs         = 5;             /* $a1 */
 157                 mi.i_format.rt         = pref_src_mode;
 158                 mi.i_format.simmediate = load_offset + advance;
 159
 160                 emit_instruction(mi);
 161         }
 162 }
 163
 164 static inline void __build_load_reg(int reg)
 165 {
 166         union mips_instruction mi;
 167         unsigned int width;
 168
 169         if (cpu_has_64bit_gp_regs) {
 170                 mi.i_format.opcode     = ld_op;
 171                 width = 8;
 172         } else {
 173                 mi.i_format.opcode     = lw_op;
 174                 width = 4;
 175         }
 176         mi.i_format.rs         = 5;             /* $a1 */
 177         mi.i_format.rt         = reg;           /* $reg */
 178         mi.i_format.simmediate = load_offset;
 179
 180         load_offset += width;
 181         emit_instruction(mi);
 182 }
 183
 184 static inline void build_load_reg(int reg)
 185 {
 186         if (cpu_has_prefetch)
 187                 build_src_pref(pref_offset_copy);
 188
 189         __build_load_reg(reg);
 190 }
 191
 192 static inline void build_dst_pref(int advance)
 193 {
 194         if (!(store_offset & (cpu_dcache_line_size() - 1)) && advance) {
 195                 union mips_instruction mi;
 196
 197                 mi.i_format.opcode     = pref_op;
 198                 mi.i_format.rs         = 4;             /* $a0 */
 199                 mi.i_format.rt         = pref_dst_mode;
 200                 mi.i_format.simmediate = store_offset + advance;
 201
 202                 emit_instruction(mi);
 203         }
 204 }
 205
 206 static inline void build_cdex_s(void)
 207 {
 208         union mips_instruction mi;
 209
 210         if ((store_offset & (cpu_scache_line_size() - 1)))
 211                 return;
 212
 213         mi.c_format.opcode     = cache_op;
 214         mi.c_format.rs         = 4;             /* $a0 */
 215         mi.c_format.c_op       = 3;             /* Create Dirty Exclusive */
 216         mi.c_format.cache      = 3;             /* Secondary Data Cache */
 217         mi.c_format.simmediate = store_offset;
 218
 219         emit_instruction(mi);
 220 }
 221
 222 static inline void build_cdex_p(void)
 223 {
 224         union mips_instruction mi;
 225
 226         if (store_offset & (cpu_dcache_line_size() - 1))
 227                 return;
 228
 229         if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
 230                 build_nop();
 231                 build_nop();
 232                 build_nop();
 233                 build_nop();
 234         }
 235
 236         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
 237                 build_insn_word(0x8c200000);    /* lw      $zero, ($at) */
 238
 239         mi.c_format.opcode     = cache_op;
 240         mi.c_format.rs         = 4;             /* $a0 */
 241         mi.c_format.c_op       = 3;             /* Create Dirty Exclusive */
 242         mi.c_format.cache      = 1;             /* Data Cache */
 243         mi.c_format.simmediate = store_offset;
 244
 245         emit_instruction(mi);
 246 }
 247
 248 <<<<<<< HEAD:arch/mips/mm/pg-r4k.c
 249 static void __init __build_store_reg(int reg)
 250 =======
 251 static void __cpuinit __build_store_reg(int reg)
 252 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/pg-r4k.c
 253 {
 254         union mips_instruction mi;
 255         unsigned int width;
 256
 257         if (cpu_has_64bit_gp_regs ||
 258             (cpu_has_64bit_zero_reg && reg == 0)) {
 259                 mi.i_format.opcode     = sd_op;
 260                 width = 8;
 261         } else {
 262                 mi.i_format.opcode     = sw_op;
 263                 width = 4;
 264         }
 265         mi.i_format.rs         = 4;             /* $a0 */
 266         mi.i_format.rt         = reg;           /* $reg */
 267         mi.i_format.simmediate = store_offset;
 268
 269         store_offset += width;
 270         emit_instruction(mi);
 271 }
 272
 273 static inline void build_store_reg(int reg)
 274 {
 275         int pref_off = cpu_has_prefetch ?
 276                 (reg ? pref_offset_copy : pref_offset_clear) : 0;
 277         if (pref_off)
 278                 build_dst_pref(pref_off);
 279         else if (cpu_has_cache_cdex_s)
 280                 build_cdex_s();
 281         else if (cpu_has_cache_cdex_p)
 282                 build_cdex_p();
 283
 284         __build_store_reg(reg);
 285 }
 286
 287 static inline void build_addiu_rt_rs(unsigned int rt, unsigned int rs,
 288                                      unsigned long offset)
 289 {
 290         union mips_instruction mi;
 291
 292         BUG_ON(offset > 0x7fff);
 293
 294         if (cpu_has_64bit_gp_regs && DADDI_WAR && r4k_daddiu_bug()) {
 295                 mi.i_format.opcode     = addiu_op;
 296                 mi.i_format.rs         = 0;     /* $zero */
 297                 mi.i_format.rt         = 25;    /* $t9 */
 298                 mi.i_format.simmediate = offset;
 299                 emit_instruction(mi);
 300
 301                 mi.r_format.opcode     = spec_op;
 302                 mi.r_format.rs         = rs;
 303                 mi.r_format.rt         = 25;    /* $t9 */
 304                 mi.r_format.rd         = rt;
 305                 mi.r_format.re         = 0;
 306                 mi.r_format.func       = daddu_op;
 307         } else {
 308                 mi.i_format.opcode     = cpu_has_64bit_gp_regs ?
 309                                          daddiu_op : addiu_op;
 310                 mi.i_format.rs         = rs;
 311                 mi.i_format.rt         = rt;
 312                 mi.i_format.simmediate = offset;
 313         }
 314         emit_instruction(mi);
 315 }
 316
 317 static inline void build_addiu_a2_a0(unsigned long offset)
 318 {
 319         build_addiu_rt_rs(6, 4, offset);        /* $a2, $a0, offset */
 320 }
 321
 322 static inline void build_addiu_a2(unsigned long offset)
 323 {
 324         build_addiu_rt_rs(6, 6, offset);        /* $a2, $a2, offset */
 325 }
 326
 327 static inline void build_addiu_a1(unsigned long offset)
 328 {
 329         build_addiu_rt_rs(5, 5, offset);        /* $a1, $a1, offset */
 330
 331         load_offset -= offset;
 332 }
 333
 334 static inline void build_addiu_a0(unsigned long offset)
 335 {
 336         build_addiu_rt_rs(4, 4, offset);        /* $a0, $a0, offset */
 337
 338         store_offset -= offset;
 339 }
 340
 341 static inline void build_bne(unsigned int *dest)
 342 {
 343         union mips_instruction mi;
 344
 345         mi.i_format.opcode = bne_op;
 346         mi.i_format.rs     = 6;                 /* $a2 */
 347         mi.i_format.rt     = 4;                 /* $a0 */
 348         mi.i_format.simmediate = dest - epc - 1;
 349
 350         *epc++ = mi.word;
 351         flush_delay_slot_or_nop();
 352 }
 353
 354 static inline void build_jr_ra(void)
 355 {
 356         union mips_instruction mi;
 357
 358         mi.r_format.opcode = spec_op;
 359         mi.r_format.rs     = 31;
 360         mi.r_format.rt     = 0;
 361         mi.r_format.rd     = 0;
 362         mi.r_format.re     = 0;
 363         mi.r_format.func   = jr_op;
 364
 365         *epc++ = mi.word;
 366         flush_delay_slot_or_nop();
 367 }
 368
 369 <<<<<<< HEAD:arch/mips/mm/pg-r4k.c
 370 void __init build_clear_page(void)
 371 =======
 372 void __cpuinit build_clear_page(void)
 373 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/pg-r4k.c
 374 {
 375         unsigned int loop_start;
 376         unsigned long off;
 377         int i;
 378
 379         epc = (unsigned int *) &clear_page_array;
 380         instruction_pending = 0;
 381         store_offset = 0;
 382
 383         if (cpu_has_prefetch) {
 384                 switch (current_cpu_type()) {
 385                 case CPU_TX49XX:
 386                         /* TX49 supports only Pref_Load */
 387                         pref_offset_clear = 0;
 388                         pref_offset_copy = 0;
 389                         break;
 390
 391                 case CPU_RM9000:
 392                         /*
 393                          * As a workaround for erratum G105 which make the
 394                          * PrepareForStore hint unusable we fall back to
 395                          * StoreRetained on the RM9000.  Once it is known which
 396                          * versions of the RM9000 we'll be able to condition-
 397                          * alize this.
 398                          */
 399
 400                 case CPU_R10000:
 401                 case CPU_R12000:
 402                 case CPU_R14000:
 403                         pref_src_mode = Pref_LoadStreamed;
 404                         pref_dst_mode = Pref_StoreStreamed;
 405                         break;
 406
 407                 default:
 408                         pref_src_mode = Pref_LoadStreamed;
 409                         pref_dst_mode = Pref_PrepareForStore;
 410                         break;
 411                 }
 412         }
 413
 414         off = PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0);
 415         if (off > 0x7fff) {
 416                 build_addiu_a2_a0(off >> 1);
 417                 build_addiu_a2(off >> 1);
 418         } else
 419                 build_addiu_a2_a0(off);
 420
 421         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
 422                 build_insn_word(0x3c01a000);    /* lui     $at, 0xa000  */
 423
 424 dest = label();
 425         do {
 426                 build_store_reg(0);
 427                 build_store_reg(0);
 428                 build_store_reg(0);
 429                 build_store_reg(0);
 430         } while (store_offset < half_scache_line_size());
 431         build_addiu_a0(2 * store_offset);
 432         loop_start = store_offset;
 433         do {
 434                 build_store_reg(0);
 435                 build_store_reg(0);
 436                 build_store_reg(0);
 437                 build_store_reg(0);
 438         } while ((store_offset - loop_start) < half_scache_line_size());
 439         build_bne(dest);
 440
 441         if (cpu_has_prefetch && pref_offset_clear) {
 442                 build_addiu_a2_a0(pref_offset_clear);
 443         dest = label();
 444                 loop_start = store_offset;
 445                 do {
 446                         __build_store_reg(0);
 447                         __build_store_reg(0);
 448                         __build_store_reg(0);
 449                         __build_store_reg(0);
 450                 } while ((store_offset - loop_start) < half_scache_line_size());
 451                 build_addiu_a0(2 * store_offset);
 452                 loop_start = store_offset;
 453                 do {
 454                         __build_store_reg(0);
 455                         __build_store_reg(0);
 456                         __build_store_reg(0);
 457                         __build_store_reg(0);
 458                 } while ((store_offset - loop_start) < half_scache_line_size());
 459                 build_bne(dest);
 460         }
 461
 462         build_jr_ra();
 463
 464         BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
 465
 466         pr_info("Synthesized clear page handler (%u instructions).\n",
 467                 (unsigned int)(epc - clear_page_array));
 468
 469         pr_debug("\t.set push\n");
 470         pr_debug("\t.set noreorder\n");
 471         for (i = 0; i < (epc - clear_page_array); i++)
 472                 pr_debug("\t.word 0x%08x\n", clear_page_array[i]);
 473         pr_debug("\t.set pop\n");
 474 }
 475
 476 <<<<<<< HEAD:arch/mips/mm/pg-r4k.c
 477 void __init build_copy_page(void)
 478 =======
 479 void __cpuinit build_copy_page(void)
 480 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/pg-r4k.c
 481 {
 482         unsigned int loop_start;
 483         unsigned long off;
 484         int i;
 485
 486         epc = (unsigned int *) &copy_page_array;
 487         store_offset = load_offset = 0;
 488         instruction_pending = 0;
 489
 490         off = PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0);
 491         if (off > 0x7fff) {
 492                 build_addiu_a2_a0(off >> 1);
 493                 build_addiu_a2(off >> 1);
 494         } else
 495                 build_addiu_a2_a0(off);
 496
 497         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())
 498                 build_insn_word(0x3c01a000);    /* lui     $at, 0xa000  */
 499
 500 dest = label();
 501         loop_start = store_offset;
 502         do {
 503                 build_load_reg( 8);
 504                 build_load_reg( 9);
 505                 build_load_reg(10);
 506                 build_load_reg(11);
 507                 build_store_reg( 8);
 508                 build_store_reg( 9);
 509                 build_store_reg(10);
 510                 build_store_reg(11);
 511         } while ((store_offset - loop_start) < half_scache_line_size());
 512         build_addiu_a0(2 * store_offset);
 513         build_addiu_a1(2 * load_offset);
 514         loop_start = store_offset;
 515         do {
 516                 build_load_reg( 8);
 517                 build_load_reg( 9);
 518                 build_load_reg(10);
 519                 build_load_reg(11);
 520                 build_store_reg( 8);
 521                 build_store_reg( 9);
 522                 build_store_reg(10);
 523                 build_store_reg(11);
 524         } while ((store_offset - loop_start) < half_scache_line_size());
 525         build_bne(dest);
 526
 527         if (cpu_has_prefetch && pref_offset_copy) {
 528                 build_addiu_a2_a0(pref_offset_copy);
 529         dest = label();
 530                 loop_start = store_offset;
 531                 do {
 532                         __build_load_reg( 8);
 533                         __build_load_reg( 9);
 534                         __build_load_reg(10);
 535                         __build_load_reg(11);
 536                         __build_store_reg( 8);
 537                         __build_store_reg( 9);
 538                         __build_store_reg(10);
 539                         __build_store_reg(11);
 540                 } while ((store_offset - loop_start) < half_scache_line_size());
 541                 build_addiu_a0(2 * store_offset);
 542                 build_addiu_a1(2 * load_offset);
 543                 loop_start = store_offset;
 544                 do {
 545                         __build_load_reg( 8);
 546                         __build_load_reg( 9);
 547                         __build_load_reg(10);
 548                         __build_load_reg(11);
 549                         __build_store_reg( 8);
 550                         __build_store_reg( 9);
 551                         __build_store_reg(10);
 552                         __build_store_reg(11);
 553                 } while ((store_offset - loop_start) < half_scache_line_size());
 554                 build_bne(dest);
 555         }
 556
 557         build_jr_ra();
 558
 559         BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));
 560
 561         pr_info("Synthesized copy page handler (%u instructions).\n",
 562                 (unsigned int)(epc - copy_page_array));
 563
 564         pr_debug("\t.set push\n");
 565         pr_debug("\t.set noreorder\n");
 566         for (i = 0; i < (epc - copy_page_array); i++)
 567                 pr_debug("\t.word 0x%08x\n", copy_page_array[i]);
 568         pr_debug("\t.set pop\n");
 569 }