arch/mips/mm/cache.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 - 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
   7  * Copyright (C) 2007 MIPS Technologies, Inc.
   8  */
   9 #include <linux/fs.h>
  10 #include <linux/fcntl.h>
  11 #include <linux/init.h>
  12 #include <linux/kernel.h>
  13 #include <linux/linkage.h>
  14 #include <linux/module.h>
  15 #include <linux/sched.h>
  16 #include <linux/mm.h>
  17
  18 #include <asm/cacheflush.h>
  19 #include <asm/processor.h>
  20 #include <asm/cpu.h>
  21 #include <asm/cpu-features.h>
  22
  23 /* Cache operations. */
  24 void (*flush_cache_all)(void);
  25 void (*__flush_cache_all)(void);
  26 void (*flush_cache_mm)(struct mm_struct *mm);
  27 void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start,
  28         unsigned long end);
  29 void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page,
  30         unsigned long pfn);
  31 void (*flush_icache_range)(unsigned long start, unsigned long end);
  32
  33 /* MIPS specific cache operations */
  34 void (*flush_cache_sigtramp)(unsigned long addr);
  35 void (*local_flush_data_cache_page)(void * addr);
  36 void (*flush_data_cache_page)(unsigned long addr);
  37 void (*flush_icache_all)(void);
  38
  39 EXPORT_SYMBOL_GPL(local_flush_data_cache_page);
  40 EXPORT_SYMBOL(flush_data_cache_page);
  41
  42 #ifdef CONFIG_DMA_NONCOHERENT
  43
  44 /* DMA cache operations. */
  45 void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
  46 void (*_dma_cache_wback)(unsigned long start, unsigned long size);
  47 void (*_dma_cache_inv)(unsigned long start, unsigned long size);
  48
  49 EXPORT_SYMBOL(_dma_cache_wback_inv);
  50
  51 #endif /* CONFIG_DMA_NONCOHERENT */
  52
  53 /*
  54  * We could optimize the case where the cache argument is not BCACHE but
  55  * that seems very atypical use ...
  56  */
  57 asmlinkage int sys_cacheflush(unsigned long addr,
  58         unsigned long bytes, unsigned int cache)
  59 {
  60         if (bytes == 0)
  61                 return 0;
  62         if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
  63                 return -EFAULT;
  64
  65         flush_icache_range(addr, addr + bytes);
  66
  67         return 0;
  68 }
  69
  70 void __flush_dcache_page(struct page *page)
  71 {
  72         struct address_space *mapping = page_mapping(page);
  73         unsigned long addr;
  74
  75         if (PageHighMem(page))
  76                 return;
  77         if (mapping && !mapping_mapped(mapping)) {
  78                 SetPageDcacheDirty(page);
  79                 return;
  80         }
  81
  82         /*
  83          * We could delay the flush for the !page_mapping case too.  But that
  84          * case is for exec env/arg pages and those are %99 certainly going to
  85          * get faulted into the tlb (and thus flushed) anyways.
  86          */
  87         addr = (unsigned long) page_address(page);
  88         flush_data_cache_page(addr);
  89 }
  90
  91 EXPORT_SYMBOL(__flush_dcache_page);
  92
  93 void __flush_anon_page(struct page *page, unsigned long vmaddr)
  94 {
  95 <<<<<<< HEAD:arch/mips/mm/cache.c
  96         if (pages_do_alias((unsigned long)page_address(page), vmaddr)) {
  97                 void *kaddr;
  98 =======
  99         unsigned long addr = (unsigned long) page_address(page);
 100 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/cache.c
 101
 102 <<<<<<< HEAD:arch/mips/mm/cache.c
 103                 kaddr = kmap_coherent(page, vmaddr);
 104                 flush_data_cache_page((unsigned long)kaddr);
 105                 kunmap_coherent();
 106 =======
 107         if (pages_do_alias(addr, vmaddr)) {
 108                 if (page_mapped(page) && !Page_dcache_dirty(page)) {
 109                         void *kaddr;
 110
 111                         kaddr = kmap_coherent(page, vmaddr);
 112                         flush_data_cache_page((unsigned long)kaddr);
 113                         kunmap_coherent();
 114                 } else
 115                         flush_data_cache_page(addr);
 116 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/cache.c
 117         }
 118 }
 119
 120 EXPORT_SYMBOL(__flush_anon_page);
 121
 122 void __update_cache(struct vm_area_struct *vma, unsigned long address,
 123         pte_t pte)
 124 {
 125         struct page *page;
 126         unsigned long pfn, addr;
 127         int exec = (vma->vm_flags & VM_EXEC) && !cpu_has_ic_fills_f_dc;
 128
 129         pfn = pte_pfn(pte);
 130         if (unlikely(!pfn_valid(pfn)))
 131                 return;
 132         page = pfn_to_page(pfn);
 133         if (page_mapping(page) && Page_dcache_dirty(page)) {
 134                 addr = (unsigned long) page_address(page);
 135                 if (exec || pages_do_alias(addr, address & PAGE_MASK))
 136                         flush_data_cache_page(addr);
 137                 ClearPageDcacheDirty(page);
 138         }
 139 }
 140
 141 <<<<<<< HEAD:arch/mips/mm/cache.c
 142 static char cache_panic[] __initdata = "Yeee, unsupported cache architecture.";
 143 =======
 144 static char cache_panic[] __cpuinitdata =
 145         "Yeee, unsupported cache architecture.";
 146 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/cache.c
 147
 148 <<<<<<< HEAD:arch/mips/mm/cache.c
 149 void __init cpu_cache_init(void)
 150 =======
 151 void __devinit cpu_cache_init(void)
 152 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/mips/mm/cache.c
 153 {
 154         if (cpu_has_3k_cache) {
 155                 extern void __weak r3k_cache_init(void);
 156
 157                 r3k_cache_init();
 158                 return;
 159         }
 160         if (cpu_has_6k_cache) {
 161                 extern void __weak r6k_cache_init(void);
 162
 163                 r6k_cache_init();
 164                 return;
 165         }
 166         if (cpu_has_4k_cache) {
 167                 extern void __weak r4k_cache_init(void);
 168
 169                 r4k_cache_init();
 170                 return;
 171         }
 172         if (cpu_has_8k_cache) {
 173                 extern void __weak r8k_cache_init(void);
 174
 175                 r8k_cache_init();
 176                 return;
 177         }
 178         if (cpu_has_tx39_cache) {
 179                 extern void __weak tx39_cache_init(void);
 180
 181                 tx39_cache_init();
 182                 return;
 183         }
 184
 185         panic(cache_panic);
 186 }
 187
 188 int __weak __uncached_access(struct file *file, unsigned long addr)
 189 {
 190         if (file->f_flags & O_SYNC)
 191                 return 1;
 192
 193         return addr >= __pa(high_memory);
 194 }