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Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
[wrt350n-kernel.git] / arch / arm / plat-omap / gpio.c
blob9d74d5d17f120bb1173ed9d3d04a196ae77a335f
1 /*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
6 * Copyright (C) 2003-2005 Nokia Corporation
7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14 #include <linux/init.h>
15 #include <linux/module.h>
16 #include <linux/interrupt.h>
17 #include <linux/sysdev.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20
21 #include <asm/hardware.h>
22 #include <asm/irq.h>
23 #include <asm/arch/irqs.h>
24 #include <asm/arch/gpio.h>
25 #include <asm/mach/irq.h>
26
27 #include <asm/io.h>
28
29 /*
30 * OMAP1510 GPIO registers
31 */
32 #define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
33 #define OMAP1510_GPIO_DATA_INPUT 0x00
34 #define OMAP1510_GPIO_DATA_OUTPUT 0x04
35 #define OMAP1510_GPIO_DIR_CONTROL 0x08
36 #define OMAP1510_GPIO_INT_CONTROL 0x0c
37 #define OMAP1510_GPIO_INT_MASK 0x10
38 #define OMAP1510_GPIO_INT_STATUS 0x14
39 #define OMAP1510_GPIO_PIN_CONTROL 0x18
40
41 #define OMAP1510_IH_GPIO_BASE 64
42
43 /*
44 * OMAP1610 specific GPIO registers
45 */
46 #define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
47 #define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
48 #define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
49 #define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
50 #define OMAP1610_GPIO_REVISION 0x0000
51 #define OMAP1610_GPIO_SYSCONFIG 0x0010
52 #define OMAP1610_GPIO_SYSSTATUS 0x0014
53 #define OMAP1610_GPIO_IRQSTATUS1 0x0018
54 #define OMAP1610_GPIO_IRQENABLE1 0x001c
55 #define OMAP1610_GPIO_WAKEUPENABLE 0x0028
56 #define OMAP1610_GPIO_DATAIN 0x002c
57 #define OMAP1610_GPIO_DATAOUT 0x0030
58 #define OMAP1610_GPIO_DIRECTION 0x0034
59 #define OMAP1610_GPIO_EDGE_CTRL1 0x0038
60 #define OMAP1610_GPIO_EDGE_CTRL2 0x003c
61 #define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
62 #define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
63 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
64 #define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
65 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
66 #define OMAP1610_GPIO_SET_DATAOUT 0x00f0
67
68 /*
69 * OMAP730 specific GPIO registers
70 */
71 #define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
72 #define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
73 #define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
74 #define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
75 #define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
76 #define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
77 #define OMAP730_GPIO_DATA_INPUT 0x00
78 #define OMAP730_GPIO_DATA_OUTPUT 0x04
79 #define OMAP730_GPIO_DIR_CONTROL 0x08
80 #define OMAP730_GPIO_INT_CONTROL 0x0c
81 #define OMAP730_GPIO_INT_MASK 0x10
82 #define OMAP730_GPIO_INT_STATUS 0x14
83
84 /*
85 * omap24xx specific GPIO registers
86 */
87 #define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
88 #define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
89 #define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
90 #define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
91
92 #define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
93 #define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
94 #define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
95 #define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
96 #define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
97
98 #define OMAP24XX_GPIO_REVISION 0x0000
99 #define OMAP24XX_GPIO_SYSCONFIG 0x0010
100 #define OMAP24XX_GPIO_SYSSTATUS 0x0014
101 #define OMAP24XX_GPIO_IRQSTATUS1 0x0018
102 #define OMAP24XX_GPIO_IRQSTATUS2 0x0028
103 #define OMAP24XX_GPIO_IRQENABLE2 0x002c
104 #define OMAP24XX_GPIO_IRQENABLE1 0x001c
105 #define OMAP24XX_GPIO_CTRL 0x0030
106 #define OMAP24XX_GPIO_OE 0x0034
107 #define OMAP24XX_GPIO_DATAIN 0x0038
108 #define OMAP24XX_GPIO_DATAOUT 0x003c
109 #define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110 #define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111 #define OMAP24XX_GPIO_RISINGDETECT 0x0048
112 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
113 #define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114 #define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
115 #define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117 #define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118 #define OMAP24XX_GPIO_SETWKUENA 0x0084
119 #define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120 #define OMAP24XX_GPIO_SETDATAOUT 0x0094
121
122 /*
123 * omap34xx specific GPIO registers
124 */
125
126 #define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
127 #define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
128 #define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
129 #define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
130 #define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
131 #define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
132
133
134 struct gpio_bank {
135 void __iomem *base;
136 u16 irq;
137 u16 virtual_irq_start;
138 int method;
139 u32 reserved_map;
140 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
141 u32 suspend_wakeup;
142 u32 saved_wakeup;
143 #endif
144 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
147
148 u32 saved_datain;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
151 #endif
152 spinlock_t lock;
153 };
154
155 #define METHOD_MPUIO 0
156 #define METHOD_GPIO_1510 1
157 #define METHOD_GPIO_1610 2
158 #define METHOD_GPIO_730 3
159 #define METHOD_GPIO_24XX 4
160
161 #ifdef CONFIG_ARCH_OMAP16XX
162 static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
168 };
169 #endif
170
171 #ifdef CONFIG_ARCH_OMAP15XX
172 static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
175 };
176 #endif
177
178 #ifdef CONFIG_ARCH_OMAP730
179 static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
184 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
185 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
186 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
187 };
188 #endif
189
190 #ifdef CONFIG_ARCH_OMAP24XX
191
192 static struct gpio_bank gpio_bank_242x[4] = {
193 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
197 };
198
199 static struct gpio_bank gpio_bank_243x[5] = {
200 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
205 };
206
207 #endif
208
209 #ifdef CONFIG_ARCH_OMAP34XX
210 static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
217 };
218
219 #endif
220
221 static struct gpio_bank *gpio_bank;
222 static int gpio_bank_count;
223
224 static inline struct gpio_bank *get_gpio_bank(int gpio)
225 {
226 if (cpu_is_omap15xx()) {
227 if (OMAP_GPIO_IS_MPUIO(gpio))
228 return &gpio_bank[0];
229 return &gpio_bank[1];
230 }
231 if (cpu_is_omap16xx()) {
232 if (OMAP_GPIO_IS_MPUIO(gpio))
233 return &gpio_bank[0];
234 return &gpio_bank[1 + (gpio >> 4)];
235 }
236 if (cpu_is_omap730()) {
237 if (OMAP_GPIO_IS_MPUIO(gpio))
238 return &gpio_bank[0];
239 return &gpio_bank[1 + (gpio >> 5)];
240 }
241 if (cpu_is_omap24xx())
242 return &gpio_bank[gpio >> 5];
243 if (cpu_is_omap34xx())
244 return &gpio_bank[gpio >> 5];
245 }
246
247 static inline int get_gpio_index(int gpio)
248 {
249 if (cpu_is_omap730())
250 return gpio & 0x1f;
251 if (cpu_is_omap24xx())
252 return gpio & 0x1f;
253 if (cpu_is_omap34xx())
254 return gpio & 0x1f;
255 return gpio & 0x0f;
256 }
257
258 static inline int gpio_valid(int gpio)
259 {
260 if (gpio < 0)
261 return -1;
262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
263 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
264 return -1;
265 return 0;
266 }
267 if (cpu_is_omap15xx() && gpio < 16)
268 return 0;
269 if ((cpu_is_omap16xx()) && gpio < 64)
270 return 0;
271 if (cpu_is_omap730() && gpio < 192)
272 return 0;
273 if (cpu_is_omap24xx() && gpio < 128)
274 return 0;
275 if (cpu_is_omap34xx() && gpio < 160)
276 return 0;
277 return -1;
278 }
279
280 static int check_gpio(int gpio)
281 {
282 if (unlikely(gpio_valid(gpio)) < 0) {
283 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
284 dump_stack();
285 return -1;
286 }
287 return 0;
288 }
289
290 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
291 {
292 void __iomem *reg = bank->base;
293 u32 l;
294
295 switch (bank->method) {
296 #ifdef CONFIG_ARCH_OMAP1
297 case METHOD_MPUIO:
298 reg += OMAP_MPUIO_IO_CNTL;
299 break;
300 #endif
301 #ifdef CONFIG_ARCH_OMAP15XX
302 case METHOD_GPIO_1510:
303 reg += OMAP1510_GPIO_DIR_CONTROL;
304 break;
305 #endif
306 #ifdef CONFIG_ARCH_OMAP16XX
307 case METHOD_GPIO_1610:
308 reg += OMAP1610_GPIO_DIRECTION;
309 break;
310 #endif
311 #ifdef CONFIG_ARCH_OMAP730
312 case METHOD_GPIO_730:
313 reg += OMAP730_GPIO_DIR_CONTROL;
314 break;
315 #endif
316 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
317 case METHOD_GPIO_24XX:
318 reg += OMAP24XX_GPIO_OE;
319 break;
320 #endif
321 default:
322 WARN_ON(1);
323 return;
324 }
325 l = __raw_readl(reg);
326 if (is_input)
327 l |= 1 << gpio;
328 else
329 l &= ~(1 << gpio);
330 __raw_writel(l, reg);
331 }
332
333 void omap_set_gpio_direction(int gpio, int is_input)
334 {
335 struct gpio_bank *bank;
336 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
337 =======
338 unsigned long flags;
339 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
340
341 if (check_gpio(gpio) < 0)
342 return;
343 bank = get_gpio_bank(gpio);
344 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
345 spin_lock(&bank->lock);
346 =======
347 spin_lock_irqsave(&bank->lock, flags);
348 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
349 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
350 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
351 spin_unlock(&bank->lock);
352 =======
353 spin_unlock_irqrestore(&bank->lock, flags);
354 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
355 }
356
357 static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
358 {
359 void __iomem *reg = bank->base;
360 u32 l = 0;
361
362 switch (bank->method) {
363 #ifdef CONFIG_ARCH_OMAP1
364 case METHOD_MPUIO:
365 reg += OMAP_MPUIO_OUTPUT;
366 l = __raw_readl(reg);
367 if (enable)
368 l |= 1 << gpio;
369 else
370 l &= ~(1 << gpio);
371 break;
372 #endif
373 #ifdef CONFIG_ARCH_OMAP15XX
374 case METHOD_GPIO_1510:
375 reg += OMAP1510_GPIO_DATA_OUTPUT;
376 l = __raw_readl(reg);
377 if (enable)
378 l |= 1 << gpio;
379 else
380 l &= ~(1 << gpio);
381 break;
382 #endif
383 #ifdef CONFIG_ARCH_OMAP16XX
384 case METHOD_GPIO_1610:
385 if (enable)
386 reg += OMAP1610_GPIO_SET_DATAOUT;
387 else
388 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
389 l = 1 << gpio;
390 break;
391 #endif
392 #ifdef CONFIG_ARCH_OMAP730
393 case METHOD_GPIO_730:
394 reg += OMAP730_GPIO_DATA_OUTPUT;
395 l = __raw_readl(reg);
396 if (enable)
397 l |= 1 << gpio;
398 else
399 l &= ~(1 << gpio);
400 break;
401 #endif
402 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
403 case METHOD_GPIO_24XX:
404 if (enable)
405 reg += OMAP24XX_GPIO_SETDATAOUT;
406 else
407 reg += OMAP24XX_GPIO_CLEARDATAOUT;
408 l = 1 << gpio;
409 break;
410 #endif
411 default:
412 WARN_ON(1);
413 return;
414 }
415 __raw_writel(l, reg);
416 }
417
418 void omap_set_gpio_dataout(int gpio, int enable)
419 {
420 struct gpio_bank *bank;
421 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
422 =======
423 unsigned long flags;
424 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
425
426 if (check_gpio(gpio) < 0)
427 return;
428 bank = get_gpio_bank(gpio);
429 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
430 spin_lock(&bank->lock);
431 =======
432 spin_lock_irqsave(&bank->lock, flags);
433 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
434 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
435 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
436 spin_unlock(&bank->lock);
437 =======
438 spin_unlock_irqrestore(&bank->lock, flags);
439 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
440 }
441
442 int omap_get_gpio_datain(int gpio)
443 {
444 struct gpio_bank *bank;
445 void __iomem *reg;
446
447 if (check_gpio(gpio) < 0)
448 return -EINVAL;
449 bank = get_gpio_bank(gpio);
450 reg = bank->base;
451 switch (bank->method) {
452 #ifdef CONFIG_ARCH_OMAP1
453 case METHOD_MPUIO:
454 reg += OMAP_MPUIO_INPUT_LATCH;
455 break;
456 #endif
457 #ifdef CONFIG_ARCH_OMAP15XX
458 case METHOD_GPIO_1510:
459 reg += OMAP1510_GPIO_DATA_INPUT;
460 break;
461 #endif
462 #ifdef CONFIG_ARCH_OMAP16XX
463 case METHOD_GPIO_1610:
464 reg += OMAP1610_GPIO_DATAIN;
465 break;
466 #endif
467 #ifdef CONFIG_ARCH_OMAP730
468 case METHOD_GPIO_730:
469 reg += OMAP730_GPIO_DATA_INPUT;
470 break;
471 #endif
472 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
473 case METHOD_GPIO_24XX:
474 reg += OMAP24XX_GPIO_DATAIN;
475 break;
476 #endif
477 default:
478 return -EINVAL;
479 }
480 return (__raw_readl(reg)
481 & (1 << get_gpio_index(gpio))) != 0;
482 }
483
484 #define MOD_REG_BIT(reg, bit_mask, set) \
485 do { \
486 int l = __raw_readl(base + reg); \
487 if (set) l |= bit_mask; \
488 else l &= ~bit_mask; \
489 __raw_writel(l, base + reg); \
490 } while(0)
491
492 void omap_set_gpio_debounce(int gpio, int enable)
493 {
494 struct gpio_bank *bank;
495 void __iomem *reg;
496 u32 val, l = 1 << get_gpio_index(gpio);
497
498 if (cpu_class_is_omap1())
499 return;
500
501 bank = get_gpio_bank(gpio);
502 reg = bank->base;
503
504 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
505 val = __raw_readl(reg);
506
507 if (enable)
508 val |= l;
509 else
510 val &= ~l;
511
512 __raw_writel(val, reg);
513 }
514 EXPORT_SYMBOL(omap_set_gpio_debounce);
515
516 void omap_set_gpio_debounce_time(int gpio, int enc_time)
517 {
518 struct gpio_bank *bank;
519 void __iomem *reg;
520
521 if (cpu_class_is_omap1())
522 return;
523
524 bank = get_gpio_bank(gpio);
525 reg = bank->base;
526
527 enc_time &= 0xff;
528 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
529 __raw_writel(enc_time, reg);
530 }
531 EXPORT_SYMBOL(omap_set_gpio_debounce_time);
532
533 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
534 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
535 int trigger)
536 {
537 void __iomem *base = bank->base;
538 u32 gpio_bit = 1 << gpio;
539
540 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
541 trigger & __IRQT_LOWLVL);
542 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
543 trigger & __IRQT_HIGHLVL);
544 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
545 trigger & __IRQT_RISEDGE);
546 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
547 trigger & __IRQT_FALEDGE);
548
549 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
550 if (trigger != 0)
551 __raw_writel(1 << gpio, bank->base
552 + OMAP24XX_GPIO_SETWKUENA);
553 else
554 __raw_writel(1 << gpio, bank->base
555 + OMAP24XX_GPIO_CLEARWKUENA);
556 } else {
557 if (trigger != 0)
558 bank->enabled_non_wakeup_gpios |= gpio_bit;
559 else
560 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
561 }
562
563 /*
564 * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
565 * level triggering requested.
566 */
567 }
568 #endif
569
570 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
571 {
572 void __iomem *reg = bank->base;
573 u32 l = 0;
574
575 switch (bank->method) {
576 #ifdef CONFIG_ARCH_OMAP1
577 case METHOD_MPUIO:
578 reg += OMAP_MPUIO_GPIO_INT_EDGE;
579 l = __raw_readl(reg);
580 if (trigger & __IRQT_RISEDGE)
581 l |= 1 << gpio;
582 else if (trigger & __IRQT_FALEDGE)
583 l &= ~(1 << gpio);
584 else
585 goto bad;
586 break;
587 #endif
588 #ifdef CONFIG_ARCH_OMAP15XX
589 case METHOD_GPIO_1510:
590 reg += OMAP1510_GPIO_INT_CONTROL;
591 l = __raw_readl(reg);
592 if (trigger & __IRQT_RISEDGE)
593 l |= 1 << gpio;
594 else if (trigger & __IRQT_FALEDGE)
595 l &= ~(1 << gpio);
596 else
597 goto bad;
598 break;
599 #endif
600 #ifdef CONFIG_ARCH_OMAP16XX
601 case METHOD_GPIO_1610:
602 if (gpio & 0x08)
603 reg += OMAP1610_GPIO_EDGE_CTRL2;
604 else
605 reg += OMAP1610_GPIO_EDGE_CTRL1;
606 gpio &= 0x07;
607 l = __raw_readl(reg);
608 l &= ~(3 << (gpio << 1));
609 if (trigger & __IRQT_RISEDGE)
610 l |= 2 << (gpio << 1);
611 if (trigger & __IRQT_FALEDGE)
612 l |= 1 << (gpio << 1);
613 if (trigger)
614 /* Enable wake-up during idle for dynamic tick */
615 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
616 else
617 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
618 break;
619 #endif
620 #ifdef CONFIG_ARCH_OMAP730
621 case METHOD_GPIO_730:
622 reg += OMAP730_GPIO_INT_CONTROL;
623 l = __raw_readl(reg);
624 if (trigger & __IRQT_RISEDGE)
625 l |= 1 << gpio;
626 else if (trigger & __IRQT_FALEDGE)
627 l &= ~(1 << gpio);
628 else
629 goto bad;
630 break;
631 #endif
632 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
633 case METHOD_GPIO_24XX:
634 set_24xx_gpio_triggering(bank, gpio, trigger);
635 break;
636 #endif
637 default:
638 goto bad;
639 }
640 __raw_writel(l, reg);
641 return 0;
642 bad:
643 return -EINVAL;
644 }
645
646 static int gpio_irq_type(unsigned irq, unsigned type)
647 {
648 struct gpio_bank *bank;
649 unsigned gpio;
650 int retval;
651 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
652 =======
653 unsigned long flags;
654 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
655
656 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
657 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
658 else
659 gpio = irq - IH_GPIO_BASE;
660
661 if (check_gpio(gpio) < 0)
662 return -EINVAL;
663
664 if (type & ~IRQ_TYPE_SENSE_MASK)
665 return -EINVAL;
666
667 /* OMAP1 allows only only edge triggering */
668 if (!cpu_class_is_omap2()
669 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
670 return -EINVAL;
671
672 bank = get_irq_chip_data(irq);
673 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
674 spin_lock(&bank->lock);
675 =======
676 spin_lock_irqsave(&bank->lock, flags);
677 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
678 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
679 if (retval == 0) {
680 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
681 irq_desc[irq].status |= type;
682 }
683 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
684 spin_unlock(&bank->lock);
685 =======
686 spin_unlock_irqrestore(&bank->lock, flags);
687 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
688 return retval;
689 }
690
691 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
692 {
693 void __iomem *reg = bank->base;
694
695 switch (bank->method) {
696 #ifdef CONFIG_ARCH_OMAP1
697 case METHOD_MPUIO:
698 /* MPUIO irqstatus is reset by reading the status register,
699 * so do nothing here */
700 return;
701 #endif
702 #ifdef CONFIG_ARCH_OMAP15XX
703 case METHOD_GPIO_1510:
704 reg += OMAP1510_GPIO_INT_STATUS;
705 break;
706 #endif
707 #ifdef CONFIG_ARCH_OMAP16XX
708 case METHOD_GPIO_1610:
709 reg += OMAP1610_GPIO_IRQSTATUS1;
710 break;
711 #endif
712 #ifdef CONFIG_ARCH_OMAP730
713 case METHOD_GPIO_730:
714 reg += OMAP730_GPIO_INT_STATUS;
715 break;
716 #endif
717 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
718 case METHOD_GPIO_24XX:
719 reg += OMAP24XX_GPIO_IRQSTATUS1;
720 break;
721 #endif
722 default:
723 WARN_ON(1);
724 return;
725 }
726 __raw_writel(gpio_mask, reg);
727
728 /* Workaround for clearing DSP GPIO interrupts to allow retention */
729 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
730 if (cpu_is_omap24xx() || cpu_is_omap34xx())
731 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
732 #endif
733 }
734
735 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
736 {
737 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
738 }
739
740 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
741 {
742 void __iomem *reg = bank->base;
743 int inv = 0;
744 u32 l;
745 u32 mask;
746
747 switch (bank->method) {
748 #ifdef CONFIG_ARCH_OMAP1
749 case METHOD_MPUIO:
750 reg += OMAP_MPUIO_GPIO_MASKIT;
751 mask = 0xffff;
752 inv = 1;
753 break;
754 #endif
755 #ifdef CONFIG_ARCH_OMAP15XX
756 case METHOD_GPIO_1510:
757 reg += OMAP1510_GPIO_INT_MASK;
758 mask = 0xffff;
759 inv = 1;
760 break;
761 #endif
762 #ifdef CONFIG_ARCH_OMAP16XX
763 case METHOD_GPIO_1610:
764 reg += OMAP1610_GPIO_IRQENABLE1;
765 mask = 0xffff;
766 break;
767 #endif
768 #ifdef CONFIG_ARCH_OMAP730
769 case METHOD_GPIO_730:
770 reg += OMAP730_GPIO_INT_MASK;
771 mask = 0xffffffff;
772 inv = 1;
773 break;
774 #endif
775 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
776 case METHOD_GPIO_24XX:
777 reg += OMAP24XX_GPIO_IRQENABLE1;
778 mask = 0xffffffff;
779 break;
780 #endif
781 default:
782 WARN_ON(1);
783 return 0;
784 }
785
786 l = __raw_readl(reg);
787 if (inv)
788 l = ~l;
789 l &= mask;
790 return l;
791 }
792
793 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
794 {
795 void __iomem *reg = bank->base;
796 u32 l;
797
798 switch (bank->method) {
799 #ifdef CONFIG_ARCH_OMAP1
800 case METHOD_MPUIO:
801 reg += OMAP_MPUIO_GPIO_MASKIT;
802 l = __raw_readl(reg);
803 if (enable)
804 l &= ~(gpio_mask);
805 else
806 l |= gpio_mask;
807 break;
808 #endif
809 #ifdef CONFIG_ARCH_OMAP15XX
810 case METHOD_GPIO_1510:
811 reg += OMAP1510_GPIO_INT_MASK;
812 l = __raw_readl(reg);
813 if (enable)
814 l &= ~(gpio_mask);
815 else
816 l |= gpio_mask;
817 break;
818 #endif
819 #ifdef CONFIG_ARCH_OMAP16XX
820 case METHOD_GPIO_1610:
821 if (enable)
822 reg += OMAP1610_GPIO_SET_IRQENABLE1;
823 else
824 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
825 l = gpio_mask;
826 break;
827 #endif
828 #ifdef CONFIG_ARCH_OMAP730
829 case METHOD_GPIO_730:
830 reg += OMAP730_GPIO_INT_MASK;
831 l = __raw_readl(reg);
832 if (enable)
833 l &= ~(gpio_mask);
834 else
835 l |= gpio_mask;
836 break;
837 #endif
838 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
839 case METHOD_GPIO_24XX:
840 if (enable)
841 reg += OMAP24XX_GPIO_SETIRQENABLE1;
842 else
843 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
844 l = gpio_mask;
845 break;
846 #endif
847 default:
848 WARN_ON(1);
849 return;
850 }
851 __raw_writel(l, reg);
852 }
853
854 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
855 {
856 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
857 }
858
859 /*
860 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
861 * 1510 does not seem to have a wake-up register. If JTAG is connected
862 * to the target, system will wake up always on GPIO events. While
863 * system is running all registered GPIO interrupts need to have wake-up
864 * enabled. When system is suspended, only selected GPIO interrupts need
865 * to have wake-up enabled.
866 */
867 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
868 {
869 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
870 =======
871 unsigned long flags;
872
873 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
874 switch (bank->method) {
875 #ifdef CONFIG_ARCH_OMAP16XX
876 case METHOD_MPUIO:
877 case METHOD_GPIO_1610:
878 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
879 spin_lock(&bank->lock);
880 =======
881 spin_lock_irqsave(&bank->lock, flags);
882 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
883 if (enable) {
884 bank->suspend_wakeup |= (1 << gpio);
885 enable_irq_wake(bank->irq);
886 } else {
887 disable_irq_wake(bank->irq);
888 bank->suspend_wakeup &= ~(1 << gpio);
889 }
890 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
891 spin_unlock(&bank->lock);
892 =======
893 spin_unlock_irqrestore(&bank->lock, flags);
894 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
895 return 0;
896 #endif
897 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
898 case METHOD_GPIO_24XX:
899 if (bank->non_wakeup_gpios & (1 << gpio)) {
900 printk(KERN_ERR "Unable to modify wakeup on "
901 "non-wakeup GPIO%d\n",
902 (bank - gpio_bank) * 32 + gpio);
903 return -EINVAL;
904 }
905 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
906 spin_lock(&bank->lock);
907 =======
908 spin_lock_irqsave(&bank->lock, flags);
909 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
910 if (enable) {
911 bank->suspend_wakeup |= (1 << gpio);
912 enable_irq_wake(bank->irq);
913 } else {
914 disable_irq_wake(bank->irq);
915 bank->suspend_wakeup &= ~(1 << gpio);
916 }
917 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
918 spin_unlock(&bank->lock);
919 =======
920 spin_unlock_irqrestore(&bank->lock, flags);
921 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
922 return 0;
923 #endif
924 default:
925 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
926 bank->method);
927 return -EINVAL;
928 }
929 }
930
931 static void _reset_gpio(struct gpio_bank *bank, int gpio)
932 {
933 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
934 _set_gpio_irqenable(bank, gpio, 0);
935 _clear_gpio_irqstatus(bank, gpio);
936 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
937 }
938
939 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
940 static int gpio_wake_enable(unsigned int irq, unsigned int enable)
941 {
942 unsigned int gpio = irq - IH_GPIO_BASE;
943 struct gpio_bank *bank;
944 int retval;
945
946 if (check_gpio(gpio) < 0)
947 return -ENODEV;
948 bank = get_irq_chip_data(irq);
949 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
950
951 return retval;
952 }
953
954 int omap_request_gpio(int gpio)
955 {
956 struct gpio_bank *bank;
957 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
958 =======
959 unsigned long flags;
960 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
961
962 if (check_gpio(gpio) < 0)
963 return -EINVAL;
964
965 bank = get_gpio_bank(gpio);
966 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
967 spin_lock(&bank->lock);
968 =======
969 spin_lock_irqsave(&bank->lock, flags);
970 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
971 if (unlikely(bank->reserved_map & (1 << get_gpio_index(gpio)))) {
972 printk(KERN_ERR "omap-gpio: GPIO %d is already reserved!\n", gpio);
973 dump_stack();
974 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
975 spin_unlock(&bank->lock);
976 =======
977 spin_unlock_irqrestore(&bank->lock, flags);
978 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
979 return -1;
980 }
981 bank->reserved_map |= (1 << get_gpio_index(gpio));
982
983 /* Set trigger to none. You need to enable the desired trigger with
984 * request_irq() or set_irq_type().
985 */
986 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQT_NOEDGE);
987
988 #ifdef CONFIG_ARCH_OMAP15XX
989 if (bank->method == METHOD_GPIO_1510) {
990 void __iomem *reg;
991
992 /* Claim the pin for MPU */
993 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
994 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
995 }
996 #endif
997 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
998 spin_unlock(&bank->lock);
999 =======
1000 spin_unlock_irqrestore(&bank->lock, flags);
1001 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1002
1003 return 0;
1004 }
1005
1006 void omap_free_gpio(int gpio)
1007 {
1008 struct gpio_bank *bank;
1009 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1010 =======
1011 unsigned long flags;
1012 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1013
1014 if (check_gpio(gpio) < 0)
1015 return;
1016 bank = get_gpio_bank(gpio);
1017 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1018 spin_lock(&bank->lock);
1019 =======
1020 spin_lock_irqsave(&bank->lock, flags);
1021 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1022 if (unlikely(!(bank->reserved_map & (1 << get_gpio_index(gpio))))) {
1023 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
1024 dump_stack();
1025 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1026 spin_unlock(&bank->lock);
1027 =======
1028 spin_unlock_irqrestore(&bank->lock, flags);
1029 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1030 return;
1031 }
1032 #ifdef CONFIG_ARCH_OMAP16XX
1033 if (bank->method == METHOD_GPIO_1610) {
1034 /* Disable wake-up during idle for dynamic tick */
1035 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1036 __raw_writel(1 << get_gpio_index(gpio), reg);
1037 }
1038 #endif
1039 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1040 if (bank->method == METHOD_GPIO_24XX) {
1041 /* Disable wake-up during idle for dynamic tick */
1042 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1043 __raw_writel(1 << get_gpio_index(gpio), reg);
1044 }
1045 #endif
1046 bank->reserved_map &= ~(1 << get_gpio_index(gpio));
1047 _reset_gpio(bank, gpio);
1048 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1049 spin_unlock(&bank->lock);
1050 =======
1051 spin_unlock_irqrestore(&bank->lock, flags);
1052 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1053 }
1054
1055 /*
1056 * We need to unmask the GPIO bank interrupt as soon as possible to
1057 * avoid missing GPIO interrupts for other lines in the bank.
1058 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1059 * in the bank to avoid missing nested interrupts for a GPIO line.
1060 * If we wait to unmask individual GPIO lines in the bank after the
1061 * line's interrupt handler has been run, we may miss some nested
1062 * interrupts.
1063 */
1064 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
1065 {
1066 void __iomem *isr_reg = NULL;
1067 u32 isr;
1068 unsigned int gpio_irq;
1069 struct gpio_bank *bank;
1070 u32 retrigger = 0;
1071 int unmasked = 0;
1072
1073 desc->chip->ack(irq);
1074
1075 bank = get_irq_data(irq);
1076 #ifdef CONFIG_ARCH_OMAP1
1077 if (bank->method == METHOD_MPUIO)
1078 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
1079 #endif
1080 #ifdef CONFIG_ARCH_OMAP15XX
1081 if (bank->method == METHOD_GPIO_1510)
1082 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1083 #endif
1084 #if defined(CONFIG_ARCH_OMAP16XX)
1085 if (bank->method == METHOD_GPIO_1610)
1086 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1087 #endif
1088 #ifdef CONFIG_ARCH_OMAP730
1089 if (bank->method == METHOD_GPIO_730)
1090 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1091 #endif
1092 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1093 if (bank->method == METHOD_GPIO_24XX)
1094 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1095 #endif
1096 while(1) {
1097 u32 isr_saved, level_mask = 0;
1098 u32 enabled;
1099
1100 enabled = _get_gpio_irqbank_mask(bank);
1101 isr_saved = isr = __raw_readl(isr_reg) & enabled;
1102
1103 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1104 isr &= 0x0000ffff;
1105
1106 if (cpu_class_is_omap2()) {
1107 level_mask =
1108 __raw_readl(bank->base +
1109 OMAP24XX_GPIO_LEVELDETECT0) |
1110 __raw_readl(bank->base +
1111 OMAP24XX_GPIO_LEVELDETECT1);
1112 level_mask &= enabled;
1113 }
1114
1115 /* clear edge sensitive interrupts before handler(s) are
1116 called so that we don't miss any interrupt occurred while
1117 executing them */
1118 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1119 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1120 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1121
1122 /* if there is only edge sensitive GPIO pin interrupts
1123 configured, we could unmask GPIO bank interrupt immediately */
1124 if (!level_mask && !unmasked) {
1125 unmasked = 1;
1126 desc->chip->unmask(irq);
1127 }
1128
1129 isr |= retrigger;
1130 retrigger = 0;
1131 if (!isr)
1132 break;
1133
1134 gpio_irq = bank->virtual_irq_start;
1135 for (; isr != 0; isr >>= 1, gpio_irq++) {
1136 struct irq_desc *d;
1137 int irq_mask;
1138 if (!(isr & 1))
1139 continue;
1140 d = irq_desc + gpio_irq;
1141 /* Don't run the handler if it's already running
1142 * or was disabled lazely.
1143 */
1144 if (unlikely((d->depth ||
1145 (d->status & IRQ_INPROGRESS)))) {
1146 irq_mask = 1 <<
1147 (gpio_irq - bank->virtual_irq_start);
1148 /* The unmasking will be done by
1149 * enable_irq in case it is disabled or
1150 * after returning from the handler if
1151 * it's already running.
1152 */
1153 _enable_gpio_irqbank(bank, irq_mask, 0);
1154 if (!d->depth) {
1155 /* Level triggered interrupts
1156 * won't ever be reentered
1157 */
1158 BUG_ON(level_mask & irq_mask);
1159 d->status |= IRQ_PENDING;
1160 }
1161 continue;
1162 }
1163
1164 desc_handle_irq(gpio_irq, d);
1165
1166 if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
1167 irq_mask = 1 <<
1168 (gpio_irq - bank->virtual_irq_start);
1169 d->status &= ~IRQ_PENDING;
1170 _enable_gpio_irqbank(bank, irq_mask, 1);
1171 retrigger |= irq_mask;
1172 }
1173 }
1174
1175 if (cpu_class_is_omap2()) {
1176 /* clear level sensitive interrupts after handler(s) */
1177 _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
1178 _clear_gpio_irqbank(bank, isr_saved & level_mask);
1179 _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
1180 }
1181
1182 }
1183 /* if bank has any level sensitive GPIO pin interrupt
1184 configured, we must unmask the bank interrupt only after
1185 handler(s) are executed in order to avoid spurious bank
1186 interrupt */
1187 if (!unmasked)
1188 desc->chip->unmask(irq);
1189
1190 }
1191
1192 static void gpio_irq_shutdown(unsigned int irq)
1193 {
1194 unsigned int gpio = irq - IH_GPIO_BASE;
1195 struct gpio_bank *bank = get_irq_chip_data(irq);
1196
1197 _reset_gpio(bank, gpio);
1198 }
1199
1200 static void gpio_ack_irq(unsigned int irq)
1201 {
1202 unsigned int gpio = irq - IH_GPIO_BASE;
1203 struct gpio_bank *bank = get_irq_chip_data(irq);
1204
1205 _clear_gpio_irqstatus(bank, gpio);
1206 }
1207
1208 static void gpio_mask_irq(unsigned int irq)
1209 {
1210 unsigned int gpio = irq - IH_GPIO_BASE;
1211 struct gpio_bank *bank = get_irq_chip_data(irq);
1212
1213 _set_gpio_irqenable(bank, gpio, 0);
1214 }
1215
1216 static void gpio_unmask_irq(unsigned int irq)
1217 {
1218 unsigned int gpio = irq - IH_GPIO_BASE;
1219 unsigned int gpio_idx = get_gpio_index(gpio);
1220 struct gpio_bank *bank = get_irq_chip_data(irq);
1221
1222 _set_gpio_irqenable(bank, gpio_idx, 1);
1223 }
1224
1225 static struct irq_chip gpio_irq_chip = {
1226 .name = "GPIO",
1227 .shutdown = gpio_irq_shutdown,
1228 .ack = gpio_ack_irq,
1229 .mask = gpio_mask_irq,
1230 .unmask = gpio_unmask_irq,
1231 .set_type = gpio_irq_type,
1232 .set_wake = gpio_wake_enable,
1233 };
1234
1235 /*---------------------------------------------------------------------*/
1236
1237 #ifdef CONFIG_ARCH_OMAP1
1238
1239 /* MPUIO uses the always-on 32k clock */
1240
1241 static void mpuio_ack_irq(unsigned int irq)
1242 {
1243 /* The ISR is reset automatically, so do nothing here. */
1244 }
1245
1246 static void mpuio_mask_irq(unsigned int irq)
1247 {
1248 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1249 struct gpio_bank *bank = get_irq_chip_data(irq);
1250
1251 _set_gpio_irqenable(bank, gpio, 0);
1252 }
1253
1254 static void mpuio_unmask_irq(unsigned int irq)
1255 {
1256 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
1257 struct gpio_bank *bank = get_irq_chip_data(irq);
1258
1259 _set_gpio_irqenable(bank, gpio, 1);
1260 }
1261
1262 static struct irq_chip mpuio_irq_chip = {
1263 .name = "MPUIO",
1264 .ack = mpuio_ack_irq,
1265 .mask = mpuio_mask_irq,
1266 .unmask = mpuio_unmask_irq,
1267 .set_type = gpio_irq_type,
1268 #ifdef CONFIG_ARCH_OMAP16XX
1269 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1270 .set_wake = gpio_wake_enable,
1271 #endif
1272 };
1273
1274
1275 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1276
1277
1278 #ifdef CONFIG_ARCH_OMAP16XX
1279
1280 #include <linux/platform_device.h>
1281
1282 static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1283 {
1284 struct gpio_bank *bank = platform_get_drvdata(pdev);
1285 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1286 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1287 =======
1288 unsigned long flags;
1289 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1290
1291 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1292 spin_lock(&bank->lock);
1293 =======
1294 spin_lock_irqsave(&bank->lock, flags);
1295 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1296 bank->saved_wakeup = __raw_readl(mask_reg);
1297 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
1298 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1299 spin_unlock(&bank->lock);
1300 =======
1301 spin_unlock_irqrestore(&bank->lock, flags);
1302 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1303
1304 return 0;
1305 }
1306
1307 static int omap_mpuio_resume_early(struct platform_device *pdev)
1308 {
1309 struct gpio_bank *bank = platform_get_drvdata(pdev);
1310 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
1311 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1312 =======
1313 unsigned long flags;
1314 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1315
1316 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1317 spin_lock(&bank->lock);
1318 =======
1319 spin_lock_irqsave(&bank->lock, flags);
1320 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1321 __raw_writel(bank->saved_wakeup, mask_reg);
1322 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1323 spin_unlock(&bank->lock);
1324 =======
1325 spin_unlock_irqrestore(&bank->lock, flags);
1326 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1327
1328 return 0;
1329 }
1330
1331 /* use platform_driver for this, now that there's no longer any
1332 * point to sys_device (other than not disturbing old code).
1333 */
1334 static struct platform_driver omap_mpuio_driver = {
1335 .suspend_late = omap_mpuio_suspend_late,
1336 .resume_early = omap_mpuio_resume_early,
1337 .driver = {
1338 .name = "mpuio",
1339 },
1340 };
1341
1342 static struct platform_device omap_mpuio_device = {
1343 .name = "mpuio",
1344 .id = -1,
1345 .dev = {
1346 .driver = &omap_mpuio_driver.driver,
1347 }
1348 /* could list the /proc/iomem resources */
1349 };
1350
1351 static inline void mpuio_init(void)
1352 {
1353 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1354
1355 if (platform_driver_register(&omap_mpuio_driver) == 0)
1356 (void) platform_device_register(&omap_mpuio_device);
1357 }
1358
1359 #else
1360 static inline void mpuio_init(void) {}
1361 #endif /* 16xx */
1362
1363 #else
1364
1365 extern struct irq_chip mpuio_irq_chip;
1366
1367 #define bank_is_mpuio(bank) 0
1368 static inline void mpuio_init(void) {}
1369
1370 #endif
1371
1372 /*---------------------------------------------------------------------*/
1373
1374 static int initialized;
1375 #if !defined(CONFIG_ARCH_OMAP3)
1376 static struct clk * gpio_ick;
1377 #endif
1378
1379 #if defined(CONFIG_ARCH_OMAP2)
1380 static struct clk * gpio_fck;
1381 #endif
1382
1383 #if defined(CONFIG_ARCH_OMAP2430)
1384 static struct clk * gpio5_ick;
1385 static struct clk * gpio5_fck;
1386 #endif
1387
1388 #if defined(CONFIG_ARCH_OMAP3)
1389 static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1390 static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1391 #endif
1392
1393 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1394 =======
1395 /* This lock class tells lockdep that GPIO irqs are in a different
1396 * category than their parents, so it won't report false recursion.
1397 */
1398 static struct lock_class_key gpio_lock_class;
1399
1400 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1401 static int __init _omap_gpio_init(void)
1402 {
1403 int i;
1404 struct gpio_bank *bank;
1405 #if defined(CONFIG_ARCH_OMAP3)
1406 char clk_name[11];
1407 #endif
1408
1409 initialized = 1;
1410
1411 #if defined(CONFIG_ARCH_OMAP1)
1412 if (cpu_is_omap15xx()) {
1413 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1414 if (IS_ERR(gpio_ick))
1415 printk("Could not get arm_gpio_ck\n");
1416 else
1417 clk_enable(gpio_ick);
1418 }
1419 #endif
1420 #if defined(CONFIG_ARCH_OMAP2)
1421 if (cpu_class_is_omap2()) {
1422 gpio_ick = clk_get(NULL, "gpios_ick");
1423 if (IS_ERR(gpio_ick))
1424 printk("Could not get gpios_ick\n");
1425 else
1426 clk_enable(gpio_ick);
1427 gpio_fck = clk_get(NULL, "gpios_fck");
1428 if (IS_ERR(gpio_fck))
1429 printk("Could not get gpios_fck\n");
1430 else
1431 clk_enable(gpio_fck);
1432
1433 /*
1434 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
1435 */
1436 #if defined(CONFIG_ARCH_OMAP2430)
1437 if (cpu_is_omap2430()) {
1438 gpio5_ick = clk_get(NULL, "gpio5_ick");
1439 if (IS_ERR(gpio5_ick))
1440 printk("Could not get gpio5_ick\n");
1441 else
1442 clk_enable(gpio5_ick);
1443 gpio5_fck = clk_get(NULL, "gpio5_fck");
1444 if (IS_ERR(gpio5_fck))
1445 printk("Could not get gpio5_fck\n");
1446 else
1447 clk_enable(gpio5_fck);
1448 }
1449 #endif
1450 }
1451 #endif
1452
1453 #if defined(CONFIG_ARCH_OMAP3)
1454 if (cpu_is_omap34xx()) {
1455 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1456 sprintf(clk_name, "gpio%d_ick", i + 1);
1457 gpio_iclks[i] = clk_get(NULL, clk_name);
1458 if (IS_ERR(gpio_iclks[i]))
1459 printk(KERN_ERR "Could not get %s\n", clk_name);
1460 else
1461 clk_enable(gpio_iclks[i]);
1462 sprintf(clk_name, "gpio%d_fck", i + 1);
1463 gpio_fclks[i] = clk_get(NULL, clk_name);
1464 if (IS_ERR(gpio_fclks[i]))
1465 printk(KERN_ERR "Could not get %s\n", clk_name);
1466 else
1467 clk_enable(gpio_fclks[i]);
1468 }
1469 }
1470 #endif
1471
1472
1473 #ifdef CONFIG_ARCH_OMAP15XX
1474 if (cpu_is_omap15xx()) {
1475 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1476 gpio_bank_count = 2;
1477 gpio_bank = gpio_bank_1510;
1478 }
1479 #endif
1480 #if defined(CONFIG_ARCH_OMAP16XX)
1481 if (cpu_is_omap16xx()) {
1482 u32 rev;
1483
1484 gpio_bank_count = 5;
1485 gpio_bank = gpio_bank_1610;
1486 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1487 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1488 (rev >> 4) & 0x0f, rev & 0x0f);
1489 }
1490 #endif
1491 #ifdef CONFIG_ARCH_OMAP730
1492 if (cpu_is_omap730()) {
1493 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1494 gpio_bank_count = 7;
1495 gpio_bank = gpio_bank_730;
1496 }
1497 #endif
1498
1499 #ifdef CONFIG_ARCH_OMAP24XX
1500 if (cpu_is_omap242x()) {
1501 int rev;
1502
1503 gpio_bank_count = 4;
1504 gpio_bank = gpio_bank_242x;
1505 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1506 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1507 (rev >> 4) & 0x0f, rev & 0x0f);
1508 }
1509 if (cpu_is_omap243x()) {
1510 int rev;
1511
1512 gpio_bank_count = 5;
1513 gpio_bank = gpio_bank_243x;
1514 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1515 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
1516 (rev >> 4) & 0x0f, rev & 0x0f);
1517 }
1518 #endif
1519 #ifdef CONFIG_ARCH_OMAP34XX
1520 if (cpu_is_omap34xx()) {
1521 int rev;
1522
1523 gpio_bank_count = OMAP34XX_NR_GPIOS;
1524 gpio_bank = gpio_bank_34xx;
1525 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1526 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1527 (rev >> 4) & 0x0f, rev & 0x0f);
1528 }
1529 #endif
1530 for (i = 0; i < gpio_bank_count; i++) {
1531 int j, gpio_count = 16;
1532
1533 bank = &gpio_bank[i];
1534 bank->reserved_map = 0;
1535 bank->base = IO_ADDRESS(bank->base);
1536 spin_lock_init(&bank->lock);
1537 if (bank_is_mpuio(bank))
1538 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
1539 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1540 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1541 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1542 }
1543 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1544 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1545 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
1546 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
1547 }
1548 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
1549 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1550 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1551
1552 gpio_count = 32; /* 730 has 32-bit GPIOs */
1553 }
1554
1555 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1556 if (bank->method == METHOD_GPIO_24XX) {
1557 static const u32 non_wakeup_gpios[] = {
1558 0xe203ffc0, 0x08700040
1559 };
1560
1561 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1562 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
1563 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1564
1565 /* Initialize interface clock ungated, module enabled */
1566 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1567 if (i < ARRAY_SIZE(non_wakeup_gpios))
1568 bank->non_wakeup_gpios = non_wakeup_gpios[i];
1569 gpio_count = 32;
1570 }
1571 #endif
1572 for (j = bank->virtual_irq_start;
1573 j < bank->virtual_irq_start + gpio_count; j++) {
1574 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1575 =======
1576 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
1577 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1578 set_irq_chip_data(j, bank);
1579 if (bank_is_mpuio(bank))
1580 set_irq_chip(j, &mpuio_irq_chip);
1581 else
1582 set_irq_chip(j, &gpio_irq_chip);
1583 set_irq_handler(j, handle_simple_irq);
1584 set_irq_flags(j, IRQF_VALID);
1585 }
1586 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1587 set_irq_data(bank->irq, bank);
1588 }
1589
1590 /* Enable system clock for GPIO module.
1591 * The CAM_CLK_CTRL *is* really the right place. */
1592 if (cpu_is_omap16xx())
1593 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1594
1595 /* Enable autoidle for the OCP interface */
1596 if (cpu_is_omap24xx())
1597 omap_writel(1 << 0, 0x48019010);
1598 if (cpu_is_omap34xx())
1599 omap_writel(1 << 0, 0x48306814);
1600
1601 return 0;
1602 }
1603
1604 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1605 static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1606 {
1607 int i;
1608
1609 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
1610 return 0;
1611
1612 for (i = 0; i < gpio_bank_count; i++) {
1613 struct gpio_bank *bank = &gpio_bank[i];
1614 void __iomem *wake_status;
1615 void __iomem *wake_clear;
1616 void __iomem *wake_set;
1617 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1618 =======
1619 unsigned long flags;
1620 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1621
1622 switch (bank->method) {
1623 #ifdef CONFIG_ARCH_OMAP16XX
1624 case METHOD_GPIO_1610:
1625 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1626 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1627 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1628 break;
1629 #endif
1630 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1631 case METHOD_GPIO_24XX:
1632 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1633 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1634 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1635 break;
1636 #endif
1637 default:
1638 continue;
1639 }
1640
1641 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1642 spin_lock(&bank->lock);
1643 =======
1644 spin_lock_irqsave(&bank->lock, flags);
1645 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1646 bank->saved_wakeup = __raw_readl(wake_status);
1647 __raw_writel(0xffffffff, wake_clear);
1648 __raw_writel(bank->suspend_wakeup, wake_set);
1649 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1650 spin_unlock(&bank->lock);
1651 =======
1652 spin_unlock_irqrestore(&bank->lock, flags);
1653 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1654 }
1655
1656 return 0;
1657 }
1658
1659 static int omap_gpio_resume(struct sys_device *dev)
1660 {
1661 int i;
1662
1663 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1664 return 0;
1665
1666 for (i = 0; i < gpio_bank_count; i++) {
1667 struct gpio_bank *bank = &gpio_bank[i];
1668 void __iomem *wake_clear;
1669 void __iomem *wake_set;
1670 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1671 =======
1672 unsigned long flags;
1673 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1674
1675 switch (bank->method) {
1676 #ifdef CONFIG_ARCH_OMAP16XX
1677 case METHOD_GPIO_1610:
1678 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1679 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1680 break;
1681 #endif
1682 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1683 case METHOD_GPIO_24XX:
1684 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1685 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1686 break;
1687 #endif
1688 default:
1689 continue;
1690 }
1691
1692 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1693 spin_lock(&bank->lock);
1694 =======
1695 spin_lock_irqsave(&bank->lock, flags);
1696 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1697 __raw_writel(0xffffffff, wake_clear);
1698 __raw_writel(bank->saved_wakeup, wake_set);
1699 <<<<<<< HEAD:arch/arm/plat-omap/gpio.c
1700 spin_unlock(&bank->lock);
1701 =======
1702 spin_unlock_irqrestore(&bank->lock, flags);
1703 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/plat-omap/gpio.c
1704 }
1705
1706 return 0;
1707 }
1708
1709 static struct sysdev_class omap_gpio_sysclass = {
1710 .name = "gpio",
1711 .suspend = omap_gpio_suspend,
1712 .resume = omap_gpio_resume,
1713 };
1714
1715 static struct sys_device omap_gpio_device = {
1716 .id = 0,
1717 .cls = &omap_gpio_sysclass,
1718 };
1719
1720 #endif
1721
1722 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1723
1724 static int workaround_enabled;
1725
1726 void omap2_gpio_prepare_for_retention(void)
1727 {
1728 int i, c = 0;
1729
1730 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1731 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1732 for (i = 0; i < gpio_bank_count; i++) {
1733 struct gpio_bank *bank = &gpio_bank[i];
1734 u32 l1, l2;
1735
1736 if (!(bank->enabled_non_wakeup_gpios))
1737 continue;
1738 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1739 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1740 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1741 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
1742 #endif
1743 bank->saved_fallingdetect = l1;
1744 bank->saved_risingdetect = l2;
1745 l1 &= ~bank->enabled_non_wakeup_gpios;
1746 l2 &= ~bank->enabled_non_wakeup_gpios;
1747 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1748 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1749 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
1750 #endif
1751 c++;
1752 }
1753 if (!c) {
1754 workaround_enabled = 0;
1755 return;
1756 }
1757 workaround_enabled = 1;
1758 }
1759
1760 void omap2_gpio_resume_after_retention(void)
1761 {
1762 int i;
1763
1764 if (!workaround_enabled)
1765 return;
1766 for (i = 0; i < gpio_bank_count; i++) {
1767 struct gpio_bank *bank = &gpio_bank[i];
1768 u32 l;
1769
1770 if (!(bank->enabled_non_wakeup_gpios))
1771 continue;
1772 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1773 __raw_writel(bank->saved_fallingdetect,
1774 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1775 __raw_writel(bank->saved_risingdetect,
1776 bank->base + OMAP24XX_GPIO_RISINGDETECT);
1777 #endif
1778 /* Check if any of the non-wakeup interrupt GPIOs have changed
1779 * state. If so, generate an IRQ by software. This is
1780 * horribly racy, but it's the best we can do to work around
1781 * this silicon bug. */
1782 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1783 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1784 #endif
1785 l ^= bank->saved_datain;
1786 l &= bank->non_wakeup_gpios;
1787 if (l) {
1788 u32 old0, old1;
1789 #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1790 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1791 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1792 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1793 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1794 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1795 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1796 #endif
1797 }
1798 }
1799
1800 }
1801
1802 #endif
1803
1804 /*
1805 * This may get called early from board specific init
1806 * for boards that have interrupts routed via FPGA.
1807 */
1808 int __init omap_gpio_init(void)
1809 {
1810 if (!initialized)
1811 return _omap_gpio_init();
1812 else
1813 return 0;
1814 }
1815
1816 static int __init omap_gpio_sysinit(void)
1817 {
1818 int ret = 0;
1819
1820 if (!initialized)
1821 ret = _omap_gpio_init();
1822
1823 mpuio_init();
1824
1825 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1826 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
1827 if (ret == 0) {
1828 ret = sysdev_class_register(&omap_gpio_sysclass);
1829 if (ret == 0)
1830 ret = sysdev_register(&omap_gpio_device);
1831 }
1832 }
1833 #endif
1834
1835 return ret;
1836 }
1837
1838 EXPORT_SYMBOL(omap_request_gpio);
1839 EXPORT_SYMBOL(omap_free_gpio);
1840 EXPORT_SYMBOL(omap_set_gpio_direction);
1841 EXPORT_SYMBOL(omap_set_gpio_dataout);
1842 EXPORT_SYMBOL(omap_get_gpio_datain);
1843
1844 arch_initcall(omap_gpio_sysinit);
1845
1846
1847 #ifdef CONFIG_DEBUG_FS
1848
1849 #include <linux/debugfs.h>
1850 #include <linux/seq_file.h>
1851
1852 static int gpio_is_input(struct gpio_bank *bank, int mask)
1853 {
1854 void __iomem *reg = bank->base;
1855
1856 switch (bank->method) {
1857 case METHOD_MPUIO:
1858 reg += OMAP_MPUIO_IO_CNTL;
1859 break;
1860 case METHOD_GPIO_1510:
1861 reg += OMAP1510_GPIO_DIR_CONTROL;
1862 break;
1863 case METHOD_GPIO_1610:
1864 reg += OMAP1610_GPIO_DIRECTION;
1865 break;
1866 case METHOD_GPIO_730:
1867 reg += OMAP730_GPIO_DIR_CONTROL;
1868 break;
1869 case METHOD_GPIO_24XX:
1870 reg += OMAP24XX_GPIO_OE;
1871 break;
1872 }
1873 return __raw_readl(reg) & mask;
1874 }
1875
1876
1877 static int dbg_gpio_show(struct seq_file *s, void *unused)
1878 {
1879 unsigned i, j, gpio;
1880
1881 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1882 struct gpio_bank *bank = gpio_bank + i;
1883 unsigned bankwidth = 16;
1884 u32 mask = 1;
1885
1886 if (bank_is_mpuio(bank))
1887 gpio = OMAP_MPUIO(0);
1888 else if (cpu_class_is_omap2() || cpu_is_omap730())
1889 bankwidth = 32;
1890
1891 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1892 unsigned irq, value, is_in, irqstat;
1893
1894 if (!(bank->reserved_map & mask))
1895 continue;
1896
1897 irq = bank->virtual_irq_start + j;
1898 value = omap_get_gpio_datain(gpio);
1899 is_in = gpio_is_input(bank, mask);
1900
1901 if (bank_is_mpuio(bank))
1902 seq_printf(s, "MPUIO %2d: ", j);
1903 else
1904 seq_printf(s, "GPIO %3d: ", gpio);
1905 seq_printf(s, "%s %s",
1906 is_in ? "in " : "out",
1907 value ? "hi" : "lo");
1908
1909 irqstat = irq_desc[irq].status;
1910 if (is_in && ((bank->suspend_wakeup & mask)
1911 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1912 char *trigger = NULL;
1913
1914 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1915 case IRQ_TYPE_EDGE_FALLING:
1916 trigger = "falling";
1917 break;
1918 case IRQ_TYPE_EDGE_RISING:
1919 trigger = "rising";
1920 break;
1921 case IRQ_TYPE_EDGE_BOTH:
1922 trigger = "bothedge";
1923 break;
1924 case IRQ_TYPE_LEVEL_LOW:
1925 trigger = "low";
1926 break;
1927 case IRQ_TYPE_LEVEL_HIGH:
1928 trigger = "high";
1929 break;
1930 case IRQ_TYPE_NONE:
1931 trigger = "(unspecified)";
1932 break;
1933 }
1934 seq_printf(s, ", irq-%d %s%s",
1935 irq, trigger,
1936 (bank->suspend_wakeup & mask)
1937 ? " wakeup" : "");
1938 }
1939 seq_printf(s, "\n");
1940 }
1941
1942 if (bank_is_mpuio(bank)) {
1943 seq_printf(s, "\n");
1944 gpio = 0;
1945 }
1946 }
1947 return 0;
1948 }
1949
1950 static int dbg_gpio_open(struct inode *inode, struct file *file)
1951 {
1952 return single_open(file, dbg_gpio_show, &inode->i_private);
1953 }
1954
1955 static const struct file_operations debug_fops = {
1956 .open = dbg_gpio_open,
1957 .read = seq_read,
1958 .llseek = seq_lseek,
1959 .release = single_release,
1960 };
1961
1962 static int __init omap_gpio_debuginit(void)
1963 {
1964 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1965 NULL, NULL, &debug_fops);
1966 return 0;
1967 }
1968 late_initcall(omap_gpio_debuginit);
1969 #endif
WRT350N Kernel Patches