arch/arm/mach-imx/dma.c

   1 /*
   2  *  linux/arch/arm/mach-imx/dma.c
   3  *
   4  *  imx DMA registration and IRQ dispatching
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License version 2 as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  2004-03-03 Sascha Hauer <sascha@saschahauer.de>
  11  *             initial version heavily inspired by
  12  *             linux/arch/arm/mach-pxa/dma.c
  13  *
  14  *  2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
  15  *             Changed to support scatter gather DMA
  16  *             by taking Russell's code from RiscPC
  17  *
  18  *  2006-05-31 Pavel Pisa <pisa@cmp.felk.cvut.cz>
  19  *             Corrected error handling code.
  20  *
  21  */
  22
  23 #undef DEBUG
  24
  25 #include <linux/module.h>
  26 #include <linux/init.h>
  27 #include <linux/kernel.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/errno.h>
  30
  31 #include <asm/system.h>
  32 #include <asm/irq.h>
  33 #include <asm/hardware.h>
  34 #include <asm/dma.h>
  35 #include <asm/arch/imx-dma.h>
  36
  37 struct imx_dma_channel imx_dma_channels[IMX_DMA_CHANNELS];
  38
  39 /*
  40  * imx_dma_sg_next - prepare next chunk for scatter-gather DMA emulation
  41  * @dma_ch: i.MX DMA channel number
  42  * @lastcount: number of bytes transferred during last transfer
  43  *
  44  * Functions prepares DMA controller for next sg data chunk transfer.
  45  * The @lastcount argument informs function about number of bytes transferred
  46  * during last block. Zero value can be used for @lastcount to setup DMA
  47  * for the first chunk.
  48  */
  49 static inline int imx_dma_sg_next(imx_dmach_t dma_ch, unsigned int lastcount)
  50 {
  51         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
  52         unsigned int nextcount;
  53         unsigned int nextaddr;
  54
  55         if (!imxdma->name) {
  56                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
  57 <<<<<<< HEAD:arch/arm/mach-imx/dma.c
  58                        __FUNCTION__, dma_ch);
  59 =======
  60                        __func__, dma_ch);
  61 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-imx/dma.c
  62                 return 0;
  63         }
  64
  65         imxdma->resbytes -= lastcount;
  66
  67         if (!imxdma->sg) {
  68                 pr_debug("imxdma%d: no sg data\n", dma_ch);
  69                 return 0;
  70         }
  71
  72         imxdma->sgbc += lastcount;
  73         if ((imxdma->sgbc >= imxdma->sg->length) || !imxdma->resbytes) {
  74                 if ((imxdma->sgcount <= 1) || !imxdma->resbytes) {
  75                         pr_debug("imxdma%d: sg transfer limit reached\n",
  76                                  dma_ch);
  77                         imxdma->sgcount=0;
  78                         imxdma->sg = NULL;
  79                         return 0;
  80                 } else {
  81                         imxdma->sgcount--;
  82                         imxdma->sg++;
  83                         imxdma->sgbc = 0;
  84                 }
  85         }
  86         nextcount = imxdma->sg->length - imxdma->sgbc;
  87         nextaddr = imxdma->sg->dma_address + imxdma->sgbc;
  88
  89         if(imxdma->resbytes < nextcount)
  90                 nextcount = imxdma->resbytes;
  91
  92         if ((imxdma->dma_mode & DMA_MODE_MASK) == DMA_MODE_READ)
  93                 DAR(dma_ch) = nextaddr;
  94         else
  95                 SAR(dma_ch) = nextaddr;
  96
  97         CNTR(dma_ch) = nextcount;
  98         pr_debug("imxdma%d: next sg chunk dst 0x%08x, src 0x%08x, size 0x%08x\n",
  99                  dma_ch, DAR(dma_ch), SAR(dma_ch), CNTR(dma_ch));
 100
 101         return nextcount;
 102 }
 103
 104 /*
 105  * imx_dma_setup_sg_base - scatter-gather DMA emulation
 106  * @dma_ch: i.MX DMA channel number
 107  * @sg: pointer to the scatter-gather list/vector
 108  * @sgcount: scatter-gather list hungs count
 109  *
 110  * Functions sets up i.MX DMA state for emulated scatter-gather transfer
 111  * and sets up channel registers to be ready for the first chunk
 112  */
 113 static int
 114 imx_dma_setup_sg_base(imx_dmach_t dma_ch,
 115                       struct scatterlist *sg, unsigned int sgcount)
 116 {
 117         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 118
 119         imxdma->sg = sg;
 120         imxdma->sgcount = sgcount;
 121         imxdma->sgbc = 0;
 122         return imx_dma_sg_next(dma_ch, 0);
 123 }
 124
 125 /**
 126  * imx_dma_setup_single - setup i.MX DMA channel for linear memory to/from device transfer
 127  * @dma_ch: i.MX DMA channel number
 128  * @dma_address: the DMA/physical memory address of the linear data block
 129  *              to transfer
 130  * @dma_length: length of the data block in bytes
 131  * @dev_addr: physical device port address
 132  * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
 133  *           or %DMA_MODE_WRITE from memory to the device
 134  *
 135  * The function setups DMA channel source and destination addresses for transfer
 136  * specified by provided parameters. The scatter-gather emulation is disabled,
 137  * because linear data block
 138  * form the physical address range is transferred.
 139  * Return value: if incorrect parameters are provided -%EINVAL.
 140  *              Zero indicates success.
 141  */
 142 int
 143 imx_dma_setup_single(imx_dmach_t dma_ch, dma_addr_t dma_address,
 144                      unsigned int dma_length, unsigned int dev_addr,
 145                      dmamode_t dmamode)
 146 {
 147         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 148
 149         imxdma->sg = NULL;
 150         imxdma->sgcount = 0;
 151         imxdma->dma_mode = dmamode;
 152         imxdma->resbytes = dma_length;
 153
 154         if (!dma_address) {
 155                 printk(KERN_ERR "imxdma%d: imx_dma_setup_single null address\n",
 156                        dma_ch);
 157                 return -EINVAL;
 158         }
 159
 160         if (!dma_length) {
 161                 printk(KERN_ERR "imxdma%d: imx_dma_setup_single zero length\n",
 162                        dma_ch);
 163                 return -EINVAL;
 164         }
 165
 166         if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
 167                 pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for read\n",
 168                         dma_ch, (unsigned int)dma_address, dma_length,
 169                         dev_addr);
 170                 SAR(dma_ch) = dev_addr;
 171                 DAR(dma_ch) = (unsigned int)dma_address;
 172         } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
 173                 pr_debug("imxdma%d: mx_dma_setup_single2dev dma_addressg=0x%08x dma_length=%d dev_addr=0x%08x for write\n",
 174                         dma_ch, (unsigned int)dma_address, dma_length,
 175                         dev_addr);
 176                 SAR(dma_ch) = (unsigned int)dma_address;
 177                 DAR(dma_ch) = dev_addr;
 178         } else {
 179                 printk(KERN_ERR "imxdma%d: imx_dma_setup_single bad dmamode\n",
 180                        dma_ch);
 181                 return -EINVAL;
 182         }
 183
 184         CNTR(dma_ch) = dma_length;
 185
 186         return 0;
 187 }
 188
 189 /**
 190  * imx_dma_setup_sg - setup i.MX DMA channel SG list to/from device transfer
 191  * @dma_ch: i.MX DMA channel number
 192  * @sg: pointer to the scatter-gather list/vector
 193  * @sgcount: scatter-gather list hungs count
 194  * @dma_length: total length of the transfer request in bytes
 195  * @dev_addr: physical device port address
 196  * @dmamode: DMA transfer mode, %DMA_MODE_READ from the device to the memory
 197  *           or %DMA_MODE_WRITE from memory to the device
 198  *
 199  * The function sets up DMA channel state and registers to be ready for transfer
 200  * specified by provided parameters. The scatter-gather emulation is set up
 201  * according to the parameters.
 202  *
 203  * The full preparation of the transfer requires setup of more register
 204  * by the caller before imx_dma_enable() can be called.
 205  *
 206  * %BLR(dma_ch) holds transfer burst length in bytes, 0 means 64 bytes
 207  *
 208  * %RSSR(dma_ch) has to be set to the DMA request line source %DMA_REQ_xxx
 209  *
 210  * %CCR(dma_ch) has to specify transfer parameters, the next settings is typical
 211  * for linear or simple scatter-gather transfers if %DMA_MODE_READ is specified
 212  *
 213  * %CCR_DMOD_LINEAR | %CCR_DSIZ_32 | %CCR_SMOD_FIFO | %CCR_SSIZ_x
 214  *
 215  * The typical setup for %DMA_MODE_WRITE is specified by next options combination
 216  *
 217  * %CCR_SMOD_LINEAR | %CCR_SSIZ_32 | %CCR_DMOD_FIFO | %CCR_DSIZ_x
 218  *
 219  * Be careful here and do not mistakenly mix source and target device
 220  * port sizes constants, they are really different:
 221  * %CCR_SSIZ_8, %CCR_SSIZ_16, %CCR_SSIZ_32,
 222  * %CCR_DSIZ_8, %CCR_DSIZ_16, %CCR_DSIZ_32
 223  *
 224  * Return value: if incorrect parameters are provided -%EINVAL.
 225  * Zero indicates success.
 226  */
 227 int
 228 imx_dma_setup_sg(imx_dmach_t dma_ch,
 229                  struct scatterlist *sg, unsigned int sgcount, unsigned int dma_length,
 230                  unsigned int dev_addr, dmamode_t dmamode)
 231 {
 232         int res;
 233         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 234
 235         imxdma->sg = NULL;
 236         imxdma->sgcount = 0;
 237         imxdma->dma_mode = dmamode;
 238         imxdma->resbytes = dma_length;
 239
 240         if (!sg || !sgcount) {
 241                 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg epty sg list\n",
 242                        dma_ch);
 243                 return -EINVAL;
 244         }
 245
 246         if (!sg->length) {
 247                 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg zero length\n",
 248                        dma_ch);
 249                 return -EINVAL;
 250         }
 251
 252         if ((dmamode & DMA_MODE_MASK) == DMA_MODE_READ) {
 253                 pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for read\n",
 254                         dma_ch, sg, sgcount, dma_length, dev_addr);
 255                 SAR(dma_ch) = dev_addr;
 256         } else if ((dmamode & DMA_MODE_MASK) == DMA_MODE_WRITE) {
 257                 pr_debug("imxdma%d: mx_dma_setup_sg2dev sg=%p sgcount=%d total length=%d dev_addr=0x%08x for write\n",
 258                         dma_ch, sg, sgcount, dma_length, dev_addr);
 259                 DAR(dma_ch) = dev_addr;
 260         } else {
 261                 printk(KERN_ERR "imxdma%d: imx_dma_setup_sg bad dmamode\n",
 262                        dma_ch);
 263                 return -EINVAL;
 264         }
 265
 266         res = imx_dma_setup_sg_base(dma_ch, sg, sgcount);
 267         if (res <= 0) {
 268                 printk(KERN_ERR "imxdma%d: no sg chunk ready\n", dma_ch);
 269                 return -EINVAL;
 270         }
 271
 272         return 0;
 273 }
 274
 275 /**
 276  * imx_dma_setup_handlers - setup i.MX DMA channel end and error notification handlers
 277  * @dma_ch: i.MX DMA channel number
 278  * @irq_handler: the pointer to the function called if the transfer
 279  *              ends successfully
 280  * @err_handler: the pointer to the function called if the premature
 281  *              end caused by error occurs
 282  * @data: user specified value to be passed to the handlers
 283  */
 284 int
 285 imx_dma_setup_handlers(imx_dmach_t dma_ch,
 286                        void (*irq_handler) (int, void *),
 287                        void (*err_handler) (int, void *, int),
 288                        void *data)
 289 {
 290         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 291         unsigned long flags;
 292
 293         if (!imxdma->name) {
 294                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
 295 <<<<<<< HEAD:arch/arm/mach-imx/dma.c
 296                        __FUNCTION__, dma_ch);
 297 =======
 298                        __func__, dma_ch);
 299 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-imx/dma.c
 300                 return -ENODEV;
 301         }
 302
 303         local_irq_save(flags);
 304         DISR = (1 << dma_ch);
 305         imxdma->irq_handler = irq_handler;
 306         imxdma->err_handler = err_handler;
 307         imxdma->data = data;
 308         local_irq_restore(flags);
 309         return 0;
 310 }
 311
 312 /**
 313  * imx_dma_enable - function to start i.MX DMA channel operation
 314  * @dma_ch: i.MX DMA channel number
 315  *
 316  * The channel has to be allocated by driver through imx_dma_request()
 317  * or imx_dma_request_by_prio() function.
 318  * The transfer parameters has to be set to the channel registers through
 319  * call of the imx_dma_setup_single() or imx_dma_setup_sg() function
 320  * and registers %BLR(dma_ch), %RSSR(dma_ch) and %CCR(dma_ch) has to
 321  * be set prior this function call by the channel user.
 322  */
 323 void imx_dma_enable(imx_dmach_t dma_ch)
 324 {
 325         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 326         unsigned long flags;
 327
 328         pr_debug("imxdma%d: imx_dma_enable\n", dma_ch);
 329
 330         if (!imxdma->name) {
 331                 printk(KERN_CRIT "%s: called for  not allocated channel %d\n",
 332 <<<<<<< HEAD:arch/arm/mach-imx/dma.c
 333                        __FUNCTION__, dma_ch);
 334 =======
 335                        __func__, dma_ch);
 336 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-imx/dma.c
 337                 return;
 338         }
 339
 340         local_irq_save(flags);
 341         DISR = (1 << dma_ch);
 342         DIMR &= ~(1 << dma_ch);
 343         CCR(dma_ch) |= CCR_CEN;
 344         local_irq_restore(flags);
 345 }
 346
 347 /**
 348  * imx_dma_disable - stop, finish i.MX DMA channel operatin
 349  * @dma_ch: i.MX DMA channel number
 350  */
 351 void imx_dma_disable(imx_dmach_t dma_ch)
 352 {
 353         unsigned long flags;
 354
 355         pr_debug("imxdma%d: imx_dma_disable\n", dma_ch);
 356
 357         local_irq_save(flags);
 358         DIMR |= (1 << dma_ch);
 359         CCR(dma_ch) &= ~CCR_CEN;
 360         DISR = (1 << dma_ch);
 361         local_irq_restore(flags);
 362 }
 363
 364 /**
 365  * imx_dma_request - request/allocate specified channel number
 366  * @dma_ch: i.MX DMA channel number
 367  * @name: the driver/caller own non-%NULL identification
 368  */
 369 int imx_dma_request(imx_dmach_t dma_ch, const char *name)
 370 {
 371         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 372         unsigned long flags;
 373
 374         /* basic sanity checks */
 375         if (!name)
 376                 return -EINVAL;
 377
 378         if (dma_ch >= IMX_DMA_CHANNELS) {
 379                 printk(KERN_CRIT "%s: called for  non-existed channel %d\n",
 380 <<<<<<< HEAD:arch/arm/mach-imx/dma.c
 381                        __FUNCTION__, dma_ch);
 382 =======
 383                        __func__, dma_ch);
 384 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-imx/dma.c
 385                 return -EINVAL;
 386         }
 387
 388         local_irq_save(flags);
 389         if (imxdma->name) {
 390                 local_irq_restore(flags);
 391                 return -ENODEV;
 392         }
 393
 394         imxdma->name = name;
 395         imxdma->irq_handler = NULL;
 396         imxdma->err_handler = NULL;
 397         imxdma->data = NULL;
 398         imxdma->sg = NULL;
 399         local_irq_restore(flags);
 400         return 0;
 401 }
 402
 403 /**
 404  * imx_dma_free - release previously acquired channel
 405  * @dma_ch: i.MX DMA channel number
 406  */
 407 void imx_dma_free(imx_dmach_t dma_ch)
 408 {
 409         unsigned long flags;
 410         struct imx_dma_channel *imxdma = &imx_dma_channels[dma_ch];
 411
 412         if (!imxdma->name) {
 413                 printk(KERN_CRIT
 414                        "%s: trying to free channel %d which is already freed\n",
 415 <<<<<<< HEAD:arch/arm/mach-imx/dma.c
 416                        __FUNCTION__, dma_ch);
 417 =======
 418                        __func__, dma_ch);
 419 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-imx/dma.c
 420                 return;
 421         }
 422
 423         local_irq_save(flags);
 424         /* Disable interrupts */
 425         DIMR |= (1 << dma_ch);
 426         CCR(dma_ch) &= ~CCR_CEN;
 427         imxdma->name = NULL;
 428         local_irq_restore(flags);
 429 }
 430
 431 /**
 432  * imx_dma_request_by_prio - find and request some of free channels best suiting requested priority
 433  * @dma_ch: i.MX DMA channel number
 434  * @name: the driver/caller own non-%NULL identification
 435  * @prio: one of the hardware distinguished priority level:
 436  *        %DMA_PRIO_HIGH, %DMA_PRIO_MEDIUM, %DMA_PRIO_LOW
 437  *
 438  * This function tries to find free channel in the specified priority group
 439  * if the priority cannot be achieved it tries to look for free channel
 440  * in the higher and then even lower priority groups.
 441  *
 442  * Return value: If there is no free channel to allocate, -%ENODEV is returned.
 443  *               Zero value indicates successful channel allocation.
 444  */
 445 int
 446 imx_dma_request_by_prio(imx_dmach_t * pdma_ch, const char *name,
 447                         imx_dma_prio prio)
 448 {
 449         int i;
 450         int best;
 451
 452         switch (prio) {
 453         case (DMA_PRIO_HIGH):
 454                 best = 8;
 455                 break;
 456         case (DMA_PRIO_MEDIUM):
 457                 best = 4;
 458                 break;
 459         case (DMA_PRIO_LOW):
 460         default:
 461                 best = 0;
 462                 break;
 463         }
 464
 465         for (i = best; i < IMX_DMA_CHANNELS; i++) {
 466                 if (!imx_dma_request(i, name)) {
 467                         *pdma_ch = i;
 468                         return 0;
 469                 }
 470         }
 471
 472         for (i = best - 1; i >= 0; i--) {
 473                 if (!imx_dma_request(i, name)) {
 474                         *pdma_ch = i;
 475                         return 0;
 476                 }
 477         }
 478
 479 <<<<<<< HEAD:arch/arm/mach-imx/dma.c
 480         printk(KERN_ERR "%s: no free DMA channel found\n", __FUNCTION__);
 481 =======
 482         printk(KERN_ERR "%s: no free DMA channel found\n", __func__);
 483 >>>>>>> 264e3e889d86e552b4191d69bb60f4f3b383135a:arch/arm/mach-imx/dma.c
 484
 485         return -ENODEV;
 486 }
 487
 488 static irqreturn_t dma_err_handler(int irq, void *dev_id)
 489 {
 490         int i, disr = DISR;
 491         struct imx_dma_channel *channel;
 492         unsigned int err_mask = DBTOSR | DRTOSR | DSESR | DBOSR;
 493         int errcode;
 494
 495         DISR = disr & err_mask;
 496         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 497                 if(!(err_mask & (1 << i)))
 498                         continue;
 499                 channel = &imx_dma_channels[i];
 500                 errcode = 0;
 501
 502                 if (DBTOSR & (1 << i)) {
 503                         DBTOSR = (1 << i);
 504                         errcode |= IMX_DMA_ERR_BURST;
 505                 }
 506                 if (DRTOSR & (1 << i)) {
 507                         DRTOSR = (1 << i);
 508                         errcode |= IMX_DMA_ERR_REQUEST;
 509                 }
 510                 if (DSESR & (1 << i)) {
 511                         DSESR = (1 << i);
 512                         errcode |= IMX_DMA_ERR_TRANSFER;
 513                 }
 514                 if (DBOSR & (1 << i)) {
 515                         DBOSR = (1 << i);
 516                         errcode |= IMX_DMA_ERR_BUFFER;
 517                 }
 518
 519                 /*
 520                  * The cleaning of @sg field would be questionable
 521                  * there, because its value can help to compute
 522                  * remaining/transferred bytes count in the handler
 523                  */
 524                 /*imx_dma_channels[i].sg = NULL;*/
 525
 526                 if (channel->name && channel->err_handler) {
 527                         channel->err_handler(i, channel->data, errcode);
 528                         continue;
 529                 }
 530
 531                 imx_dma_channels[i].sg = NULL;
 532
 533                 printk(KERN_WARNING
 534                        "DMA timeout on channel %d (%s) -%s%s%s%s\n",
 535                        i, channel->name,
 536                        errcode&IMX_DMA_ERR_BURST?    " burst":"",
 537                        errcode&IMX_DMA_ERR_REQUEST?  " request":"",
 538                        errcode&IMX_DMA_ERR_TRANSFER? " transfer":"",
 539                        errcode&IMX_DMA_ERR_BUFFER?   " buffer":"");
 540         }
 541         return IRQ_HANDLED;
 542 }
 543
 544 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
 545 {
 546         int i, disr = DISR;
 547
 548         pr_debug("imxdma: dma_irq_handler called, disr=0x%08x\n",
 549                      disr);
 550
 551         DISR = disr;
 552         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 553                 if (disr & (1 << i)) {
 554                         struct imx_dma_channel *channel = &imx_dma_channels[i];
 555                         if (channel->name) {
 556                                 if (imx_dma_sg_next(i, CNTR(i))) {
 557                                         CCR(i) &= ~CCR_CEN;
 558                                         mb();
 559                                         CCR(i) |= CCR_CEN;
 560                                 } else {
 561                                         if (channel->irq_handler)
 562                                                 channel->irq_handler(i,
 563                                                         channel->data);
 564                                 }
 565                         } else {
 566                                 /*
 567                                  * IRQ for an unregistered DMA channel:
 568                                  * let's clear the interrupts and disable it.
 569                                  */
 570                                 printk(KERN_WARNING
 571                                        "spurious IRQ for DMA channel %d\n", i);
 572                         }
 573                 }
 574         }
 575         return IRQ_HANDLED;
 576 }
 577
 578 static int __init imx_dma_init(void)
 579 {
 580         int ret;
 581         int i;
 582
 583         /* reset DMA module */
 584         DCR = DCR_DRST;
 585
 586         ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
 587         if (ret) {
 588                 printk(KERN_CRIT "Wow!  Can't register IRQ for DMA\n");
 589                 return ret;
 590         }
 591
 592         ret = request_irq(DMA_ERR, dma_err_handler, 0, "DMA", NULL);
 593         if (ret) {
 594                 printk(KERN_CRIT "Wow!  Can't register ERRIRQ for DMA\n");
 595                 free_irq(DMA_INT, NULL);
 596         }
 597
 598         /* enable DMA module */
 599         DCR = DCR_DEN;
 600
 601         /* clear all interrupts */
 602         DISR = (1 << IMX_DMA_CHANNELS) - 1;
 603
 604         /* enable interrupts */
 605         DIMR = (1 << IMX_DMA_CHANNELS) - 1;
 606
 607         for (i = 0; i < IMX_DMA_CHANNELS; i++) {
 608                 imx_dma_channels[i].sg = NULL;
 609                 imx_dma_channels[i].dma_num = i;
 610         }
 611
 612         return ret;
 613 }
 614
 615 arch_initcall(imx_dma_init);
 616
 617 EXPORT_SYMBOL(imx_dma_setup_single);
 618 EXPORT_SYMBOL(imx_dma_setup_sg);
 619 EXPORT_SYMBOL(imx_dma_setup_handlers);
 620 EXPORT_SYMBOL(imx_dma_enable);
 621 EXPORT_SYMBOL(imx_dma_disable);
 622 EXPORT_SYMBOL(imx_dma_request);
 623 EXPORT_SYMBOL(imx_dma_free);
 624 EXPORT_SYMBOL(imx_dma_request_by_prio);
 625 EXPORT_SYMBOL(imx_dma_channels);