1 /*****************************************************************************
2 * fastmemcpy.h : fast memcpy routines
3 *****************************************************************************
6 * Authors: various Linux kernel hackers
7 * various MPlayer hackers
8 * Nick Kurshev <nickols_k@mail.ru>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301, USA.
23 *****************************************************************************/
26 aclib - advanced C library ;)
27 This file contains functions which improve and expand standard C-library
30 #define BLOCK_SIZE 4096
31 #define CONFUSION_FACTOR 0
32 /*Feel free to fine-tune the above 2, it might be possible to get some speedup with them :)*/
34 /*#define STATISTICS*/
38 P3 processor has only one SSE decoder so can execute only 1 sse insn per
39 cpu clock, but it has 3 mmx decoders (include load/store unit)
40 and executes 3 mmx insns per cpu clock.
41 P4 processor has some chances, but after reading:
42 http://www.emulators.com/pentium4.htm
43 I have doubts. Anyway SSE2 version of this code can be written better.
50 This part of code was taken by me from Linux-2.4.3 and slightly modified
51 for MMX, MMX2, SSE instruction set. I have done it since linux uses page aligned
52 blocks but mplayer uses weakly ordered data and original sources can not
53 speedup them. Only using PREFETCHNTA and MOVNTQ together have effect!
55 >From IA-32 Intel Architecture Software Developer's Manual Volume 1,
58 "10.4.6. Cacheability Control, Prefetch, and Memory Ordering Instructions"
60 Data referenced by a program can be temporal (data will be used again) or
61 non-temporal (data will be referenced once and not reused in the immediate
62 future). To make efficient use of the processor's caches, it is generally
63 desirable to cache temporal data and not cache non-temporal data. Overloading
64 the processor's caches with non-temporal data is sometimes referred to as
65 "polluting the caches".
66 The non-temporal data is written to memory with Write-Combining semantics.
68 The PREFETCHh instructions permits a program to load data into the processor
69 at a suggested cache level, so that it is closer to the processors load and
70 store unit when it is needed. If the data is already present in a level of
71 the cache hierarchy that is closer to the processor, the PREFETCHh instruction
72 will not result in any data movement.
73 But we should you PREFETCHNTA: Non-temporal data fetch data into location
74 close to the processor, minimizing cache pollution.
76 The MOVNTQ (store quadword using non-temporal hint) instruction stores
77 packed integer data from an MMX register to memory, using a non-temporal hint.
78 The MOVNTPS (store packed single-precision floating-point values using
79 non-temporal hint) instruction stores packed floating-point data from an
80 XMM register to memory, using a non-temporal hint.
82 The SFENCE (Store Fence) instruction controls write ordering by creating a
83 fence for memory store operations. This instruction guarantees that the results
84 of every store instruction that precedes the store fence in program order is
85 globally visible before any store instruction that follows the fence. The
86 SFENCE instruction provides an efficient way of ensuring ordering between
87 procedures that produce weakly-ordered data and procedures that consume that
90 If you have questions please contact with me: Nick Kurshev: nickols_k@mail.ru.
93 /* 3dnow memcpy support from kernel 2.4.2 */
94 /* by Pontscho/fresh!mindworkz */
96 #if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX )
99 #if defined(HAVE_MMX) && !defined(HAVE_MMX2) && !defined(HAVE_3DNOW) && !defined(HAVE_SSE)
100 /* means: mmx v.1. Note: Since we added alignment of destinition it speedups
101 of memory copying on PentMMX, Celeron-1 and P2 upto 12% versus
102 standard (non MMX-optimized) version.
103 Note: on K6-2+ it speedups memory copying upto 25% and
104 on K7 and P3 about 500% (5 times). */
110 #if !defined( HAVE_MMX2) && defined( HAVE_3DNOW)
111 #define HAVE_K6_2PLUS
114 /* for small memory blocks (<256 bytes) this version is faster */
115 #define small_memcpy(to,from,n)\
117 register unsigned long int dummy;\
118 __asm__ __volatile__(\
120 :"=&D"(to), "=&S"(from), "=&c"(dummy)\
121 /* It's most portable way to notify compiler */\
122 /* that edi, esi and ecx are clobbered in asm block. */\
123 /* Thanks to A'rpi for hint!!! */\
124 :"0" (to), "1" (from),"2" (n)\
129 #define MMREG_SIZE 16
131 #define MMREG_SIZE 64 /*8*/
134 /* Small defines (for readability only) ;) */
136 #define PREFETCH "prefetch"
137 /* On K6 femms is faster of emms. On K7 femms is directly mapped on emms. */
140 #define PREFETCH "prefetchnta"
145 #define MOVNTQ "movntq"
147 #define MOVNTQ "movq"
151 #define MIN_LEN 0x800 /* 2K blocks */
153 #define MIN_LEN 0x40 /* 64-byte blocks */
156 static void * fast_memcpy(void * to
, const void * from
, size_t len
)
166 for(i
=0; len
>(1<<i
); i
++);
169 if(1024*1024*1024 % t
== 0)
171 printf("freq < %8d %4d\n", 1<<i
, freq
[i
]);
175 /* PREFETCH has effect even for MOVSB instruction ;) */
176 __asm__
__volatile__ (
186 register unsigned long int delta
;
187 /* Align destinition to MMREG_SIZE -boundary */
188 delta
= ((unsigned long int)to
)&(MMREG_SIZE
-1);
191 delta
=MMREG_SIZE
-delta
;
193 small_memcpy(to
, from
, delta
);
195 i
= len
>> 6; /* len/64 */
198 This algorithm is top effective when the code consequently
199 reads and writes blocks which have size of cache line.
200 Size of cache line is processor-dependent.
201 It will, however, be a minimum of 32 bytes on any processors.
202 It would be better to have a number of instructions which
203 perform reading and writing to be multiple to a number of
204 processor's decoders, but it's not always possible.
206 #ifdef HAVE_SSE /* Only P3 (may be Cyrix3) */
207 if(((unsigned long)from
) & 15)
208 /* if SRC is misaligned */
211 __asm__
__volatile__ (
213 "movups (%0), %%xmm0\n"
214 "movups 16(%0), %%xmm1\n"
215 "movups 32(%0), %%xmm2\n"
216 "movups 48(%0), %%xmm3\n"
217 "movntps %%xmm0, (%1)\n"
218 "movntps %%xmm1, 16(%1)\n"
219 "movntps %%xmm2, 32(%1)\n"
220 "movntps %%xmm3, 48(%1)\n"
221 :: "r" (from
), "r" (to
) : "memory");
222 ((const unsigned char *)from
)+=64;
223 ((unsigned char *)to
)+=64;
227 Only if SRC is aligned on 16-byte boundary.
228 It allows using movaps instead of movups, which required data
229 to be aligned or a general-protection exception (#GP) is generated.
233 __asm__
__volatile__ (
235 "movaps (%0), %%xmm0\n"
236 "movaps 16(%0), %%xmm1\n"
237 "movaps 32(%0), %%xmm2\n"
238 "movaps 48(%0), %%xmm3\n"
239 "movntps %%xmm0, (%1)\n"
240 "movntps %%xmm1, 16(%1)\n"
241 "movntps %%xmm2, 32(%1)\n"
242 "movntps %%xmm3, 48(%1)\n"
243 :: "r" (from
), "r" (to
) : "memory");
244 ((const unsigned char *)from
)+=64;
245 ((unsigned char *)to
)+=64;
248 /* Align destination at BLOCK_SIZE boundary */
249 for(; ((uintptr_t)to
& (BLOCK_SIZE
-1)) && i
>0; i
--)
251 __asm__
__volatile__ (
256 "movq 8(%0), %%mm1\n"
257 "movq 16(%0), %%mm2\n"
258 "movq 24(%0), %%mm3\n"
259 "movq 32(%0), %%mm4\n"
260 "movq 40(%0), %%mm5\n"
261 "movq 48(%0), %%mm6\n"
262 "movq 56(%0), %%mm7\n"
263 MOVNTQ
" %%mm0, (%1)\n"
264 MOVNTQ
" %%mm1, 8(%1)\n"
265 MOVNTQ
" %%mm2, 16(%1)\n"
266 MOVNTQ
" %%mm3, 24(%1)\n"
267 MOVNTQ
" %%mm4, 32(%1)\n"
268 MOVNTQ
" %%mm5, 40(%1)\n"
269 MOVNTQ
" %%mm6, 48(%1)\n"
270 MOVNTQ
" %%mm7, 56(%1)\n"
271 :: "r" (from
), "r" (to
) : "memory");
272 from
= (const void *) (((const unsigned char *)from
)+64);
273 to
= (void *) (((unsigned char *)to
)+64);
276 /* printf(" %p %p\n", (uintptr_t)from&1023, (uintptr_t)to&1023); */
277 /* Pure Assembly cuz gcc is a bit unpredictable ;) */
281 "xorl %%eax, %%eax \n\t"
284 "movl (%0, %%eax), %%ebx \n\t"
285 "movl 32(%0, %%eax), %%ebx \n\t"
286 "movl 64(%0, %%eax), %%ebx \n\t"
287 "movl 96(%0, %%eax), %%ebx \n\t"
288 "addl $128, %%eax \n\t"
289 "cmpl %3, %%eax \n\t"
292 "xorl %%eax, %%eax \n\t"
296 "movq (%0, %%eax), %%mm0\n"
297 "movq 8(%0, %%eax), %%mm1\n"
298 "movq 16(%0, %%eax), %%mm2\n"
299 "movq 24(%0, %%eax), %%mm3\n"
300 "movq 32(%0, %%eax), %%mm4\n"
301 "movq 40(%0, %%eax), %%mm5\n"
302 "movq 48(%0, %%eax), %%mm6\n"
303 "movq 56(%0, %%eax), %%mm7\n"
304 MOVNTQ
" %%mm0, (%1, %%eax)\n"
305 MOVNTQ
" %%mm1, 8(%1, %%eax)\n"
306 MOVNTQ
" %%mm2, 16(%1, %%eax)\n"
307 MOVNTQ
" %%mm3, 24(%1, %%eax)\n"
308 MOVNTQ
" %%mm4, 32(%1, %%eax)\n"
309 MOVNTQ
" %%mm5, 40(%1, %%eax)\n"
310 MOVNTQ
" %%mm6, 48(%1, %%eax)\n"
311 MOVNTQ
" %%mm7, 56(%1, %%eax)\n"
312 "addl $64, %%eax \n\t"
313 "cmpl %3, %%eax \n\t"
316 #if CONFUSION_FACTOR > 0
317 /* a few percent speedup on out of order executing CPUs */
318 "movl %5, %%eax \n\t"
320 "movl (%0), %%ebx \n\t"
321 "movl (%0), %%ebx \n\t"
322 "movl (%0), %%ebx \n\t"
323 "movl (%0), %%ebx \n\t"
328 "xorl %%eax, %%eax \n\t"
334 : "+r" (from
), "+r" (to
), "+r" (i
)
335 : "r" (BLOCK_SIZE
), "i" (BLOCK_SIZE
/64), "i" (CONFUSION_FACTOR
)
342 __asm__
__volatile__ (
347 "movq 8(%0), %%mm1\n"
348 "movq 16(%0), %%mm2\n"
349 "movq 24(%0), %%mm3\n"
350 "movq 32(%0), %%mm4\n"
351 "movq 40(%0), %%mm5\n"
352 "movq 48(%0), %%mm6\n"
353 "movq 56(%0), %%mm7\n"
354 MOVNTQ
" %%mm0, (%1)\n"
355 MOVNTQ
" %%mm1, 8(%1)\n"
356 MOVNTQ
" %%mm2, 16(%1)\n"
357 MOVNTQ
" %%mm3, 24(%1)\n"
358 MOVNTQ
" %%mm4, 32(%1)\n"
359 MOVNTQ
" %%mm5, 40(%1)\n"
360 MOVNTQ
" %%mm6, 48(%1)\n"
361 MOVNTQ
" %%mm7, 56(%1)\n"
362 :: "r" (from
), "r" (to
) : "memory");
363 from
= (const void *) (((const unsigned char *)from
)+64);
364 to
= (void *) (((unsigned char *)to
)+64);
367 #endif /* Have SSE */
369 /* since movntq is weakly-ordered, a "sfence"
370 * is needed to become ordered again. */
371 __asm__
__volatile__ ("sfence":::"memory");
374 /* enables to use FPU */
375 __asm__
__volatile__ (EMMS:::"memory");
379 * Now do the tail of the block
381 if(len
) small_memcpy(to
, from
, len
);
386 #endif /* #if defined( HAVE_MMX2 ) || defined( HAVE_3DNOW ) || defined( HAVE_MMX ) */