More arm64 isel tuning: create {and,orr,eor,add,sub} reg,reg,reg-shifted-by-imm

More arm64 isel tuning: create {and,orr,eor,add,sub} reg,reg,reg-shifted-by-imm

Thus far the arm64 isel can't generate instructions of the form

   {and,or,xor,add,sub} reg,reg,reg-shifted-by-imm

and hence sometimes winds up generating pairs like

   lsh x2, x1, #13 ; orr x4, x3, x2

when instead it could just have generated

   orr x4, x3, x1, lsh #13

This commit fixes that, although only for the 64-bit case, not the 32-bit
case.  Specifically, it can transform the IR forms

  {Add,Sub,And,Or,Xor}(E1, {Shl,Shr,Sar}(E2, immediate))   and
  {Add,And,Or,Xor}({Shl,Shr,Sar}(E1, immediate), E2)

into a single arm64 instruction.  Note that `Sub` is not included in the
second line, because shifting the first operand requires inverting the arg
order in the arm64 instruction, which isn't allowable with `Sub`, since it's
not commutative and arm64 doesn't offer us a reverse-subtract instruction to
use instead.

This gives a 1.1% reduction generated code size when running
/usr/bin/date on Memcheck.