| commit | 2471e0521da06200bd9d553b4d17750af2852bb0 | |
| author | Julian Seward <jseward@acm.org> | |
| Fri, 30 Oct 2020 16:34:14 +0000 (30 17:34 +0100) | ||
| committer | Julian Seward <jseward@acm.org> | |
| Fri, 30 Oct 2020 16:34:14 +0000 (30 17:34 +0100) | ||
| tree | d8889c987e8eca38a6170a231b17a74178a2abe7 | treesnapshot (tar.gz zip) |
| parent | 3073d03e4b6e76797828b3f466863dbdda76cc7a | commitdiff |
arm64 front end: mark a couple of vector load/store insns as "verbose".
Mark
LD3/ST3 (multiple 3-elem structs to/from 3 regs
LD4/ST4 (multiple 4-elem structs to/from 4 regs
as "verbose", since they can generate so much IR that a long sequence
of them causes later stages of the JIT to run out of space.
Mark
LD3/ST3 (multiple 3-elem structs to/from 3 regs
LD4/ST4 (multiple 4-elem structs to/from 4 regs
as "verbose", since they can generate so much IR that a long sequence
of them causes later stages of the JIT to run out of space.
| VEX/priv/guest_arm64_toIR.c | diffblobblamehistory |