VEX/pub/libvex.h

   1
   2 /*---------------------------------------------------------------*/
   3 /*--- begin                                          libvex.h ---*/
   4 /*---------------------------------------------------------------*/
   5
   6 /*
   7    This file is part of Valgrind, a dynamic binary instrumentation
   8    framework.
   9
  10    Copyright (C) 2004-2017 OpenWorks LLP
  11       info@open-works.net
  12
  13    This program is free software; you can redistribute it and/or
  14    modify it under the terms of the GNU General Public License as
  15    published by the Free Software Foundation; either version 2 of the
  16    License, or (at your option) any later version.
  17
  18    This program is distributed in the hope that it will be useful, but
  19    WITHOUT ANY WARRANTY; without even the implied warranty of
  20    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  21    General Public License for more details.
  22
  23    You should have received a copy of the GNU General Public License
  24    along with this program; if not, see <http://www.gnu.org/licenses/>.
  25
  26    The GNU General Public License is contained in the file COPYING.
  27
  28    Neither the names of the U.S. Department of Energy nor the
  29    University of California nor the names of its contributors may be
  30    used to endorse or promote products derived from this software
  31    without prior written permission.
  32 */
  33
  34 #ifndef __LIBVEX_H
  35 #define __LIBVEX_H
  36
  37
  38 #include "libvex_basictypes.h"
  39 #include "libvex_ir.h"
  40
  41
  42 /*---------------------------------------------------------------*/
  43 /*--- This file defines the top-level interface to LibVEX.    ---*/
  44 /*---------------------------------------------------------------*/
  45
  46 /*-------------------------------------------------------*/
  47 /*--- Architectures, variants, and other arch info    ---*/
  48 /*-------------------------------------------------------*/
  49
  50 typedef
  51    enum {
  52       VexArch_INVALID=0x400,
  53       VexArchX86,
  54       VexArchAMD64,
  55       VexArchARM,
  56       VexArchARM64,
  57       VexArchPPC32,
  58       VexArchPPC64,
  59       VexArchS390X,
  60       VexArchMIPS32,
  61       VexArchMIPS64,
  62       VexArchNANOMIPS,
  63    }
  64    VexArch;
  65
  66
  67 /* Information about endianness. */
  68 typedef
  69    enum {
  70       VexEndness_INVALID=0x600, /* unknown endianness */
  71       VexEndnessLE,             /* little endian */
  72       VexEndnessBE              /* big endian */
  73    }
  74    VexEndness;
  75
  76
  77 /* For a given architecture, these specify extra capabilities beyond
  78    the minimum supported (baseline) capabilities.  They may be OR'd
  79    together, although some combinations don't make sense.  (eg, SSE2
  80    but not SSE1).  LibVEX_Translate will check for nonsensical
  81    combinations. */
  82
  83 /* x86: baseline capability is Pentium-1 (FPU, MMX, but no SSE), with
  84    cmpxchg8b. MMXEXT is a special AMD only subset of SSE1 (Integer SSE). */
  85 #define VEX_HWCAPS_X86_MMXEXT  (1<<1)  /* A subset of SSE1 on early AMD */
  86 #define VEX_HWCAPS_X86_SSE1    (1<<2)  /* SSE1 support (Pentium III) */
  87 #define VEX_HWCAPS_X86_SSE2    (1<<3)  /* SSE2 support (Pentium 4) */
  88 #define VEX_HWCAPS_X86_SSE3    (1<<4)  /* SSE3 support (>= Prescott) */
  89 #define VEX_HWCAPS_X86_LZCNT   (1<<5)  /* SSE4a LZCNT insn */
  90
  91 /* amd64: baseline capability is SSE2, with cmpxchg8b but not
  92    cmpxchg16b. */
  93 #define VEX_HWCAPS_AMD64_SSE3   (1<<5)  /* SSE3 support */
  94 #define VEX_HWCAPS_AMD64_SSSE3  (1<<12) /* Supplemental SSE3 support */
  95 #define VEX_HWCAPS_AMD64_CX16   (1<<6)  /* cmpxchg16b support */
  96 #define VEX_HWCAPS_AMD64_LZCNT  (1<<7)  /* SSE4a LZCNT insn */
  97 #define VEX_HWCAPS_AMD64_AVX    (1<<8)  /* AVX instructions */
  98 #define VEX_HWCAPS_AMD64_RDTSCP (1<<9)  /* RDTSCP instruction */
  99 #define VEX_HWCAPS_AMD64_BMI    (1<<10) /* BMI1 instructions */
 100 #define VEX_HWCAPS_AMD64_AVX2   (1<<11) /* AVX2 instructions */
 101 #define VEX_HWCAPS_AMD64_RDRAND (1<<13) /* RDRAND instructions */
 102 #define VEX_HWCAPS_AMD64_F16C   (1<<14) /* F16C instructions */
 103 #define VEX_HWCAPS_AMD64_RDSEED (1<<15) /* RDSEED instructions */
 104 #define VEX_HWCAPS_AMD64_FMA3   (1<<16) /* FMA3 instructions */
 105 #define VEX_HWCAPS_AMD64_FMA4   (1<<17) /* FMA4 instructions */
 106
 107 /* ppc32: baseline capability is integer only */
 108 #define VEX_HWCAPS_PPC32_F     (1<<8)  /* basic (non-optional) FP */
 109 #define VEX_HWCAPS_PPC32_V     (1<<9)  /* Altivec (VMX) */
 110 #define VEX_HWCAPS_PPC32_FX    (1<<10) /* FP extns (fsqrt, fsqrts) */
 111 #define VEX_HWCAPS_PPC32_GX    (1<<11) /* Graphics extns
 112                                           (fres,frsqrte,fsel,stfiwx) */
 113 #define VEX_HWCAPS_PPC32_VX    (1<<12) /* Vector-scalar floating-point (VSX); implies ISA 2.06 or higher  */
 114 #define VEX_HWCAPS_PPC32_DFP   (1<<17) /* Decimal Floating Point (DFP) -- e.g., dadd */
 115 #define VEX_HWCAPS_PPC32_ISA2_07   (1<<19) /* ISA 2.07 -- e.g., mtvsrd */
 116 #define VEX_HWCAPS_PPC32_ISA3_0    (1<<21) /* ISA 3.0  -- e.g., cnttzw */
 117 #define VEX_HWCAPS_PPC32_ISA3_1    (1<<22) /* ISA 3.1  -- e.g., brh */
 118 /* ISA 3.1 not supported in 32-bit mode */
 119
 120 /* ppc64: baseline capability is integer and basic FP insns */
 121 #define VEX_HWCAPS_PPC64_V     (1<<13) /* Altivec (VMX) */
 122 #define VEX_HWCAPS_PPC64_FX    (1<<14) /* FP extns (fsqrt, fsqrts) */
 123 #define VEX_HWCAPS_PPC64_GX    (1<<15) /* Graphics extns
 124                                           (fres,frsqrte,fsel,stfiwx) */
 125 #define VEX_HWCAPS_PPC64_VX    (1<<16) /* Vector-scalar floating-point (VSX); implies ISA 2.06 or higher  */
 126 #define VEX_HWCAPS_PPC64_DFP   (1<<18) /* Decimal Floating Point (DFP) -- e.g., dadd */
 127 #define VEX_HWCAPS_PPC64_ISA2_07   (1<<20) /* ISA 2.07 -- e.g., mtvsrd */
 128 #define VEX_HWCAPS_PPC64_ISA3_0    (1<<22) /* ISA 3.0  -- e.g., cnttzw */
 129 #define VEX_HWCAPS_PPC64_ISA3_1    (1<<23) /* ISA 3.1  -- e.g., brh */
 130 #define VEX_HWCAPS_PPC64_SCV       (1<<24) /* ISA 3.0, Kernel supports scv
 131                                               instruction. */
 132
 133 /* s390x: Hardware capability encoding
 134
 135    Bits [26:31] encode the machine model (see VEX_S390X_MODEL... below)
 136    Bits [0:20]  encode specific hardware capabilities
 137                 (see VEX_HWAPS_S390X_... below)
 138 */
 139
 140 /* Model numbers must be assigned in chronological order.
 141    They are used as array index. */
 142 #define VEX_S390X_MODEL_Z900     0
 143 #define VEX_S390X_MODEL_Z800     1
 144 #define VEX_S390X_MODEL_Z990     2
 145 #define VEX_S390X_MODEL_Z890     3
 146 #define VEX_S390X_MODEL_Z9_EC    4
 147 #define VEX_S390X_MODEL_Z9_BC    5
 148 #define VEX_S390X_MODEL_Z10_EC   6
 149 #define VEX_S390X_MODEL_Z10_BC   7
 150 #define VEX_S390X_MODEL_Z196     8
 151 #define VEX_S390X_MODEL_Z114     9
 152 #define VEX_S390X_MODEL_ZEC12    10
 153 #define VEX_S390X_MODEL_ZBC12    11
 154 #define VEX_S390X_MODEL_Z13      12
 155 #define VEX_S390X_MODEL_Z13S     13
 156 #define VEX_S390X_MODEL_Z14      14
 157 #define VEX_S390X_MODEL_Z14_ZR1  15
 158 #define VEX_S390X_MODEL_Z15      16
 159 #define VEX_S390X_MODEL_Z16      17
 160 #define VEX_S390X_MODEL_UNKNOWN  18     /* always last in list */
 161 #define VEX_S390X_MODEL_MASK     0x3F
 162
 163 #define VEX_HWCAPS_S390X_LDISP (1<<6)   /* Long-displacement facility */
 164 #define VEX_HWCAPS_S390X_EIMM  (1<<7)   /* Extended-immediate facility */
 165 #define VEX_HWCAPS_S390X_GIE   (1<<8)   /* General-instruction-extension facility */
 166 #define VEX_HWCAPS_S390X_DFP   (1<<9)   /* Decimal floating point facility */
 167 #define VEX_HWCAPS_S390X_FGX   (1<<10)  /* FPR-GR transfer facility */
 168 #define VEX_HWCAPS_S390X_ETF2  (1<<11)  /* ETF2-enhancement facility */
 169 #define VEX_HWCAPS_S390X_STFLE (1<<12)  /* STFLE facility */
 170 #define VEX_HWCAPS_S390X_ETF3  (1<<13)  /* ETF3-enhancement facility */
 171 #define VEX_HWCAPS_S390X_STCKF (1<<14)  /* STCKF facility */
 172 #define VEX_HWCAPS_S390X_FPEXT (1<<15)  /* Floating point extension facility */
 173 #define VEX_HWCAPS_S390X_LSC   (1<<16)  /* Conditional load/store facility */
 174 #define VEX_HWCAPS_S390X_PFPO  (1<<17)  /* Perform floating point ops facility */
 175 #define VEX_HWCAPS_S390X_VX    (1<<18)  /* Vector facility */
 176 #define VEX_HWCAPS_S390X_MSA5  (1<<19)  /* message security assistance facility */
 177 #define VEX_HWCAPS_S390X_MI2   (1<<20)  /* miscellaneous-instruction-extensions facility 2 */
 178 #define VEX_HWCAPS_S390X_LSC2  (1<<21)  /* Conditional load/store facility2 */
 179 #define VEX_HWCAPS_S390X_VXE   (1<<22)  /* Vector-enhancements facility */
 180 #define VEX_HWCAPS_S390X_NNPA  (1<<23)  /* NNPA facility */
 181
 182 /* Special value representing all available s390x hwcaps */
 183 #define VEX_HWCAPS_S390X_ALL   (VEX_HWCAPS_S390X_LDISP | \
 184                                 VEX_HWCAPS_S390X_EIMM  | \
 185                                 VEX_HWCAPS_S390X_GIE   | \
 186                                 VEX_HWCAPS_S390X_DFP   | \
 187                                 VEX_HWCAPS_S390X_FGX   | \
 188                                 VEX_HWCAPS_S390X_STFLE | \
 189                                 VEX_HWCAPS_S390X_STCKF | \
 190                                 VEX_HWCAPS_S390X_FPEXT | \
 191                                 VEX_HWCAPS_S390X_LSC   | \
 192                                 VEX_HWCAPS_S390X_ETF3  | \
 193                                 VEX_HWCAPS_S390X_ETF2  | \
 194                                 VEX_HWCAPS_S390X_PFPO  | \
 195                                 VEX_HWCAPS_S390X_VX    | \
 196                                 VEX_HWCAPS_S390X_MSA5  | \
 197                                 VEX_HWCAPS_S390X_MI2   | \
 198                                 VEX_HWCAPS_S390X_LSC2  | \
 199                                 VEX_HWCAPS_S390X_VXE   | \
 200                                 VEX_HWCAPS_S390X_NNPA)
 201
 202 #define VEX_HWCAPS_S390X(x)  ((x) & ~VEX_S390X_MODEL_MASK)
 203 #define VEX_S390X_MODEL(x)   ((x) &  VEX_S390X_MODEL_MASK)
 204
 205 /* arm: baseline capability is ARMv4 */
 206 /* Bits 5:0 - architecture level (e.g. 5 for v5, 6 for v6 etc) */
 207 #define VEX_HWCAPS_ARM_VFP    (1<<6)  /* VFP extension */
 208 #define VEX_HWCAPS_ARM_VFP2   (1<<7)  /* VFPv2 */
 209 #define VEX_HWCAPS_ARM_VFP3   (1<<8)  /* VFPv3 */
 210 /* Bits 15:10 reserved for (possible) future VFP revisions */
 211 #define VEX_HWCAPS_ARM_NEON   (1<<16) /* Advanced SIMD also known as NEON */
 212
 213 /* Get an ARM architecure level from HWCAPS */
 214 #define VEX_ARM_ARCHLEVEL(x) ((x) & 0x3f)
 215
 216 /* ARM64: baseline capability is AArch64 v8. */
 217 #define VEX_HWCAPS_ARM64_FHM         (1 << 4)
 218 #define VEX_HWCAPS_ARM64_DPBCVAP     (1 << 5)
 219 #define VEX_HWCAPS_ARM64_DPBCVADP    (1 << 6)
 220 #define VEX_HWCAPS_ARM64_SM3         (1 << 7)
 221 #define VEX_HWCAPS_ARM64_SM4         (1 << 8)
 222 #define VEX_HWCAPS_ARM64_SHA3        (1 << 9)
 223 #define VEX_HWCAPS_ARM64_RDM         (1 << 10)
 224 #define VEX_HWCAPS_ARM64_ATOMICS     (1 << 11)
 225 #define VEX_HWCAPS_ARM64_I8MM        (1 << 12)
 226 #define VEX_HWCAPS_ARM64_BF16        (1 << 13)
 227 #define VEX_HWCAPS_ARM64_FP16        (1 << 14)
 228 #define VEX_HWCAPS_ARM64_VFP16       (1 << 15)
 229
 230 /* MIPS baseline capability */
 231 /* Assigned Company values for bits 23:16 of the PRId Register
 232    (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
 233    MTI, the PRId register is defined in this (backwards compatible)
 234    way:
 235
 236   +----------------+----------------+----------------+----------------+
 237   | Company Options| Company ID     | Processor ID   | Revision       |
 238   +----------------+----------------+----------------+----------------+
 239    31            24 23            16 15             8 7
 240
 241 */
 242
 243 #define VEX_PRID_COMP_LEGACY      0x00000000
 244 #define VEX_PRID_COMP_MIPS        0x00010000
 245 #define VEX_PRID_COMP_BROADCOM    0x00020000
 246 #define VEX_PRID_COMP_NETLOGIC    0x000C0000
 247 #define VEX_PRID_COMP_CAVIUM      0x000D0000
 248 #define VEX_PRID_COMP_INGENIC_E1  0x00E10000        /* JZ4780 */
 249
 250 /*
 251  * These are valid when 23:16 == PRID_COMP_LEGACY
 252  */
 253 #define VEX_PRID_IMP_LOONGSON_64        0x6300  /* Loongson-2/3 */
 254
 255 /*
 256  * These are the PRID's for when 23:16 == PRID_COMP_MIPS
 257  */
 258 #define VEX_PRID_IMP_34K                0x9500
 259 #define VEX_PRID_IMP_74K                0x9700
 260 #define VEX_PRID_IMP_P5600              0xa800
 261
 262 /*
 263  * Instead of Company Options values, bits 31:24 will be packed with
 264  * additional information, such as isa level and FP mode.
 265  */
 266 #define VEX_MIPS_CPU_ISA_M32R1      0x01000000
 267 #define VEX_MIPS_CPU_ISA_M32R2      0x02000000
 268 #define VEX_MIPS_CPU_ISA_M64R1      0x04000000
 269 #define VEX_MIPS_CPU_ISA_M64R2      0x08000000
 270 #define VEX_MIPS_CPU_ISA_M32R6      0x10000000
 271 #define VEX_MIPS_CPU_ISA_M64R6      0x20000000
 272 /* FP mode is FR = 1 (32 dbl. prec. FP registers) */
 273 #define VEX_MIPS_HOST_FR            0x40000000
 274 /* Get MIPS Extended Information */
 275 #define VEX_MIPS_EX_INFO(x) ((x) & 0xFF000000)
 276 /* Get MIPS Company ID from HWCAPS */
 277 #define VEX_MIPS_COMP_ID(x) ((x) & 0x00FF0000)
 278 /* Get MIPS Processor ID from HWCAPS */
 279 #define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FF00)
 280 /* Get MIPS Revision from HWCAPS */
 281 #define VEX_MIPS_REV(x) ((x) & 0x000000FF)
 282 /* Get host FP mode */
 283 #define VEX_MIPS_HOST_FP_MODE(x) (!!(VEX_MIPS_EX_INFO(x) & VEX_MIPS_HOST_FR))
 284 /* Check if the processor supports MIPS32R2. */
 285 #define VEX_MIPS_CPU_HAS_MIPS32R2(x) (VEX_MIPS_EX_INFO(x) & \
 286                                       VEX_MIPS_CPU_ISA_M32R2)
 287 /* Check if the processor supports MIPS64R2. */
 288 #define VEX_MIPS_CPU_HAS_MIPS64R2(x) (VEX_MIPS_EX_INFO(x) & \
 289                                       VEX_MIPS_CPU_ISA_M64R2)
 290 /* Check if the processor supports MIPSR6. */
 291 #define VEX_MIPS_CPU_HAS_MIPSR6(x) (VEX_MIPS_EX_INFO(x) & \
 292                                     (VEX_MIPS_CPU_ISA_M32R6 | \
 293                                     VEX_MIPS_CPU_ISA_M64R6))
 294 /* Check if the processor supports DSP ASE Rev 2. */
 295 #define VEX_MIPS_PROC_DSP2(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
 296                                (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_74K))
 297 /* Check if the processor supports DSP ASE Rev 1. */
 298 #define VEX_MIPS_PROC_DSP(x)  (VEX_MIPS_PROC_DSP2(x) || \
 299                                ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
 300                                (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_34K)))
 301
 302 /* Check if the processor supports MIPS MSA (SIMD)*/
 303 #define VEX_MIPS_PROC_MSA(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \
 304                               (VEX_MIPS_PROC_ID(x) == VEX_PRID_IMP_P5600) && \
 305                               (VEX_MIPS_HOST_FP_MODE(x)))
 306
 307 /* These return statically allocated strings. */
 308
 309 extern const HChar* LibVEX_ppVexArch    ( VexArch );
 310 extern const HChar* LibVEX_ppVexEndness ( VexEndness endness );
 311 extern const HChar* LibVEX_ppVexHwCaps  ( VexArch, UInt );
 312
 313
 314 /* The various kinds of caches */
 315 typedef enum {
 316    DATA_CACHE=0x500,
 317    INSN_CACHE,
 318    UNIFIED_CACHE
 319 } VexCacheKind;
 320
 321 /* Information about a particular cache */
 322 typedef struct {
 323    VexCacheKind kind;
 324    UInt level;         /* level this cache is at, e.g. 1 for L1 cache */
 325    UInt sizeB;         /* size of this cache in bytes */
 326    UInt line_sizeB;    /* cache line size in bytes */
 327    UInt assoc;         /* set associativity */
 328    Bool is_trace_cache;  /* False, except for certain Pentium 4 models */
 329 } VexCache;
 330
 331 /* Convenience macro to initialise a VexCache */
 332 #define VEX_CACHE_INIT(_kind, _level, _size, _line_size, _assoc)         \
 333          ({ (VexCache) { .kind = _kind, .level = _level, .sizeB = _size, \
 334                .line_sizeB = _line_size, .assoc = _assoc, \
 335                .is_trace_cache = False }; })
 336
 337 /* Information about the cache system as a whole */
 338 typedef struct {
 339    UInt num_levels;
 340    UInt num_caches;
 341    /* Unordered array of caches for this host. NULL if there are
 342       no caches. The following can always be assumed:
 343       (1) There is at most one cache of a given kind per cache level.
 344       (2) If there exists a unified cache at a particular level then
 345           no other cache exists at that level.
 346       (3) The existence of a cache at level N > 1 implies the existence of
 347           at least one cache at level N-1. */
 348    VexCache *caches;
 349    Bool icaches_maintain_coherence;
 350 } VexCacheInfo;
 351
 352
 353 /* This struct is a bit of a hack, but is needed to carry misc
 354    important bits of info about an arch.  Fields which are meaningless
 355    or ignored for the platform in question should be set to zero.
 356    Nb: if you add fields to the struct make sure to update function
 357    LibVEX_default_VexArchInfo. */
 358
 359 typedef
 360    struct {
 361       /* The following three fields are mandatory. */
 362       UInt         hwcaps;
 363       VexEndness   endness;
 364       VexCacheInfo hwcache_info;
 365       /* PPC32/PPC64 only: size of instruction cache line */
 366       Int ppc_icache_line_szB;
 367       /* PPC32/PPC64 only: sizes zeroed by the dcbz/dcbzl instructions
 368          (bug#135264) */
 369       UInt ppc_dcbz_szB;
 370       /* PPC32/PPC64 only: True scv is supported */
 371       Bool ppc_scv_supported;
 372       UInt ppc_dcbzl_szB; /* 0 means unsupported (SIGILL) */
 373       /* ARM64: I- and D- minimum line sizes in log2(bytes), as
 374          obtained from ctr_el0.DminLine and .IminLine.  For example, a
 375          line size of 64 bytes would be encoded here as 6. */
 376       UInt arm64_dMinLine_lg2_szB;
 377       UInt arm64_iMinLine_lg2_szB;
 378       /* ARM64: does the host require us to use the fallback LLSC
 379          implementation? */
 380       Bool arm64_requires_fallback_LLSC;
 381    }
 382    VexArchInfo;
 383
 384 /* Write default settings info *vai. */
 385 extern
 386 void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai );
 387
 388
 389 /* This struct carries guest and host ABI variant information that may
 390    be needed.  Fields which are meaningless or ignored for the
 391    platform in question should be set to zero.
 392
 393    Settings which are believed to be correct are:
 394
 395    guest_stack_redzone_size
 396       guest is ppc32-linux                ==> 0
 397       guest is ppc64-linux                ==> 288
 398       guest is amd64-linux                ==> 128
 399       guest is other                      ==> inapplicable
 400
 401    guest_amd64_assume_fs_is_const
 402       guest is amd64-linux                ==> True
 403       guest is amd64-darwin               ==> False
 404       guest is amd64-solaris              ==> True
 405       guest is other                      ==> inapplicable
 406
 407    guest_amd64_assume_gs_is_const
 408       guest is amd64-darwin               ==> True
 409       guest is amd64-linux                ==> True
 410       guest is amd64-solaris              ==> False
 411       guest is other                      ==> inapplicable
 412
 413    guest_ppc_zap_RZ_at_blr
 414       guest is ppc64-linux                ==> True
 415       guest is ppc32-linux                ==> False
 416       guest is other                      ==> inapplicable
 417
 418    guest_ppc_zap_RZ_at_bl
 419       guest is ppc64-linux                ==> const True
 420       guest is ppc32-linux                ==> const False
 421       guest is other                      ==> inapplicable
 422
 423    guest__use_fallback_LLSC
 424       guest is mips32                     ==> applicable, default True
 425       guest is mips64                     ==> applicable, default True
 426       guest is arm64                      ==> applicable, default False
 427
 428    host_ppc_calls_use_fndescrs:
 429       host is ppc32-linux                 ==> False
 430       host is ppc64-linux                 ==> True
 431       host is other                       ==> inapplicable
 432 */
 433
 434 typedef
 435    struct {
 436       /* PPC and AMD64 GUESTS only: how many bytes below the
 437          stack pointer are validly addressible? */
 438       Int guest_stack_redzone_size;
 439
 440       /* AMD64 GUESTS only: should we translate %fs-prefixed
 441          instructions using the assumption that %fs always contains
 442          the same value? (typically zero on linux and solaris) */
 443       Bool guest_amd64_assume_fs_is_const;
 444
 445       /* AMD64 GUESTS only: should we translate %gs-prefixed
 446          instructions using the assumption that %gs always contains
 447          the same value? (typically 0x60 on darwin)? */
 448       Bool guest_amd64_assume_gs_is_const;
 449
 450       /* AMD64 GUESTS only: for a misaligned memory access, for which we should
 451          generate a trap, should we generate SigBUS (a la FreeBSD) or SIGSEGV
 452          (Linux, OSX) ?? */
 453       Bool guest_amd64_sigbus_on_misalign;
 454
 455       /* PPC GUESTS only: should we zap the stack red zone at a 'blr'
 456          (function return) ? */
 457       Bool guest_ppc_zap_RZ_at_blr;
 458
 459       /* PPC GUESTS only: should we zap the stack red zone at a 'bl'
 460          (function call) ?  Is supplied with the guest address of the
 461          target of the call since that may be significant.  If NULL,
 462          is assumed equivalent to a fn which always returns False. */
 463       Bool (*guest_ppc_zap_RZ_at_bl)(Addr);
 464
 465       /* Potentially for all guests that use LL/SC: use the fallback
 466          (synthesised) implementation rather than passing LL/SC on to
 467          the host? */
 468       Bool guest__use_fallback_LLSC;
 469
 470       /* PPC32/PPC64 HOSTS only: does '&f' give us a pointer to a
 471          function descriptor on the host, or to the function code
 472          itself?  True => descriptor, False => code. */
 473       Bool host_ppc_calls_use_fndescrs;
 474
 475       /* MIPS32/MIPS64 GUESTS only: emulated FPU mode. */
 476       UInt guest_mips_fp_mode;
 477    }
 478    VexAbiInfo;
 479
 480 /* Write default settings info *vbi. */
 481 extern
 482 void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi );
 483
 484
 485 /*-------------------------------------------------------*/
 486 /*--- Control of Vex's optimiser (iropt).             ---*/
 487 /*-------------------------------------------------------*/
 488
 489
 490 /* VexRegisterUpdates specifies when to ensure that the guest state is
 491    up to date, in order of increasing accuracy but increasing expense.
 492
 493      VexRegUpdSpAtMemAccess: all registers are updated at superblock
 494      exits, and SP is also up to date at memory exception points.  The
 495      SP is described by the arch specific functions
 496      guest_<arch>_state_requires_precise_mem_exns.
 497
 498      VexRegUpdUnwindregsAtMemAccess: registers needed to make a stack
 499      trace are up to date at memory exception points.  Typically,
 500      these are PC/SP/FP.  The minimal registers are described by the
 501      arch specific functions guest_<arch>_state_requires_precise_mem_exns.
 502      This is what Valgrind sets as the default.
 503
 504      VexRegUpdAllregsAtMemAccess: all registers up to date at memory
 505      exception points.  This is what normally might be considered as
 506      providing "precise exceptions for memory", but does not
 507      necessarily provide precise register values at any other kind of
 508      exception.
 509
 510      VexRegUpdAllregsAtEachInsn: all registers up to date at each
 511      instruction.
 512 */
 513 typedef
 514    enum {
 515       VexRegUpd_INVALID=0x700,
 516       VexRegUpdSpAtMemAccess,
 517       VexRegUpdUnwindregsAtMemAccess,
 518       VexRegUpdAllregsAtMemAccess,
 519       VexRegUpdAllregsAtEachInsn
 520    }
 521    VexRegisterUpdates;
 522
 523 /* Control of Vex's optimiser. */
 524
 525 typedef
 526    struct {
 527       /* Controls verbosity of iropt.  0 = no output. */
 528       Int iropt_verbosity;
 529       /* Control aggressiveness of iropt.  0 = no opt, 1 = simple
 530          opts, 2 (default) = max optimisation. */
 531       Int iropt_level;
 532       /* Controls when registers are updated in guest state.  Note
 533          that this is the default value.  The VEX client can override
 534          this on a per-IRSB basis if it wants.  bb_to_IR() will query
 535          the client to ask if it wants a different setting for the
 536          block under construction, and that new setting is transported
 537          back to LibVEX_Translate, which feeds it to iropt via the
 538          various do_iropt_BB calls. */
 539       VexRegisterUpdates iropt_register_updates_default;
 540       /* How aggressive should iropt be in unrolling loops?  Higher
 541          numbers make it more enthusiastic about loop unrolling.
 542          Default=120.  A setting of zero disables unrolling.  */
 543       Int iropt_unroll_thresh;
 544       /* What's the maximum basic block length the front end(s) allow?
 545          BBs longer than this are split up.  Default=60 (guest
 546          insns). */
 547       Int guest_max_insns;
 548       /* Should Vex try to construct superblocks, by chasing unconditional
 549          branches/calls to known destinations, and performing AND/OR idiom
 550          recognition?  It is recommended to set this to True as that possibly
 551          improves performance a bit, and also is important for avoiding certain
 552          kinds of false positives in Memcheck.  Default=True.  */
 553       Bool guest_chase;
 554       /* Register allocator version. Allowed values are:
 555          - '2': previous, good and slow implementation.
 556          - '3': current, faster implementation; perhaps producing slightly worse
 557                 spilling decisions. */
 558       UInt regalloc_version;
 559    }
 560    VexControl;
 561
 562
 563 /* Write the default settings into *vcon. */
 564
 565 extern
 566 void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon );
 567
 568
 569 /*-------------------------------------------------------*/
 570 /*--- Storage management control                      ---*/
 571 /*-------------------------------------------------------*/
 572
 573 /* Allocate in Vex's temporary allocation area.  Be careful with this.
 574    You can only call it inside an instrumentation or optimisation
 575    callback that you have previously specified in a call to
 576    LibVEX_Translate.  The storage allocated will only stay alive until
 577    translation of the current basic block is complete. */
 578 extern void* LibVEX_Alloc ( SizeT nbytes );
 579
 580 /* Show Vex allocation statistics. */
 581 extern void LibVEX_ShowAllocStats ( void );
 582
 583
 584 /*-------------------------------------------------------*/
 585 /*--- Describing guest state layout                   ---*/
 586 /*-------------------------------------------------------*/
 587
 588 /* Describe the guest state enough that the instrumentation
 589    functions can work. */
 590
 591 /* The max number of guest state chunks which we can describe as
 592    always defined (for the benefit of Memcheck). */
 593 #define VEXGLO_N_ALWAYSDEFD  24
 594
 595 typedef
 596    struct {
 597       /* Total size of the guest state, in bytes.  Must be
 598          16-aligned. */
 599       Int total_sizeB;
 600       /* Whereabouts is the stack pointer? */
 601       Int offset_SP;
 602       Int sizeof_SP; /* 4 or 8 */
 603       /* Whereabouts is the frame pointer? */
 604       Int offset_FP;
 605       Int sizeof_FP; /* 4 or 8 */
 606       /* Whereabouts is the instruction pointer? */
 607       Int offset_IP;
 608       Int sizeof_IP; /* 4 or 8 */
 609       /* Describe parts of the guest state regarded as 'always
 610          defined'. */
 611       Int n_alwaysDefd;
 612       struct {
 613          Int offset;
 614          Int size;
 615       } alwaysDefd[VEXGLO_N_ALWAYSDEFD];
 616    }
 617    VexGuestLayout;
 618
 619 /* A note about guest state layout.
 620
 621    LibVEX defines the layout for the guest state, in the file
 622    pub/libvex_guest_<arch>.h.  The struct will have an 16-aligned
 623    size.  Each translated bb is assumed to be entered with a specified
 624    register pointing at such a struct.  Beyond that is two copies of
 625    the shadow state area with the same size as the struct.  Beyond
 626    that is a spill area that LibVEX may spill into.  It must have size
 627    LibVEX_N_SPILL_BYTES, and this must be a 16-aligned number.
 628
 629    On entry, the baseblock pointer register must be 16-aligned.
 630
 631    There must be no holes in between the primary guest state, its two
 632    copies, and the spill area.  In short, all 4 areas must have a
 633    16-aligned size and be 16-aligned, and placed back-to-back.
 634 */
 635
 636 #define LibVEX_N_SPILL_BYTES 4096
 637
 638 /* The size of the guest state must be a multiple of this number. */
 639 #define LibVEX_GUEST_STATE_ALIGN 16
 640
 641 /*-------------------------------------------------------*/
 642 /*--- Initialisation of the library                   ---*/
 643 /*-------------------------------------------------------*/
 644
 645 /* Initialise the library.  You must call this first. */
 646
 647 extern void LibVEX_Init (
 648
 649    /* failure exit function */
 650 #  if defined(__cplusplus) && defined(__GNUC__) && __GNUC__ <= 3
 651    /* g++ 3.x doesn't understand attributes on function parameters.
 652       See #265762. */
 653 #  else
 654    __attribute__ ((noreturn))
 655 #  endif
 656    void (*failure_exit) ( void ),
 657
 658    /* logging output function */
 659    void (*log_bytes) ( const HChar*, SizeT nbytes ),
 660
 661    /* debug paranoia level */
 662    Int debuglevel,
 663
 664    /* Control ... */
 665    const VexControl* vcon
 666 );
 667
 668
 669 /*-------------------------------------------------------*/
 670 /*--- Make a translation                              ---*/
 671 /*-------------------------------------------------------*/
 672
 673 /* Describes the outcome of a translation attempt. */
 674 typedef
 675    struct {
 676       /* overall status */
 677       enum { VexTransOK=0x800,
 678              VexTransAccessFail, VexTransOutputFull } status;
 679       /* The number of extents that have a self-check (0 to 3) */
 680       UInt n_sc_extents;
 681       /* Offset in generated code of the profile inc, or -1 if
 682          none.  Needed for later patching. */
 683       Int offs_profInc;
 684       /* Stats only: the number of guest insns included in the
 685          translation.  It may be zero (!). */
 686       UInt n_guest_instrs;
 687       /* Stats only: the number of unconditional branches incorporated into the
 688          trace. */
 689       UShort n_uncond_in_trace;
 690       /* Stats only: the number of conditional branches incorporated into the
 691          trace. */
 692       UShort n_cond_in_trace;
 693    }
 694    VexTranslateResult;
 695
 696
 697 /* Describes precisely the pieces of guest code that a translation
 698    covers.  Now that Vex can chase across BB boundaries, the old
 699    scheme of describing a chunk of guest code merely by its start
 700    address and length is inadequate.
 701
 702    This struct uses 20 bytes on a 32-bit archtecture and 32 bytes on a
 703    64-bit architecture.  Space is important as clients will have to store
 704    one of these for each translation made.
 705 */
 706 typedef
 707    struct {
 708       Addr   base[3];
 709       UShort len[3];
 710       UShort n_used;
 711    }
 712    VexGuestExtents;
 713
 714
 715 /* A structure to carry arguments for LibVEX_Translate.  There are so
 716    many of them, it seems better to have a structure. */
 717 typedef
 718    struct {
 719       /* IN: The instruction sets we are translating from and to.  And
 720          guest/host misc info. */
 721       VexArch      arch_guest;
 722       VexArchInfo  archinfo_guest;
 723       VexArch      arch_host;
 724       VexArchInfo  archinfo_host;
 725       VexAbiInfo   abiinfo_both;
 726
 727       /* IN: an opaque value which is passed as the first arg to all
 728          callback functions supplied in this struct.  Vex has no idea
 729          what's at the other end of this pointer. */
 730       void*   callback_opaque;
 731
 732       /* IN: the block to translate, and its guest address. */
 733       /* where are the actual bytes in the host's address space? */
 734       const UChar*  guest_bytes;
 735       /* where do the bytes really come from in the guest's aspace?
 736          This is the post-redirection guest address.  Not that Vex
 737          understands anything about redirection; that is all done on
 738          the Valgrind side. */
 739       Addr    guest_bytes_addr;
 740
 741       /* Is it OK to chase into this guest address?  May not be
 742          NULL. */
 743       Bool    (*chase_into_ok) ( /*callback_opaque*/void*, Addr );
 744
 745       /* OUT: which bits of guest code actually got translated */
 746       VexGuestExtents* guest_extents;
 747
 748       /* IN: a place to put the resulting code, and its size */
 749       UChar*  host_bytes;
 750       Int     host_bytes_size;
 751       /* OUT: how much of the output area is used. */
 752       Int*    host_bytes_used;
 753
 754       /* IN: optionally, two instrumentation functions.  May be
 755          NULL. */
 756       IRSB*   (*instrument1) ( /*callback_opaque*/void*,
 757                                IRSB*,
 758                                const VexGuestLayout*,
 759                                const VexGuestExtents*,
 760                                const VexArchInfo*,
 761                                IRType gWordTy, IRType hWordTy );
 762       IRSB*   (*instrument2) ( /*callback_opaque*/void*,
 763                                IRSB*,
 764                                const VexGuestLayout*,
 765                                const VexGuestExtents*,
 766                                const VexArchInfo*,
 767                                IRType gWordTy, IRType hWordTy );
 768
 769       IRSB* (*finaltidy) ( IRSB* );
 770
 771       /* IN: a callback used to ask the caller which of the extents,
 772          if any, a self check is required for.  Must not be NULL.
 773          The returned value is a bitmask with a 1 in position i indicating
 774          that the i'th extent needs a check.  Since there can be at most
 775          3 extents, the returned values must be between 0 and 7.
 776
 777          This call also gives the VEX client the opportunity to change
 778          the precision of register update preservation as performed by
 779          the IR optimiser.  Before the call, VEX will set *pxControl
 780          to hold the default register-update status value as specified
 781          by VexControl::iropt_register_updates_default as passed to
 782          LibVEX_Init at library initialisation time.  The client (in
 783          this callback) can if it wants, inspect the value and change
 784          it to something different, and that value will be used for
 785          subsequent IR optimisation of the block. */
 786       UInt (*needs_self_check)( /*callback_opaque*/void*,
 787                                 /*MAYBE_MOD*/VexRegisterUpdates* pxControl,
 788                                 const VexGuestExtents* );
 789
 790       /* IN: optionally, a callback which allows the caller to add its
 791          own IR preamble following the self-check and any other
 792          VEX-generated preamble, if any.  May be NULL.  If non-NULL,
 793          the IRSB under construction is handed to this function, which
 794          presumably adds IR statements to it.  The callback may
 795          optionally complete the block and direct bb_to_IR not to
 796          disassemble any instructions into it; this is indicated by
 797          the callback returning True.
 798       */
 799       Bool    (*preamble_function)(/*callback_opaque*/void*, IRSB*);
 800
 801       /* IN: debug: trace vex activity at various points */
 802       Int     traceflags;
 803
 804       /* IN: debug: print diagnostics when an illegal instr is detected */
 805       Bool    sigill_diag;
 806
 807       /* IN: profiling: add a 64 bit profiler counter increment to the
 808          translation? */
 809       Bool    addProfInc;
 810
 811       /* IN: address of the dispatcher entry points.  Describes the
 812          places where generated code should jump to at the end of each
 813          bb.
 814
 815          At the end of each translation, the next guest address is
 816          placed in the host's standard return register (x86: %eax,
 817          amd64: %rax, ppc32: %r3, ppc64: %r3).  Optionally, the guest
 818          state pointer register (on host x86: %ebp; amd64: %rbp;
 819          ppc32/64: r31) may be set to a VEX_TRC_ value to indicate any
 820          special action required before the next block is run.
 821
 822          Control is then passed back to the dispatcher (beyond Vex's
 823          control; caller supplies this) in the following way:
 824
 825          - On host archs which lack a link register (x86, amd64), by a
 826            jump to the host address specified in
 827            'dispatcher_assisted', if the guest state pointer has been
 828            changed so as to request some action before the next block
 829            is run, or 'dispatcher_unassisted' (the fast path), in
 830            which it is assumed that the guest state pointer is
 831            unchanged and we wish to continue directly with the next
 832            translation.  Both of these must be non-NULL.
 833
 834          - On host archs which have a link register (ppc32, ppc64), by
 835            a branch to the link register (which is guaranteed to be
 836            unchanged from whatever it was at entry to the
 837            translation).  'dispatch_assisted' and
 838            'dispatch_unassisted' must be NULL.
 839
 840          The aim is to get back and forth between translations and the
 841          dispatcher without creating memory traffic to store return
 842          addresses.
 843
 844          FIXME: update this comment
 845       */
 846       const void* disp_cp_chain_me_to_slowEP;
 847       const void* disp_cp_chain_me_to_fastEP;
 848       const void* disp_cp_xindir;
 849       const void* disp_cp_xassisted;
 850    }
 851    VexTranslateArgs;
 852
 853
 854 /* Runs the entire compilation pipeline. */
 855 extern
 856 VexTranslateResult LibVEX_Translate ( /*MOD*/ VexTranslateArgs* );
 857
 858 /* Runs the first half of the compilation pipeline: lifts guest code to IR,
 859    optimises, instruments and optimises it some more. */
 860 extern
 861 IRSB* LibVEX_FrontEnd ( /*MOD*/ VexTranslateArgs*,
 862                         /*OUT*/ VexTranslateResult* res,
 863                         /*OUT*/ VexRegisterUpdates* pxControl );
 864
 865
 866 /* A subtlety re interaction between self-checking translations and
 867    bb-chasing.  The supplied chase_into_ok function should say NO
 868    (False) when presented with any address for which you might want to
 869    make a self-checking translation.
 870
 871    If it doesn't do that, you may end up with Vex chasing from BB #1
 872    to BB #2 (fine); but if you wanted checking for #2 and not #1, that
 873    would not be the result.  Therefore chase_into_ok should disallow
 874    following into #2.  That will force the caller to eventually
 875    request a new translation starting at #2, at which point Vex will
 876    correctly observe the make-a-self-check flag.
 877
 878    FIXME: is this still up to date? */
 879
 880
 881 /*-------------------------------------------------------*/
 882 /*--- Patch existing translations                     ---*/
 883 /*-------------------------------------------------------*/
 884
 885 /* A host address range that was modified by the functions below.
 886    Callers must request I-cache syncing after the call as appropriate. */
 887 typedef
 888    struct {
 889       HWord start;
 890       HWord len;     /* always > 0 */
 891    }
 892    VexInvalRange;
 893
 894 /* Chain an XDirect jump located at place_to_chain so it jumps to
 895    place_to_jump_to.  It is expected (and checked) that this site
 896    currently contains a call to the dispatcher specified by
 897    disp_cp_chain_me_EXPECTED. */
 898 extern
 899 VexInvalRange LibVEX_Chain ( VexArch     arch_host,
 900                              VexEndness  endhess_host,
 901                              void*       place_to_chain,
 902                              const void* disp_cp_chain_me_EXPECTED,
 903                              const void* place_to_jump_to );
 904
 905 /* Undo an XDirect jump located at place_to_unchain, so it is
 906    converted back into a call to disp_cp_chain_me.  It is expected
 907    (and checked) that this site currently contains a jump directly to
 908    the address specified by place_to_jump_to_EXPECTED. */
 909 extern
 910 VexInvalRange LibVEX_UnChain ( VexArch     arch_host,
 911                                VexEndness  endness_host,
 912                                void*       place_to_unchain,
 913                                const void* place_to_jump_to_EXPECTED,
 914                                const void* disp_cp_chain_me );
 915
 916 /* Returns a constant -- the size of the event check that is put at
 917    the start of every translation.  This makes it possible to
 918    calculate the fast entry point address if the slow entry point
 919    address is known (the usual case), or vice versa. */
 920 extern
 921 Int LibVEX_evCheckSzB ( VexArch arch_host );
 922
 923
 924 /* Patch the counter location into an existing ProfInc point.  The
 925    specified point is checked to make sure it is plausible. */
 926 extern
 927 VexInvalRange LibVEX_PatchProfInc ( VexArch      arch_host,
 928                                     VexEndness   endness_host,
 929                                     void*        place_to_patch,
 930                                     const ULong* location_of_counter );
 931
 932
 933 /*-------------------------------------------------------*/
 934 /*--- Show accumulated statistics                     ---*/
 935 /*-------------------------------------------------------*/
 936
 937 extern void LibVEX_ShowStats ( void );
 938
 939 /*-------------------------------------------------------*/
 940 /*-- IR injection                                      --*/
 941 /*-------------------------------------------------------*/
 942
 943 /* IR Injection Control Block */
 944
 945 #define NO_ROUNDING_MODE (~0u)
 946
 947 typedef
 948    struct {
 949       IROp  op;        // the operation to perform
 950       HWord result;    // address of the result
 951       HWord opnd1;     // address of 1st operand
 952       HWord opnd2;     // address of 2nd operand
 953       HWord opnd3;     // address of 3rd operand
 954       HWord opnd4;     // address of 4th operand
 955       IRType t_result; // type of result
 956       IRType t_opnd1;  // type of 1st operand
 957       IRType t_opnd2;  // type of 2nd operand
 958       IRType t_opnd3;  // type of 3rd operand
 959       IRType t_opnd4;  // type of 4th operand
 960       UInt  rounding_mode;
 961       UInt  num_operands; // excluding rounding mode, if any
 962       /* The following two members describe if this operand has immediate
 963        *  operands. There are a few restrictions:
 964        *    (1) An operator can have at most one immediate operand.
 965        * (2) If there is an immediate operand, it is the right-most operand
 966        *  An immediate_index of 0 means there is no immediate operand.
 967        */
 968       UInt immediate_type;  // size of immediate Ity_I8, Ity_16
 969       UInt immediate_index; // operand number: 1, 2
 970    }
 971    IRICB;
 972
 973 extern void LibVEX_InitIRI ( const IRICB * );
 974
 975 /*-------------------------------------------------------*/
 976 /*--- Notes                                           ---*/
 977 /*-------------------------------------------------------*/
 978
 979 /* Code generation conventions that need to be recorded somewhere.
 980    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 981
 982    x86
 983    ~~~
 984    Generated code should be entered using a JMP instruction.  On
 985    entry, %ebp should point to the guest state, and %esp should be a
 986    valid stack pointer.  The generated code may change %eax, %ebx,
 987    %ecx, %edx, %esi, %edi, all the FP registers and control state, and
 988    all the XMM registers.
 989
 990    On entry, the FPU control word should be set to 0x027F, and the SSE
 991    control word (%mxcsr) should be set to 0x1F80.  On exit, they
 992    should still have those values (after masking off the lowest 6 bits
 993    of %mxcsr).  If they don't, there is a bug in VEX-generated code.
 994
 995    Generated code returns to the scheduler using a JMP instruction, to
 996    the address specified in the .dispatch field of VexTranslateArgs.
 997    %eax (or %eax:%edx, if simulating a 64-bit target) will contain the
 998    guest address of the next block to execute.  %ebp may be changed
 999    to a VEX_TRC_ value, otherwise it should be as it was at entry.
1000
1001    CRITICAL ISSUES in x86 code generation.  The only known critical
1002    issue is that the host FPU and SSE state is not properly saved
1003    across calls to helper functions.  If any helper references any
1004    such state, it is likely (1) to misbehave itself, since the FP
1005    stack tags will not be as expected, and (2) after returning to
1006    generated code, the generated code is likely to go wrong.  This
1007    really should be fixed.
1008
1009    amd64
1010    ~~~~~
1011    Analogous to x86.
1012
1013    ppc32
1014    ~~~~~
1015    On entry, guest state pointer is r31.  .dispatch must be NULL.
1016    Control is returned with a branch to the link register.  Generated
1017    code will not change lr.  At return, r3 holds the next guest addr
1018    (or r3:r4 ?).  r31 may be may be changed to a VEX_TRC_ value,
1019    otherwise it should be as it was at entry.
1020
1021    ppc64
1022    ~~~~~
1023    Same as ppc32.
1024
1025    arm32
1026    ~~~~~
1027    r8 is GSP.
1028
1029    arm64
1030    ~~~~~
1031    r21 is GSP.
1032
1033    ALL GUEST ARCHITECTURES
1034    ~~~~~~~~~~~~~~~~~~~~~~~
1035    The guest state must contain two pseudo-registers, guest_CMSTART
1036    and guest_CMLEN.  These are used to specify guest address ranges,
1037    either of code to be invalidated, when used in conjunction with
1038    Ijk_InvalICache, or of d-cache ranges to be flushed, when used in
1039    conjunction with Ijk_FlushDCache.  In such cases, the two _CM
1040    pseudo-regs should be filled in by the IR, and then an exit with
1041    one of the two abovementioned Ijk_ kinds should happen, so that the
1042    dispatcher can action them.  Both pseudo-regs must have size equal
1043    to the guest word size.
1044
1045    The architecture must a third pseudo-register, guest_NRADDR, also
1046    guest-word-sized.  This is used to record the unredirected guest
1047    address at the start of a translation whose start has been
1048    redirected.  By reading this pseudo-register shortly afterwards,
1049    the translation can find out what the corresponding no-redirection
1050    address was.  Note, this is only set for wrap-style redirects, not
1051    for replace-style ones.
1052 */
1053 #endif /* ndef __LIBVEX_H */
1054
1055 /*---------------------------------------------------------------*/
1056 /*---                                                libvex.h ---*/
1057 /*---------------------------------------------------------------*/