From d242cdf5288b86d9070d88791c8ee696612becdc Mon Sep 17 00:00:00 2001 From: Jerry Jelinek Date: Wed, 21 Jun 2017 12:08:19 +0000 Subject: [PATCH] 8492 AVX512 dis - legacy logical instructions Reviewed by: Robert Mustacchi Reviewed by: Gordon Ross Approved by: Richard Lowe --- usr/src/common/dis/i386/dis_tables.c | 85 ++++++--- .../test/util-tests/tests/dis/i386/32.avx512.out | 192 +++++++++++++++++++++ usr/src/test/util-tests/tests/dis/i386/32.avx512.s | 162 ++++++++++++++++- .../test/util-tests/tests/dis/i386/64.avx512.out | 192 +++++++++++++++++++++ usr/src/test/util-tests/tests/dis/i386/64.avx512.s | 163 ++++++++++++++++- 5 files changed, 769 insertions(+), 25 deletions(-) diff --git a/usr/src/common/dis/i386/dis_tables.c b/usr/src/common/dis/i386/dis_tables.c index 000cb020f3..78a9881b2a 100644 --- a/usr/src/common/dis/i386/dis_tables.c +++ b/usr/src/common/dis/i386/dis_tables.c @@ -84,7 +84,7 @@ typedef struct instable { uint_t it_invalid32:1; /* invalid in IA32 */ uint_t it_stackop:1; /* push/pop stack operation */ uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ - uint_t it_avxsuf:1; /* AVX suffix required */ + uint_t it_avxsuf:2; /* AVX2/AVX512 suffix rqd. */ uint_t it_vexopmask:1; /* VEX inst. that use opmask */ } instable_t; @@ -283,7 +283,9 @@ enum { * IND - indirect to another to another table * "T" - means to Terminate indirections (this is the final opcode) * "S" - means "operand length suffix required" - * "Sa" - means AVX2 suffix (d/q) required + * "Sa" - means AVX2 suffix (q/d) required + * "Sq" - means AVX512 suffix (q/d) required + * "Sd" - means AVX512 suffix (d/s) required * "NS" - means "no suffix" which is the operand length suffix of the opcode * "Z" - means instruction size arg required * "u" - means the opcode is invalid in IA32 but valid in amd64 @@ -294,6 +296,10 @@ enum { * "vo" - means VEX instruction that operates on opmask registers, not fpu */ +#define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling */ +#define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix handling */ +#define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix handling */ + #if defined(DIS_TEXT) && defined(DIS_MEM) #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} @@ -305,14 +311,15 @@ enum { #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} -#define TSavo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1, 1} #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} -#define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, 1} +#define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2} +#define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q} +#define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D} #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} @@ -333,7 +340,9 @@ enum { #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} -#define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 1} +#define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2} +#define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q} +#define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5D} #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} @@ -354,7 +363,9 @@ enum { #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} -#define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, 1} +#define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2} +#define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q} +#define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5D} #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} @@ -375,7 +386,9 @@ enum { #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} -#define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, 1} +#define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2} +#define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q} +#define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D} #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} @@ -1442,14 +1455,14 @@ const instable_t dis_opAVX62[256] = { /* [08] */ INVALID, INVALID, INVALID, INVALID, /* [0C] */ INVALID, INVALID, INVALID, INVALID, -/* [10] */ TNS("vmovup",EVEX_MX), TNS("vmovup",EVEX_RX), INVALID, INVALID, +/* [10] */ TSd("vmovup",EVEX_MX), TSd("vmovup",EVEX_RX), INVALID, INVALID, /* [14] */ INVALID, INVALID, INVALID, INVALID, /* [18] */ INVALID, INVALID, INVALID, INVALID, /* [1C] */ INVALID, INVALID, INVALID, INVALID, /* [20] */ INVALID, INVALID, INVALID, INVALID, /* [24] */ INVALID, INVALID, INVALID, INVALID, -/* [28] */ TNS("vmovap",EVEX_MX), TNS("vmovap",EVEX_RX), INVALID, INVALID, +/* [28] */ TSd("vmovap",EVEX_MX), TSd("vmovap",EVEX_RX), INVALID, INVALID, /* [2C] */ INVALID, INVALID, INVALID, INVALID, /* [30] */ INVALID, INVALID, INVALID, INVALID, @@ -1463,7 +1476,7 @@ const instable_t dis_opAVX62[256] = { /* [4C] */ INVALID, INVALID, INVALID, INVALID, /* [50] */ INVALID, INVALID, INVALID, INVALID, -/* [54] */ INVALID, INVALID, INVALID, INVALID, +/* [54] */ TSd("vandp",EVEX_RMrX), TSd("vandnp",EVEX_RMrX), TSd("vorp",EVEX_RMrX), TSd("vxorp",EVEX_RMrX), /* [58] */ INVALID, INVALID, INVALID, INVALID, /* [5C] */ INVALID, INVALID, INVALID, INVALID, @@ -1504,13 +1517,13 @@ const instable_t dis_opAVX62[256] = { /* [D0] */ INVALID, INVALID, INVALID, INVALID, /* [D4] */ INVALID, INVALID, INVALID, INVALID, -/* [D8] */ INVALID, INVALID, INVALID, INVALID, -/* [DC] */ INVALID, INVALID, INVALID, INVALID, +/* [D8] */ INVALID, INVALID, INVALID, TSq("vpand",EVEX_RMrX), +/* [DC] */ INVALID, INVALID, INVALID, TSq("vpandn",EVEX_RMrX), /* [E0] */ INVALID, INVALID, INVALID, INVALID, /* [E4] */ INVALID, INVALID, INVALID, INVALID, -/* [E8] */ INVALID, INVALID, INVALID, INVALID, -/* [EC] */ INVALID, INVALID, INVALID, INVALID, +/* [E8] */ INVALID, INVALID, INVALID, TSq("vpor",EVEX_RMrX), +/* [EC] */ INVALID, INVALID, INVALID, TSq("vpxor",EVEX_RMrX), /* [F0] */ INVALID, INVALID, INVALID, INVALID, /* [F4] */ INVALID, INVALID, INVALID, INVALID, @@ -2668,7 +2681,13 @@ dtrace_evex_mnem_adjust(dis86_t *x, instable_t *dp, uint_t vex_W, } } else { - (void) strlcat(x->d86_mnem, vex_W != 0 ? "d" : "s", OPLEN); + if (dp->it_avxsuf == AVS5Q) { + (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", + OPLEN); + } else { + (void) strlcat(x->d86_mnem, vex_W != 0 ? "d" : "s", + OPLEN); + } } #endif } @@ -2759,10 +2778,10 @@ dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) */ /* ARGSUSED */ static void -dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t evex_byte3) +dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3) { #ifdef DIS_TEXT - char *opnd = x->d86_opnd[1].d86_opnd; + char *opnd = x->d86_opnd[tgtop].d86_opnd; int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; #endif if (x->d86_error) @@ -3255,9 +3274,9 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode) uint_t vex_X = 1; uint_t vex_B = 1; uint_t vex_W = 0; - uint_t vex_L; - uint_t evex_L; - uint_t evex_modrm; + uint_t vex_L = 0; + uint_t evex_L = 0; + uint_t evex_modrm = 0; dis_gather_regs_t *vreg; #ifdef DIS_TEXT @@ -4042,7 +4061,7 @@ not_avx512: if (strcmp(dp->it_name, "INVALID") == 0) goto error; (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); - if (dp->it_avxsuf && dp->it_suffix) { + if (dp->it_avxsuf == AVS2 && dp->it_suffix) { (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", OPLEN); } else if (dp->it_vexopmask && dp->it_suffix) { @@ -5769,7 +5788,7 @@ L_VEX_RM: dtrace_evex_adjust_rm(evex_byte1, &r_m); dtrace_evex_adjust_reg_name(evex_L, &wbit); dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); - dtrace_evex_adjust_z_opmask(x, evex_byte3); + dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); dtrace_get_operand(x, mode, r_m, wbit, 0); dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); break; @@ -5784,9 +5803,29 @@ L_VEX_RM: dtrace_evex_adjust_reg_name(evex_L, &wbit); dtrace_get_operand(x, mode, r_m, wbit, 1); dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); - dtrace_evex_adjust_z_opmask(x, evex_byte3); + dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); break; + case EVEX_RMrX: + /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */ + x->d86_numopnds = 3; + dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); + dtrace_get_modrm(x, &mode, ®, &r_m); + evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; + dtrace_evex_adjust_reg(evex_byte1, ®); + dtrace_evex_adjust_rm(evex_byte1, &r_m); + dtrace_evex_adjust_reg_name(evex_L, &wbit); + dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); + /* + * EVEX.vvvv is the same as VEX.vvvv (ones complement of the + * register specifier). The EVEX prefix handling uses the vex_v + * variable for these bits. + */ + dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); + dtrace_get_operand(x, mode, r_m, wbit, 0); + dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); + dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); + break; /* an invalid op code */ case AM: case DM: diff --git a/usr/src/test/util-tests/tests/dis/i386/32.avx512.out b/usr/src/test/util-tests/tests/dis/i386/32.avx512.out index 9eb45c38cd..b49b738c14 100644 --- a/usr/src/test/util-tests/tests/dis/i386/32.avx512.out +++ b/usr/src/test/util-tests/tests/dis/i386/32.avx512.out @@ -95,3 +95,195 @@ 24 libdis_test+0x1ab: 62 f1 fe 48 6f 04 vmovdqu64 (%esp),%zmm0 24 + libdis_test+0x1b2: 62 f1 f5 88 55 d0 vandnpd %xmm0,%xmm1,%xmm2{z} + libdis_test+0x1b8: 62 f1 e5 88 55 20 vandnpd (%eax),%xmm3,%xmm4{z} + libdis_test+0x1be: 62 f1 d5 88 55 b1 vandnpd 0x42(%ecx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x1c8: 62 f1 f5 a8 55 d0 vandnpd %ymm0,%ymm1,%ymm2{z} + libdis_test+0x1ce: 62 f1 e5 a8 55 23 vandnpd (%ebx),%ymm3,%ymm4{z} + libdis_test+0x1d4: 62 f1 d5 a8 55 b2 vandnpd 0x42(%edx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x1de: 62 f1 f5 48 55 d0 vandnpd %zmm0,%zmm1,%zmm2 + libdis_test+0x1e4: 62 f1 e5 48 55 23 vandnpd (%ebx),%zmm3,%zmm4 + libdis_test+0x1ea: 62 f1 d5 48 55 b2 vandnpd 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x1f4: 62 f1 74 88 55 d0 vandnps %xmm0,%xmm1,%xmm2{z} + libdis_test+0x1fa: 62 f1 64 88 55 20 vandnps (%eax),%xmm3,%xmm4{z} + libdis_test+0x200: 62 f1 54 88 55 b1 vandnps 0x42(%ecx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x20a: 62 f1 74 a8 55 d0 vandnps %ymm0,%ymm1,%ymm2{z} + libdis_test+0x210: 62 f1 64 a8 55 23 vandnps (%ebx),%ymm3,%ymm4{z} + libdis_test+0x216: 62 f1 54 a8 55 b2 vandnps 0x42(%edx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x220: 62 f1 74 48 55 d0 vandnps %zmm0,%zmm1,%zmm2 + libdis_test+0x226: 62 f1 64 48 55 23 vandnps (%ebx),%zmm3,%zmm4 + libdis_test+0x22c: 62 f1 54 48 55 b2 vandnps 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x236: 62 f1 f5 88 54 d0 vandpd %xmm0,%xmm1,%xmm2{z} + libdis_test+0x23c: 62 f1 e5 88 54 20 vandpd (%eax),%xmm3,%xmm4{z} + libdis_test+0x242: 62 f1 d5 88 54 b1 vandpd 0x42(%ecx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x24c: 62 f1 f5 a8 54 d0 vandpd %ymm0,%ymm1,%ymm2{z} + libdis_test+0x252: 62 f1 e5 a8 54 23 vandpd (%ebx),%ymm3,%ymm4{z} + libdis_test+0x258: 62 f1 d5 a8 54 b2 vandpd 0x42(%edx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x262: 62 f1 f5 48 54 d0 vandpd %zmm0,%zmm1,%zmm2 + libdis_test+0x268: 62 f1 e5 48 54 23 vandpd (%ebx),%zmm3,%zmm4 + libdis_test+0x26e: 62 f1 d5 48 54 b2 vandpd 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x278: 62 f1 74 88 54 d0 vandps %xmm0,%xmm1,%xmm2{z} + libdis_test+0x27e: 62 f1 64 88 54 20 vandps (%eax),%xmm3,%xmm4{z} + libdis_test+0x284: 62 f1 54 88 54 b1 vandps 0x42(%ecx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x28e: 62 f1 74 a8 54 d0 vandps %ymm0,%ymm1,%ymm2{z} + libdis_test+0x294: 62 f1 64 a8 54 23 vandps (%ebx),%ymm3,%ymm4{z} + libdis_test+0x29a: 62 f1 54 a8 54 b2 vandps 0x42(%edx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x2a4: 62 f1 74 48 54 d0 vandps %zmm0,%zmm1,%zmm2 + libdis_test+0x2aa: 62 f1 64 48 54 23 vandps (%ebx),%zmm3,%zmm4 + libdis_test+0x2b0: 62 f1 54 48 54 b2 vandps 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x2ba: 62 f1 75 08 db d0 vpandd %xmm0,%xmm1,%xmm2 + libdis_test+0x2c0: 62 f1 65 08 db 20 vpandd (%eax),%xmm3,%xmm4 + libdis_test+0x2c6: 62 f1 55 08 db b1 vpandd 0x42(%ecx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x2d0: 62 f1 75 28 db d0 vpandd %ymm0,%ymm1,%ymm2 + libdis_test+0x2d6: 62 f1 65 28 db 23 vpandd (%ebx),%ymm3,%ymm4 + libdis_test+0x2dc: 62 f1 55 28 db b2 vpandd 0x42(%edx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x2e6: 62 f1 75 48 db d0 vpandd %zmm0,%zmm1,%zmm2 + libdis_test+0x2ec: 62 f1 65 48 db 23 vpandd (%ebx),%zmm3,%zmm4 + libdis_test+0x2f2: 62 f1 55 48 db b2 vpandd 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x2fc: 62 f1 f5 08 db d0 vpandq %xmm0,%xmm1,%xmm2 + libdis_test+0x302: 62 f1 e5 08 db 20 vpandq (%eax),%xmm3,%xmm4 + libdis_test+0x308: 62 f1 d5 08 db b1 vpandq 0x42(%ecx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x312: 62 f1 f5 28 db d0 vpandq %ymm0,%ymm1,%ymm2 + libdis_test+0x318: 62 f1 e5 28 db 23 vpandq (%ebx),%ymm3,%ymm4 + libdis_test+0x31e: 62 f1 d5 28 db b2 vpandq 0x42(%edx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x328: 62 f1 f5 48 db d0 vpandq %zmm0,%zmm1,%zmm2 + libdis_test+0x32e: 62 f1 e5 48 db 23 vpandq (%ebx),%zmm3,%zmm4 + libdis_test+0x334: 62 f1 d5 48 db b2 vpandq 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x33e: 62 f1 75 08 df d0 vpandnd %xmm0,%xmm1,%xmm2 + libdis_test+0x344: 62 f1 65 08 df 20 vpandnd (%eax),%xmm3,%xmm4 + libdis_test+0x34a: 62 f1 55 08 df b1 vpandnd 0x42(%ecx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x354: 62 f1 75 28 df d0 vpandnd %ymm0,%ymm1,%ymm2 + libdis_test+0x35a: 62 f1 65 28 df 23 vpandnd (%ebx),%ymm3,%ymm4 + libdis_test+0x360: 62 f1 55 28 df b2 vpandnd 0x42(%edx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x36a: 62 f1 75 48 df d0 vpandnd %zmm0,%zmm1,%zmm2 + libdis_test+0x370: 62 f1 65 48 df 23 vpandnd (%ebx),%zmm3,%zmm4 + libdis_test+0x376: 62 f1 55 48 df b2 vpandnd 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x380: 62 f1 f5 08 df d0 vpandnq %xmm0,%xmm1,%xmm2 + libdis_test+0x386: 62 f1 e5 08 df 20 vpandnq (%eax),%xmm3,%xmm4 + libdis_test+0x38c: 62 f1 d5 08 df b1 vpandnq 0x42(%ecx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x396: 62 f1 f5 28 df d0 vpandnq %ymm0,%ymm1,%ymm2 + libdis_test+0x39c: 62 f1 e5 28 df 23 vpandnq (%ebx),%ymm3,%ymm4 + libdis_test+0x3a2: 62 f1 d5 28 df b2 vpandnq 0x42(%edx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x3ac: 62 f1 f5 48 df d0 vpandnq %zmm0,%zmm1,%zmm2 + libdis_test+0x3b2: 62 f1 e5 48 df 23 vpandnq (%ebx),%zmm3,%zmm4 + libdis_test+0x3b8: 62 f1 d5 48 df b2 vpandnq 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x3c2: 62 f1 f5 88 56 d0 vorpd %xmm0,%xmm1,%xmm2{z} + libdis_test+0x3c8: 62 f1 e5 88 56 20 vorpd (%eax),%xmm3,%xmm4{z} + libdis_test+0x3ce: 62 f1 d5 88 56 b1 vorpd 0x42(%ecx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x3d8: 62 f1 f5 a8 56 d0 vorpd %ymm0,%ymm1,%ymm2{z} + libdis_test+0x3de: 62 f1 e5 a8 56 23 vorpd (%ebx),%ymm3,%ymm4{z} + libdis_test+0x3e4: 62 f1 d5 a8 56 b2 vorpd 0x42(%edx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x3ee: 62 f1 f5 48 56 d0 vorpd %zmm0,%zmm1,%zmm2 + libdis_test+0x3f4: 62 f1 e5 48 56 20 vorpd (%eax),%zmm3,%zmm4 + libdis_test+0x3fa: 62 f1 d5 48 56 b1 vorpd 0x42(%ecx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x404: 62 f1 74 88 56 d0 vorps %xmm0,%xmm1,%xmm2{z} + libdis_test+0x40a: 62 f1 64 88 56 20 vorps (%eax),%xmm3,%xmm4{z} + libdis_test+0x410: 62 f1 54 88 56 b1 vorps 0x42(%ecx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x41a: 62 f1 74 a8 56 d0 vorps %ymm0,%ymm1,%ymm2{z} + libdis_test+0x420: 62 f1 64 a8 56 23 vorps (%ebx),%ymm3,%ymm4{z} + libdis_test+0x426: 62 f1 54 a8 56 b2 vorps 0x42(%edx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x430: 62 f1 74 48 56 d0 vorps %zmm0,%zmm1,%zmm2 + libdis_test+0x436: 62 f1 64 48 56 20 vorps (%eax),%zmm3,%zmm4 + libdis_test+0x43c: 62 f1 54 48 56 b1 vorps 0x42(%ecx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x446: 62 f1 75 08 eb d0 vpord %xmm0,%xmm1,%xmm2 + libdis_test+0x44c: 62 f1 65 08 eb 20 vpord (%eax),%xmm3,%xmm4 + libdis_test+0x452: 62 f1 55 08 eb b1 vpord 0x42(%ecx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x45c: 62 f1 75 28 eb d0 vpord %ymm0,%ymm1,%ymm2 + libdis_test+0x462: 62 f1 65 28 eb 23 vpord (%ebx),%ymm3,%ymm4 + libdis_test+0x468: 62 f1 55 28 eb b2 vpord 0x42(%edx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x472: 62 f1 75 48 eb d0 vpord %zmm0,%zmm1,%zmm2 + libdis_test+0x478: 62 f1 65 48 eb 20 vpord (%eax),%zmm3,%zmm4 + libdis_test+0x47e: 62 f1 55 48 eb b1 vpord 0x42(%ecx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x488: 62 f1 f5 08 eb d0 vporq %xmm0,%xmm1,%xmm2 + libdis_test+0x48e: 62 f1 e5 08 eb 20 vporq (%eax),%xmm3,%xmm4 + libdis_test+0x494: 62 f1 d5 08 eb b1 vporq 0x42(%ecx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x49e: 62 f1 f5 28 eb d0 vporq %ymm0,%ymm1,%ymm2 + libdis_test+0x4a4: 62 f1 e5 28 eb 23 vporq (%ebx),%ymm3,%ymm4 + libdis_test+0x4aa: 62 f1 d5 28 eb b2 vporq 0x42(%edx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x4b4: 62 f1 f5 48 eb d0 vporq %zmm0,%zmm1,%zmm2 + libdis_test+0x4ba: 62 f1 e5 48 eb 20 vporq (%eax),%zmm3,%zmm4 + libdis_test+0x4c0: 62 f1 d5 48 eb b1 vporq 0x42(%ecx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x4ca: 62 f1 75 08 ef d0 vpxord %xmm0,%xmm1,%xmm2 + libdis_test+0x4d0: 62 f1 65 08 ef 20 vpxord (%eax),%xmm3,%xmm4 + libdis_test+0x4d6: 62 f1 55 08 ef b1 vpxord 0x42(%ecx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x4e0: 62 f1 75 28 ef d0 vpxord %ymm0,%ymm1,%ymm2 + libdis_test+0x4e6: 62 f1 65 28 ef 23 vpxord (%ebx),%ymm3,%ymm4 + libdis_test+0x4ec: 62 f1 55 28 ef b2 vpxord 0x42(%edx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x4f6: 62 f1 75 48 ef d0 vpxord %zmm0,%zmm1,%zmm2 + libdis_test+0x4fc: 62 f1 65 48 ef 20 vpxord (%eax),%zmm3,%zmm4 + libdis_test+0x502: 62 f1 55 48 ef b1 vpxord 0x42(%ecx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x50c: 62 f1 f5 08 ef d0 vpxorq %xmm0,%xmm1,%xmm2 + libdis_test+0x512: 62 f1 e5 08 ef 20 vpxorq (%eax),%xmm3,%xmm4 + libdis_test+0x518: 62 f1 d5 08 ef b1 vpxorq 0x42(%ecx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x522: 62 f1 f5 28 ef d0 vpxorq %ymm0,%ymm1,%ymm2 + libdis_test+0x528: 62 f1 e5 28 ef 23 vpxorq (%ebx),%ymm3,%ymm4 + libdis_test+0x52e: 62 f1 d5 28 ef b2 vpxorq 0x42(%edx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x538: 62 f1 f5 48 ef d0 vpxorq %zmm0,%zmm1,%zmm2 + libdis_test+0x53e: 62 f1 e5 48 ef 20 vpxorq (%eax),%zmm3,%zmm4 + libdis_test+0x544: 62 f1 d5 48 ef b1 vpxorq 0x42(%ecx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x54e: 62 f1 f5 88 57 d0 vxorpd %xmm0,%xmm1,%xmm2{z} + libdis_test+0x554: 62 f1 e5 88 57 20 vxorpd (%eax),%xmm3,%xmm4{z} + libdis_test+0x55a: 62 f1 d5 88 57 b1 vxorpd 0x42(%ecx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x564: 62 f1 f5 a8 57 d0 vxorpd %ymm0,%ymm1,%ymm2{z} + libdis_test+0x56a: 62 f1 e5 a8 57 23 vxorpd (%ebx),%ymm3,%ymm4{z} + libdis_test+0x570: 62 f1 d5 a8 57 b2 vxorpd 0x42(%edx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x57a: 62 f1 f5 48 57 d0 vxorpd %zmm0,%zmm1,%zmm2 + libdis_test+0x580: 62 f1 e5 48 57 23 vxorpd (%ebx),%zmm3,%zmm4 + libdis_test+0x586: 62 f1 d5 48 57 b2 vxorpd 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x590: 62 f1 74 88 57 d0 vxorps %xmm0,%xmm1,%xmm2{z} + libdis_test+0x596: 62 f1 64 88 57 20 vxorps (%eax),%xmm3,%xmm4{z} + libdis_test+0x59c: 62 f1 54 88 57 b1 vxorps 0x42(%ecx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x5a6: 62 f1 74 a8 57 d0 vxorps %ymm0,%ymm1,%ymm2{z} + libdis_test+0x5ac: 62 f1 64 a8 57 23 vxorps (%ebx),%ymm3,%ymm4{z} + libdis_test+0x5b2: 62 f1 54 a8 57 b2 vxorps 0x42(%edx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x5bc: 62 f1 74 48 57 d0 vxorps %zmm0,%zmm1,%zmm2 + libdis_test+0x5c2: 62 f1 64 48 57 23 vxorps (%ebx),%zmm3,%zmm4 + libdis_test+0x5c8: 62 f1 54 48 57 b2 vxorps 0x42(%edx),%zmm5,%zmm6 + 42 00 00 00 diff --git a/usr/src/test/util-tests/tests/dis/i386/32.avx512.s b/usr/src/test/util-tests/tests/dis/i386/32.avx512.s index adcdae36da..3107788a99 100755 --- a/usr/src/test/util-tests/tests/dis/i386/32.avx512.s +++ b/usr/src/test/util-tests/tests/dis/i386/32.avx512.s @@ -14,7 +14,7 @@ */ /* - * Basic test for AVX512 mov instructions + * Basic test for AVX512 instructions */ .text @@ -97,4 +97,164 @@ libdis_test: vmovdqu16 (%esp), %zmm0 vmovdqu32 (%esp), %zmm0 vmovdqu64 (%esp), %zmm0 + + vandnpd %xmm0, %xmm1, %xmm2{z} + vandnpd (%eax), %xmm3, %xmm4{z} + vandnpd 0x42(%ecx), %xmm5, %xmm6{z} + vandnpd %ymm0, %ymm1, %ymm2{z} + vandnpd (%ebx), %ymm3, %ymm4{z} + vandnpd 0x42(%edx), %ymm5, %ymm6{z} + vandnpd %zmm0, %zmm1, %zmm2 + vandnpd (%ebx), %zmm3, %zmm4 + vandnpd 0x42(%edx), %zmm5, %zmm6 + + vandnps %xmm0, %xmm1, %xmm2{z} + vandnps (%eax), %xmm3, %xmm4{z} + vandnps 0x42(%ecx), %xmm5, %xmm6{z} + vandnps %ymm0, %ymm1, %ymm2{z} + vandnps (%ebx), %ymm3, %ymm4{z} + vandnps 0x42(%edx), %ymm5, %ymm6{z} + vandnps %zmm0, %zmm1, %zmm2 + vandnps (%ebx), %zmm3, %zmm4 + vandnps 0x42(%edx), %zmm5, %zmm6 + + vandpd %xmm0, %xmm1, %xmm2{z} + vandpd (%eax), %xmm3, %xmm4{z} + vandpd 0x42(%ecx), %xmm5, %xmm6{z} + vandpd %ymm0, %ymm1, %ymm2{z} + vandpd (%ebx), %ymm3, %ymm4{z} + vandpd 0x42(%edx), %ymm5, %ymm6{z} + vandpd %zmm0, %zmm1, %zmm2 + vandpd (%ebx), %zmm3, %zmm4 + vandpd 0x42(%edx), %zmm5, %zmm6 + + vandps %xmm0, %xmm1, %xmm2{z} + vandps (%eax), %xmm3, %xmm4{z} + vandps 0x42(%ecx), %xmm5, %xmm6{z} + vandps %ymm0, %ymm1, %ymm2{z} + vandps (%ebx), %ymm3, %ymm4{z} + vandps 0x42(%edx), %ymm5, %ymm6{z} + vandps %zmm0, %zmm1, %zmm2 + vandps (%ebx), %zmm3, %zmm4 + vandps 0x42(%edx), %zmm5, %zmm6 + + vpandd %xmm0, %xmm1, %xmm2 + vpandd (%eax), %xmm3, %xmm4 + vpandd 0x42(%ecx), %xmm5, %xmm6 + vpandd %ymm0, %ymm1, %ymm2 + vpandd (%ebx), %ymm3, %ymm4 + vpandd 0x42(%edx), %ymm5, %ymm6 + vpandd %zmm0, %zmm1, %zmm2 + vpandd (%ebx), %zmm3, %zmm4 + vpandd 0x42(%edx), %zmm5, %zmm6 + + vpandq %xmm0, %xmm1, %xmm2 + vpandq (%eax), %xmm3, %xmm4 + vpandq 0x42(%ecx), %xmm5, %xmm6 + vpandq %ymm0, %ymm1, %ymm2 + vpandq (%ebx), %ymm3, %ymm4 + vpandq 0x42(%edx), %ymm5, %ymm6 + vpandq %zmm0, %zmm1, %zmm2 + vpandq (%ebx), %zmm3, %zmm4 + vpandq 0x42(%edx), %zmm5, %zmm6 + + vpandnd %xmm0, %xmm1, %xmm2 + vpandnd (%eax), %xmm3, %xmm4 + vpandnd 0x42(%ecx), %xmm5, %xmm6 + vpandnd %ymm0, %ymm1, %ymm2 + vpandnd (%ebx), %ymm3, %ymm4 + vpandnd 0x42(%edx), %ymm5, %ymm6 + vpandnd %zmm0, %zmm1, %zmm2 + vpandnd (%ebx), %zmm3, %zmm4 + vpandnd 0x42(%edx), %zmm5, %zmm6 + + vpandnq %xmm0, %xmm1, %xmm2 + vpandnq (%eax), %xmm3, %xmm4 + vpandnq 0x42(%ecx), %xmm5, %xmm6 + vpandnq %ymm0, %ymm1, %ymm2 + vpandnq (%ebx), %ymm3, %ymm4 + vpandnq 0x42(%edx), %ymm5, %ymm6 + vpandnq %zmm0, %zmm1, %zmm2 + vpandnq (%ebx), %zmm3, %zmm4 + vpandnq 0x42(%edx), %zmm5, %zmm6 + + vorpd %xmm0, %xmm1, %xmm2{z} + vorpd (%eax), %xmm3, %xmm4{z} + vorpd 0x42(%ecx), %xmm5, %xmm6{z} + vorpd %ymm0, %ymm1, %ymm2{z} + vorpd (%ebx), %ymm3, %ymm4{z} + vorpd 0x42(%edx), %ymm5, %ymm6{z} + vorpd %zmm0, %zmm1, %zmm2 + vorpd (%eax), %zmm3, %zmm4 + vorpd 0x42(%ecx), %zmm5, %zmm6 + + vorps %xmm0, %xmm1, %xmm2{z} + vorps (%eax), %xmm3, %xmm4{z} + vorps 0x42(%ecx), %xmm5, %xmm6{z} + vorps %ymm0, %ymm1, %ymm2{z} + vorps (%ebx), %ymm3, %ymm4{z} + vorps 0x42(%edx), %ymm5, %ymm6{z} + vorps %zmm0, %zmm1, %zmm2 + vorps (%eax), %zmm3, %zmm4 + vorps 0x42(%ecx), %zmm5, %zmm6 + + vpord %xmm0, %xmm1, %xmm2 + vpord (%eax), %xmm3, %xmm4 + vpord 0x42(%ecx), %xmm5, %xmm6 + vpord %ymm0, %ymm1, %ymm2 + vpord (%ebx), %ymm3, %ymm4 + vpord 0x42(%edx), %ymm5, %ymm6 + vpord %zmm0, %zmm1, %zmm2 + vpord (%eax), %zmm3, %zmm4 + vpord 0x42(%ecx), %zmm5, %zmm6 + + vporq %xmm0, %xmm1, %xmm2 + vporq (%eax), %xmm3, %xmm4 + vporq 0x42(%ecx), %xmm5, %xmm6 + vporq %ymm0, %ymm1, %ymm2 + vporq (%ebx), %ymm3, %ymm4 + vporq 0x42(%edx), %ymm5, %ymm6 + vporq %zmm0, %zmm1, %zmm2 + vporq (%eax), %zmm3, %zmm4 + vporq 0x42(%ecx), %zmm5, %zmm6 + + vpxord %xmm0, %xmm1, %xmm2 + vpxord (%eax), %xmm3, %xmm4 + vpxord 0x42(%ecx), %xmm5, %xmm6 + vpxord %ymm0, %ymm1, %ymm2 + vpxord (%ebx), %ymm3, %ymm4 + vpxord 0x42(%edx), %ymm5, %ymm6 + vpxord %zmm0, %zmm1, %zmm2 + vpxord (%eax), %zmm3, %zmm4 + vpxord 0x42(%ecx), %zmm5, %zmm6 + + vpxorq %xmm0, %xmm1, %xmm2 + vpxorq (%eax), %xmm3, %xmm4 + vpxorq 0x42(%ecx), %xmm5, %xmm6 + vpxorq %ymm0, %ymm1, %ymm2 + vpxorq (%ebx), %ymm3, %ymm4 + vpxorq 0x42(%edx), %ymm5, %ymm6 + vpxorq %zmm0, %zmm1, %zmm2 + vpxorq (%eax), %zmm3, %zmm4 + vpxorq 0x42(%ecx), %zmm5, %zmm6 + + vxorpd %xmm0, %xmm1, %xmm2{z} + vxorpd (%eax), %xmm3, %xmm4{z} + vxorpd 0x42(%ecx), %xmm5, %xmm6{z} + vxorpd %ymm0, %ymm1, %ymm2{z} + vxorpd (%ebx), %ymm3, %ymm4{z} + vxorpd 0x42(%edx), %ymm5, %ymm6{z} + vxorpd %zmm0, %zmm1, %zmm2 + vxorpd (%ebx), %zmm3, %zmm4 + vxorpd 0x42(%edx), %zmm5, %zmm6 + + vxorps %xmm0, %xmm1, %xmm2{z} + vxorps (%eax), %xmm3, %xmm4{z} + vxorps 0x42(%ecx), %xmm5, %xmm6{z} + vxorps %ymm0, %ymm1, %ymm2{z} + vxorps (%ebx), %ymm3, %ymm4{z} + vxorps 0x42(%edx), %ymm5, %ymm6{z} + vxorps %zmm0, %zmm1, %zmm2 + vxorps (%ebx), %zmm3, %zmm4 + vxorps 0x42(%edx), %zmm5, %zmm6 .size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/i386/64.avx512.out b/usr/src/test/util-tests/tests/dis/i386/64.avx512.out index b4a325086b..e8293406e6 100644 --- a/usr/src/test/util-tests/tests/dis/i386/64.avx512.out +++ b/usr/src/test/util-tests/tests/dis/i386/64.avx512.out @@ -160,3 +160,195 @@ 24 libdis_test+0x313: 62 e1 fe 48 6f 24 vmovdqu64 (%rsp),%zmm20 24 + libdis_test+0x31a: 62 f1 f5 88 55 d0 vandnpd %xmm0,%xmm1,%xmm2{z} + libdis_test+0x320: 62 f1 e5 88 55 20 vandnpd (%rax),%xmm3,%xmm4{z} + libdis_test+0x326: 62 f1 d5 88 55 b1 vandnpd 0x42(%rcx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x330: 62 f1 f5 a8 55 d0 vandnpd %ymm0,%ymm1,%ymm2{z} + libdis_test+0x336: 62 f1 e5 a8 55 23 vandnpd (%rbx),%ymm3,%ymm4{z} + libdis_test+0x33c: 62 f1 d5 a8 55 b2 vandnpd 0x42(%rdx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x346: 62 f1 f5 48 55 d0 vandnpd %zmm0,%zmm1,%zmm2 + libdis_test+0x34c: 62 f1 e5 48 55 23 vandnpd (%rbx),%zmm3,%zmm4 + libdis_test+0x352: 62 f1 d5 48 55 b2 vandnpd 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x35c: 62 f1 74 88 55 d0 vandnps %xmm0,%xmm1,%xmm2{z} + libdis_test+0x362: 62 f1 64 88 55 20 vandnps (%rax),%xmm3,%xmm4{z} + libdis_test+0x368: 62 f1 54 88 55 b1 vandnps 0x42(%rcx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x372: 62 f1 74 a8 55 d0 vandnps %ymm0,%ymm1,%ymm2{z} + libdis_test+0x378: 62 f1 64 a8 55 23 vandnps (%rbx),%ymm3,%ymm4{z} + libdis_test+0x37e: 62 f1 54 a8 55 b2 vandnps 0x42(%rdx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x388: 62 f1 74 48 55 d0 vandnps %zmm0,%zmm1,%zmm2 + libdis_test+0x38e: 62 f1 64 48 55 23 vandnps (%rbx),%zmm3,%zmm4 + libdis_test+0x394: 62 f1 54 48 55 b2 vandnps 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x39e: 62 f1 f5 88 54 d0 vandpd %xmm0,%xmm1,%xmm2{z} + libdis_test+0x3a4: 62 f1 e5 88 54 20 vandpd (%rax),%xmm3,%xmm4{z} + libdis_test+0x3aa: 62 f1 d5 88 54 b1 vandpd 0x42(%rcx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x3b4: 62 f1 f5 a8 54 d0 vandpd %ymm0,%ymm1,%ymm2{z} + libdis_test+0x3ba: 62 f1 e5 a8 54 23 vandpd (%rbx),%ymm3,%ymm4{z} + libdis_test+0x3c0: 62 f1 d5 a8 54 b2 vandpd 0x42(%rdx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x3ca: 62 f1 f5 48 54 d0 vandpd %zmm0,%zmm1,%zmm2 + libdis_test+0x3d0: 62 f1 e5 48 54 23 vandpd (%rbx),%zmm3,%zmm4 + libdis_test+0x3d6: 62 f1 d5 48 54 b2 vandpd 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x3e0: 62 f1 74 88 54 d0 vandps %xmm0,%xmm1,%xmm2{z} + libdis_test+0x3e6: 62 f1 64 88 54 20 vandps (%rax),%xmm3,%xmm4{z} + libdis_test+0x3ec: 62 f1 54 88 54 b1 vandps 0x42(%rcx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x3f6: 62 f1 74 a8 54 d0 vandps %ymm0,%ymm1,%ymm2{z} + libdis_test+0x3fc: 62 f1 64 a8 54 23 vandps (%rbx),%ymm3,%ymm4{z} + libdis_test+0x402: 62 f1 54 a8 54 b2 vandps 0x42(%rdx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x40c: 62 f1 74 48 54 d0 vandps %zmm0,%zmm1,%zmm2 + libdis_test+0x412: 62 f1 64 48 54 23 vandps (%rbx),%zmm3,%zmm4 + libdis_test+0x418: 62 f1 54 48 54 b2 vandps 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x422: 62 f1 75 08 db d0 vpandd %xmm0,%xmm1,%xmm2 + libdis_test+0x428: 62 f1 65 08 db 20 vpandd (%rax),%xmm3,%xmm4 + libdis_test+0x42e: 62 f1 55 08 db b1 vpandd 0x42(%rcx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x438: 62 f1 75 28 db d0 vpandd %ymm0,%ymm1,%ymm2 + libdis_test+0x43e: 62 f1 65 28 db 23 vpandd (%rbx),%ymm3,%ymm4 + libdis_test+0x444: 62 f1 55 28 db b2 vpandd 0x42(%rdx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x44e: 62 f1 75 48 db d0 vpandd %zmm0,%zmm1,%zmm2 + libdis_test+0x454: 62 f1 65 48 db 23 vpandd (%rbx),%zmm3,%zmm4 + libdis_test+0x45a: 62 f1 55 48 db b2 vpandd 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x464: 62 f1 f5 08 db d0 vpandq %xmm0,%xmm1,%xmm2 + libdis_test+0x46a: 62 f1 e5 08 db 20 vpandq (%rax),%xmm3,%xmm4 + libdis_test+0x470: 62 f1 d5 08 db b1 vpandq 0x42(%rcx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x47a: 62 f1 f5 28 db d0 vpandq %ymm0,%ymm1,%ymm2 + libdis_test+0x480: 62 f1 e5 28 db 23 vpandq (%rbx),%ymm3,%ymm4 + libdis_test+0x486: 62 f1 d5 28 db b2 vpandq 0x42(%rdx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x490: 62 f1 f5 48 db d0 vpandq %zmm0,%zmm1,%zmm2 + libdis_test+0x496: 62 f1 e5 48 db 23 vpandq (%rbx),%zmm3,%zmm4 + libdis_test+0x49c: 62 f1 d5 48 db b2 vpandq 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x4a6: 62 f1 75 08 df d0 vpandnd %xmm0,%xmm1,%xmm2 + libdis_test+0x4ac: 62 f1 65 08 df 20 vpandnd (%rax),%xmm3,%xmm4 + libdis_test+0x4b2: 62 f1 55 08 df b1 vpandnd 0x42(%rcx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x4bc: 62 f1 75 28 df d0 vpandnd %ymm0,%ymm1,%ymm2 + libdis_test+0x4c2: 62 f1 65 28 df 23 vpandnd (%rbx),%ymm3,%ymm4 + libdis_test+0x4c8: 62 f1 55 28 df b2 vpandnd 0x42(%rdx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x4d2: 62 f1 75 48 df d0 vpandnd %zmm0,%zmm1,%zmm2 + libdis_test+0x4d8: 62 f1 65 48 df 23 vpandnd (%rbx),%zmm3,%zmm4 + libdis_test+0x4de: 62 f1 55 48 df b2 vpandnd 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x4e8: 62 f1 f5 08 df d0 vpandnq %xmm0,%xmm1,%xmm2 + libdis_test+0x4ee: 62 f1 e5 08 df 20 vpandnq (%rax),%xmm3,%xmm4 + libdis_test+0x4f4: 62 f1 d5 08 df b1 vpandnq 0x42(%rcx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x4fe: 62 f1 f5 28 df d0 vpandnq %ymm0,%ymm1,%ymm2 + libdis_test+0x504: 62 f1 e5 28 df 23 vpandnq (%rbx),%ymm3,%ymm4 + libdis_test+0x50a: 62 f1 d5 28 df b2 vpandnq 0x42(%rdx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x514: 62 f1 f5 48 df d0 vpandnq %zmm0,%zmm1,%zmm2 + libdis_test+0x51a: 62 f1 e5 48 df 23 vpandnq (%rbx),%zmm3,%zmm4 + libdis_test+0x520: 62 f1 d5 48 df b2 vpandnq 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x52a: 62 f1 f5 88 56 d0 vorpd %xmm0,%xmm1,%xmm2{z} + libdis_test+0x530: 62 f1 e5 88 56 20 vorpd (%rax),%xmm3,%xmm4{z} + libdis_test+0x536: 62 f1 d5 88 56 b1 vorpd 0x42(%rcx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x540: 62 f1 f5 a8 56 d0 vorpd %ymm0,%ymm1,%ymm2{z} + libdis_test+0x546: 62 f1 e5 a8 56 23 vorpd (%rbx),%ymm3,%ymm4{z} + libdis_test+0x54c: 62 f1 d5 a8 56 b2 vorpd 0x42(%rdx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x556: 62 f1 f5 48 56 d0 vorpd %zmm0,%zmm1,%zmm2 + libdis_test+0x55c: 62 f1 e5 48 56 20 vorpd (%rax),%zmm3,%zmm4 + libdis_test+0x562: 62 f1 d5 48 56 b1 vorpd 0x42(%rcx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x56c: 62 f1 74 88 56 d0 vorps %xmm0,%xmm1,%xmm2{z} + libdis_test+0x572: 62 f1 64 88 56 20 vorps (%rax),%xmm3,%xmm4{z} + libdis_test+0x578: 62 f1 54 88 56 b1 vorps 0x42(%rcx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x582: 62 f1 74 a8 56 d0 vorps %ymm0,%ymm1,%ymm2{z} + libdis_test+0x588: 62 f1 64 a8 56 23 vorps (%rbx),%ymm3,%ymm4{z} + libdis_test+0x58e: 62 f1 54 a8 56 b2 vorps 0x42(%rdx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x598: 62 f1 74 48 56 d0 vorps %zmm0,%zmm1,%zmm2 + libdis_test+0x59e: 62 f1 64 48 56 20 vorps (%rax),%zmm3,%zmm4 + libdis_test+0x5a4: 62 f1 54 48 56 b1 vorps 0x42(%rcx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x5ae: 62 f1 75 08 eb d0 vpord %xmm0,%xmm1,%xmm2 + libdis_test+0x5b4: 62 f1 65 08 eb 20 vpord (%rax),%xmm3,%xmm4 + libdis_test+0x5ba: 62 f1 55 08 eb b1 vpord 0x42(%rcx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x5c4: 62 f1 75 28 eb d0 vpord %ymm0,%ymm1,%ymm2 + libdis_test+0x5ca: 62 f1 65 28 eb 23 vpord (%rbx),%ymm3,%ymm4 + libdis_test+0x5d0: 62 f1 55 28 eb b2 vpord 0x42(%rdx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x5da: 62 f1 75 48 eb d0 vpord %zmm0,%zmm1,%zmm2 + libdis_test+0x5e0: 62 f1 65 48 eb 20 vpord (%rax),%zmm3,%zmm4 + libdis_test+0x5e6: 62 f1 55 48 eb b1 vpord 0x42(%rcx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x5f0: 62 f1 f5 08 eb d0 vporq %xmm0,%xmm1,%xmm2 + libdis_test+0x5f6: 62 f1 e5 08 eb 20 vporq (%rax),%xmm3,%xmm4 + libdis_test+0x5fc: 62 f1 d5 08 eb b1 vporq 0x42(%rcx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x606: 62 f1 f5 28 eb d0 vporq %ymm0,%ymm1,%ymm2 + libdis_test+0x60c: 62 f1 e5 28 eb 23 vporq (%rbx),%ymm3,%ymm4 + libdis_test+0x612: 62 f1 d5 28 eb b2 vporq 0x42(%rdx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x61c: 62 f1 f5 48 eb d0 vporq %zmm0,%zmm1,%zmm2 + libdis_test+0x622: 62 f1 e5 48 eb 20 vporq (%rax),%zmm3,%zmm4 + libdis_test+0x628: 62 f1 d5 48 eb b1 vporq 0x42(%rcx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x632: 62 f1 75 08 ef d0 vpxord %xmm0,%xmm1,%xmm2 + libdis_test+0x638: 62 f1 65 08 ef 20 vpxord (%rax),%xmm3,%xmm4 + libdis_test+0x63e: 62 f1 55 08 ef b1 vpxord 0x42(%rcx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x648: 62 f1 75 28 ef d0 vpxord %ymm0,%ymm1,%ymm2 + libdis_test+0x64e: 62 f1 65 28 ef 23 vpxord (%rbx),%ymm3,%ymm4 + libdis_test+0x654: 62 f1 55 28 ef b2 vpxord 0x42(%rdx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x65e: 62 f1 75 48 ef d0 vpxord %zmm0,%zmm1,%zmm2 + libdis_test+0x664: 62 f1 65 48 ef 20 vpxord (%rax),%zmm3,%zmm4 + libdis_test+0x66a: 62 f1 55 48 ef b1 vpxord 0x42(%rcx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x674: 62 f1 f5 08 ef d0 vpxorq %xmm0,%xmm1,%xmm2 + libdis_test+0x67a: 62 f1 e5 08 ef 20 vpxorq (%rax),%xmm3,%xmm4 + libdis_test+0x680: 62 f1 d5 08 ef b1 vpxorq 0x42(%rcx),%xmm5,%xmm6 + 42 00 00 00 + libdis_test+0x68a: 62 f1 f5 28 ef d0 vpxorq %ymm0,%ymm1,%ymm2 + libdis_test+0x690: 62 f1 e5 28 ef 23 vpxorq (%rbx),%ymm3,%ymm4 + libdis_test+0x696: 62 f1 d5 28 ef b2 vpxorq 0x42(%rdx),%ymm5,%ymm6 + 42 00 00 00 + libdis_test+0x6a0: 62 f1 f5 48 ef d0 vpxorq %zmm0,%zmm1,%zmm2 + libdis_test+0x6a6: 62 f1 e5 48 ef 20 vpxorq (%rax),%zmm3,%zmm4 + libdis_test+0x6ac: 62 f1 d5 48 ef b1 vpxorq 0x42(%rcx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x6b6: 62 f1 f5 88 57 d0 vxorpd %xmm0,%xmm1,%xmm2{z} + libdis_test+0x6bc: 62 f1 e5 88 57 20 vxorpd (%rax),%xmm3,%xmm4{z} + libdis_test+0x6c2: 62 f1 d5 88 57 b1 vxorpd 0x42(%rcx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x6cc: 62 f1 f5 a8 57 d0 vxorpd %ymm0,%ymm1,%ymm2{z} + libdis_test+0x6d2: 62 f1 e5 a8 57 23 vxorpd (%rbx),%ymm3,%ymm4{z} + libdis_test+0x6d8: 62 f1 d5 a8 57 b2 vxorpd 0x42(%rdx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x6e2: 62 f1 f5 48 57 d0 vxorpd %zmm0,%zmm1,%zmm2 + libdis_test+0x6e8: 62 f1 e5 48 57 23 vxorpd (%rbx),%zmm3,%zmm4 + libdis_test+0x6ee: 62 f1 d5 48 57 b2 vxorpd 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 + libdis_test+0x6f8: 62 f1 74 88 57 d0 vxorps %xmm0,%xmm1,%xmm2{z} + libdis_test+0x6fe: 62 f1 64 88 57 20 vxorps (%rax),%xmm3,%xmm4{z} + libdis_test+0x704: 62 f1 54 88 57 b1 vxorps 0x42(%rcx),%xmm5,%xmm6{z} + 42 00 00 00 + libdis_test+0x70e: 62 f1 74 a8 57 d0 vxorps %ymm0,%ymm1,%ymm2{z} + libdis_test+0x714: 62 f1 64 a8 57 23 vxorps (%rbx),%ymm3,%ymm4{z} + libdis_test+0x71a: 62 f1 54 a8 57 b2 vxorps 0x42(%rdx),%ymm5,%ymm6{z} + 42 00 00 00 + libdis_test+0x724: 62 f1 74 48 57 d0 vxorps %zmm0,%zmm1,%zmm2 + libdis_test+0x72a: 62 f1 64 48 57 23 vxorps (%rbx),%zmm3,%zmm4 + libdis_test+0x730: 62 f1 54 48 57 b2 vxorps 0x42(%rdx),%zmm5,%zmm6 + 42 00 00 00 diff --git a/usr/src/test/util-tests/tests/dis/i386/64.avx512.s b/usr/src/test/util-tests/tests/dis/i386/64.avx512.s index f038534dbf..c7e25b7328 100755 --- a/usr/src/test/util-tests/tests/dis/i386/64.avx512.s +++ b/usr/src/test/util-tests/tests/dis/i386/64.avx512.s @@ -14,7 +14,7 @@ */ /* - * Basic test for AVX512 mov instructions + * Basic tests for AVX512 instructions */ .text @@ -154,4 +154,165 @@ libdis_test: vmovdqu16 (%rsp), %zmm20 vmovdqu32 (%rsp), %zmm20 vmovdqu64 (%rsp), %zmm20 + + vandnpd %xmm0, %xmm1, %xmm2{z} + vandnpd (%rax), %xmm3, %xmm4{z} + vandnpd 0x42(%rcx), %xmm5, %xmm6{z} + vandnpd %ymm0, %ymm1, %ymm2{z} + vandnpd (%rbx), %ymm3, %ymm4{z} + vandnpd 0x42(%rdx), %ymm5, %ymm6{z} + vandnpd %zmm0, %zmm1, %zmm2 + vandnpd (%rbx), %zmm3, %zmm4 + vandnpd 0x42(%rdx), %zmm5, %zmm6 + + vandnps %xmm0, %xmm1, %xmm2{z} + vandnps (%rax), %xmm3, %xmm4{z} + vandnps 0x42(%rcx), %xmm5, %xmm6{z} + vandnps %ymm0, %ymm1, %ymm2{z} + vandnps (%rbx), %ymm3, %ymm4{z} + vandnps 0x42(%rdx), %ymm5, %ymm6{z} + vandnps %zmm0, %zmm1, %zmm2 + vandnps (%rbx), %zmm3, %zmm4 + vandnps 0x42(%rdx), %zmm5, %zmm6 + + vandpd %xmm0, %xmm1, %xmm2{z} + vandpd (%rax), %xmm3, %xmm4{z} + vandpd 0x42(%rcx), %xmm5, %xmm6{z} + vandpd %ymm0, %ymm1, %ymm2{z} + vandpd (%rbx), %ymm3, %ymm4{z} + vandpd 0x42(%rdx), %ymm5, %ymm6{z} + vandpd %zmm0, %zmm1, %zmm2 + vandpd (%rbx), %zmm3, %zmm4 + vandpd 0x42(%rdx), %zmm5, %zmm6 + + vandps %xmm0, %xmm1, %xmm2{z} + vandps (%rax), %xmm3, %xmm4{z} + vandps 0x42(%rcx), %xmm5, %xmm6{z} + vandps %ymm0, %ymm1, %ymm2{z} + vandps (%rbx), %ymm3, %ymm4{z} + vandps 0x42(%rdx), %ymm5, %ymm6{z} + vandps %zmm0, %zmm1, %zmm2 + vandps (%rbx), %zmm3, %zmm4 + vandps 0x42(%rdx), %zmm5, %zmm6 + + vpandd %xmm0, %xmm1, %xmm2 + vpandd (%rax), %xmm3, %xmm4 + vpandd 0x42(%rcx), %xmm5, %xmm6 + vpandd %ymm0, %ymm1, %ymm2 + vpandd (%rbx), %ymm3, %ymm4 + vpandd 0x42(%rdx), %ymm5, %ymm6 + vpandd %zmm0, %zmm1, %zmm2 + vpandd (%rbx), %zmm3, %zmm4 + vpandd 0x42(%rdx), %zmm5, %zmm6 + + vpandq %xmm0, %xmm1, %xmm2 + vpandq (%rax), %xmm3, %xmm4 + vpandq 0x42(%rcx), %xmm5, %xmm6 + vpandq %ymm0, %ymm1, %ymm2 + vpandq (%rbx), %ymm3, %ymm4 + vpandq 0x42(%rdx), %ymm5, %ymm6 + vpandq %zmm0, %zmm1, %zmm2 + vpandq (%rbx), %zmm3, %zmm4 + vpandq 0x42(%rdx), %zmm5, %zmm6 + + vpandnd %xmm0, %xmm1, %xmm2 + vpandnd (%rax), %xmm3, %xmm4 + vpandnd 0x42(%rcx), %xmm5, %xmm6 + vpandnd %ymm0, %ymm1, %ymm2 + vpandnd (%rbx), %ymm3, %ymm4 + vpandnd 0x42(%rdx), %ymm5, %ymm6 + vpandnd %zmm0, %zmm1, %zmm2 + vpandnd (%rbx), %zmm3, %zmm4 + vpandnd 0x42(%rdx), %zmm5, %zmm6 + + vpandnq %xmm0, %xmm1, %xmm2 + vpandnq (%rax), %xmm3, %xmm4 + vpandnq 0x42(%rcx), %xmm5, %xmm6 + vpandnq %ymm0, %ymm1, %ymm2 + vpandnq (%rbx), %ymm3, %ymm4 + vpandnq 0x42(%rdx), %ymm5, %ymm6 + vpandnq %zmm0, %zmm1, %zmm2 + vpandnq (%rbx), %zmm3, %zmm4 + vpandnq 0x42(%rdx), %zmm5, %zmm6 + + vorpd %xmm0, %xmm1, %xmm2{z} + vorpd (%rax), %xmm3, %xmm4{z} + vorpd 0x42(%rcx), %xmm5, %xmm6{z} + vorpd %ymm0, %ymm1, %ymm2{z} + vorpd (%rbx), %ymm3, %ymm4{z} + vorpd 0x42(%rdx), %ymm5, %ymm6{z} + vorpd %zmm0, %zmm1, %zmm2 + vorpd (%rax), %zmm3, %zmm4 + vorpd 0x42(%rcx), %zmm5, %zmm6 + + vorps %xmm0, %xmm1, %xmm2{z} + vorps (%rax), %xmm3, %xmm4{z} + vorps 0x42(%rcx), %xmm5, %xmm6{z} + vorps %ymm0, %ymm1, %ymm2{z} + vorps (%rbx), %ymm3, %ymm4{z} + vorps 0x42(%rdx), %ymm5, %ymm6{z} + vorps %zmm0, %zmm1, %zmm2 + vorps (%rax), %zmm3, %zmm4 + vorps 0x42(%rcx), %zmm5, %zmm6 + + vpord %xmm0, %xmm1, %xmm2 + vpord (%rax), %xmm3, %xmm4 + vpord 0x42(%rcx), %xmm5, %xmm6 + vpord %ymm0, %ymm1, %ymm2 + vpord (%rbx), %ymm3, %ymm4 + vpord 0x42(%rdx), %ymm5, %ymm6 + vpord %zmm0, %zmm1, %zmm2 + vpord (%rax), %zmm3, %zmm4 + vpord 0x42(%rcx), %zmm5, %zmm6 + + vporq %xmm0, %xmm1, %xmm2 + vporq (%rax), %xmm3, %xmm4 + vporq 0x42(%rcx), %xmm5, %xmm6 + vporq %ymm0, %ymm1, %ymm2 + vporq (%rbx), %ymm3, %ymm4 + vporq 0x42(%rdx), %ymm5, %ymm6 + vporq %zmm0, %zmm1, %zmm2 + vporq (%rax), %zmm3, %zmm4 + vporq 0x42(%rcx), %zmm5, %zmm6 + + vpxord %xmm0, %xmm1, %xmm2 + vpxord (%rax), %xmm3, %xmm4 + vpxord 0x42(%rcx), %xmm5, %xmm6 + vpxord %ymm0, %ymm1, %ymm2 + vpxord (%rbx), %ymm3, %ymm4 + vpxord 0x42(%rdx), %ymm5, %ymm6 + vpxord %zmm0, %zmm1, %zmm2 + vpxord (%rax), %zmm3, %zmm4 + vpxord 0x42(%rcx), %zmm5, %zmm6 + + vpxorq %xmm0, %xmm1, %xmm2 + vpxorq (%rax), %xmm3, %xmm4 + vpxorq 0x42(%rcx), %xmm5, %xmm6 + vpxorq %ymm0, %ymm1, %ymm2 + vpxorq (%rbx), %ymm3, %ymm4 + vpxorq 0x42(%rdx), %ymm5, %ymm6 + vpxorq %zmm0, %zmm1, %zmm2 + vpxorq (%rax), %zmm3, %zmm4 + vpxorq 0x42(%rcx), %zmm5, %zmm6 + + vxorpd %xmm0, %xmm1, %xmm2{z} + vxorpd (%rax), %xmm3, %xmm4{z} + vxorpd 0x42(%rcx), %xmm5, %xmm6{z} + vxorpd %ymm0, %ymm1, %ymm2{z} + vxorpd (%rbx), %ymm3, %ymm4{z} + vxorpd 0x42(%rdx), %ymm5, %ymm6{z} + vxorpd %zmm0, %zmm1, %zmm2 + vxorpd (%rbx), %zmm3, %zmm4 + vxorpd 0x42(%rdx), %zmm5, %zmm6 + + vxorps %xmm0, %xmm1, %xmm2{z} + vxorps (%rax), %xmm3, %xmm4{z} + vxorps 0x42(%rcx), %xmm5, %xmm6{z} + vxorps %ymm0, %ymm1, %ymm2{z} + vxorps (%rbx), %ymm3, %ymm4{z} + vxorps 0x42(%rdx), %ymm5, %ymm6{z} + vxorps %zmm0, %zmm1, %zmm2 + vxorps (%rbx), %zmm3, %zmm4 + vxorps 0x42(%rdx), %zmm5, %zmm6 + .size libdis_test, [.-libdis_test] -- 2.11.4.GIT