From 81b505b772ab015c588c56bb116239ee549b6eee Mon Sep 17 00:00:00 2001 From: Jerry Jelinek Date: Mon, 5 Jun 2017 20:53:36 +0000 Subject: [PATCH] 8384 AVX512 dis - EVEX prefix support 8385 32-bit avx dis test mishandles EVEX prefix 8386 32-bit bound dis is incorrect Reviewed by: Robert Mustacchi Reviewed by: Gordon Ross Approved by: Richard Lowe --- usr/src/common/dis/i386/dis_tables.c | 415 ++++++- usr/src/pkg/manifests/system-test-utiltest.mf | 4 + usr/src/test/util-tests/tests/dis/Makefile | 2 + usr/src/test/util-tests/tests/dis/i386/32.avx.out | 1272 ++++++++++---------- usr/src/test/util-tests/tests/dis/i386/32.avx.s | 22 +- .../test/util-tests/tests/dis/i386/32.avx512.out | 97 ++ usr/src/test/util-tests/tests/dis/i386/32.avx512.s | 100 ++ .../test/util-tests/tests/dis/i386/64.avx512.out | 162 +++ usr/src/test/util-tests/tests/dis/i386/64.avx512.s | 157 +++ 9 files changed, 1571 insertions(+), 660 deletions(-) create mode 100644 usr/src/test/util-tests/tests/dis/i386/32.avx512.out create mode 100755 usr/src/test/util-tests/tests/dis/i386/32.avx512.s create mode 100644 usr/src/test/util-tests/tests/dis/i386/64.avx512.out create mode 100755 usr/src/test/util-tests/tests/dis/i386/64.avx512.s diff --git a/usr/src/common/dis/i386/dis_tables.c b/usr/src/common/dis/i386/dis_tables.c index beb1296f57..000cb020f3 100644 --- a/usr/src/common/dis/i386/dis_tables.c +++ b/usr/src/common/dis/i386/dis_tables.c @@ -242,7 +242,10 @@ enum { SVM, /* AMD SVM instructions */ BLS, /* BLSR, BLSMSK, BLSI */ FMA, /* FMA instructions, all VEX_RMrX */ - ADX /* ADX instructions, support REX.w, mod_rm->mod_reg */ + ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */ + EVEX_RX, /* EVEX mod_reg -> mod_rm */ + EVEX_MX, /* EVEX mod_rm -> mod_reg */ + EVEX_RMrX /* EVEX EVEX.vvvv, mod_rm -> mod_reg */ }; /* @@ -476,14 +479,37 @@ const char *const dis_MMREG[16] = { "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" }; -const char *const dis_XMMREG[16] = { - "%xmm0", "%xmm1", "%xmm2", "%xmm3", "%xmm4", "%xmm5", "%xmm6", "%xmm7", - "%xmm8", "%xmm9", "%xmm10", "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15" +const char *const dis_XMMREG[32] = { + "%xmm0", "%xmm1", "%xmm2", "%xmm3", + "%xmm4", "%xmm5", "%xmm6", "%xmm7", + "%xmm8", "%xmm9", "%xmm10", "%xmm11", + "%xmm12", "%xmm13", "%xmm14", "%xmm15", + "%xmm16", "%xmm17", "%xmm18", "%xmm19", + "%xmm20", "%xmm21", "%xmm22", "%xmm23", + "%xmm24", "%xmm25", "%xmm26", "%xmm27", + "%xmm28", "%xmm29", "%xmm30", "%xmm31", }; -const char *const dis_YMMREG[16] = { - "%ymm0", "%ymm1", "%ymm2", "%ymm3", "%ymm4", "%ymm5", "%ymm6", "%ymm7", - "%ymm8", "%ymm9", "%ymm10", "%ymm11", "%ymm12", "%ymm13", "%ymm14", "%ymm15" +const char *const dis_YMMREG[32] = { + "%ymm0", "%ymm1", "%ymm2", "%ymm3", + "%ymm4", "%ymm5", "%ymm6", "%ymm7", + "%ymm8", "%ymm9", "%ymm10", "%ymm11", + "%ymm12", "%ymm13", "%ymm14", "%ymm15", + "%ymm16", "%ymm17", "%ymm18", "%ymm19", + "%ymm20", "%ymm21", "%ymm22", "%ymm23", + "%ymm24", "%ymm25", "%ymm26", "%ymm27", + "%ymm28", "%ymm29", "%ymm30", "%ymm31", +}; + +const char *const dis_ZMMREG[32] = { + "%zmm0", "%zmm1", "%zmm2", "%zmm3", + "%zmm4", "%zmm5", "%zmm6", "%zmm7", + "%zmm8", "%zmm9", "%zmm10", "%zmm11", + "%zmm12", "%zmm13", "%zmm14", "%zmm15", + "%zmm16", "%zmm17", "%zmm18", "%zmm19", + "%zmm20", "%zmm21", "%zmm22", "%zmm23", + "%zmm24", "%zmm25", "%zmm26", "%zmm27", + "%zmm28", "%zmm29", "%zmm30", "%zmm31", }; const char *const dis_KOPMASKREG[8] = { @@ -1406,6 +1432,92 @@ const instable_t dis_opAVXF30F[256] = { /* [F8] */ INVALID, INVALID, INVALID, INVALID, /* [FC] */ INVALID, INVALID, INVALID, INVALID, }; + +/* + * Table for instructions with an EVEX prefix. + */ +const instable_t dis_opAVX62[256] = { +/* [00] */ INVALID, INVALID, INVALID, INVALID, +/* [04] */ INVALID, INVALID, INVALID, INVALID, +/* [08] */ INVALID, INVALID, INVALID, INVALID, +/* [0C] */ INVALID, INVALID, INVALID, INVALID, + +/* [10] */ TNS("vmovup",EVEX_MX), TNS("vmovup",EVEX_RX), INVALID, INVALID, +/* [14] */ INVALID, INVALID, INVALID, INVALID, +/* [18] */ INVALID, INVALID, INVALID, INVALID, +/* [1C] */ INVALID, INVALID, INVALID, INVALID, + +/* [20] */ INVALID, INVALID, INVALID, INVALID, +/* [24] */ INVALID, INVALID, INVALID, INVALID, +/* [28] */ TNS("vmovap",EVEX_MX), TNS("vmovap",EVEX_RX), INVALID, INVALID, +/* [2C] */ INVALID, INVALID, INVALID, INVALID, + +/* [30] */ INVALID, INVALID, INVALID, INVALID, +/* [34] */ INVALID, INVALID, INVALID, INVALID, +/* [38] */ INVALID, INVALID, INVALID, INVALID, +/* [3C] */ INVALID, INVALID, INVALID, INVALID, + +/* [40] */ INVALID, INVALID, INVALID, INVALID, +/* [44] */ INVALID, INVALID, INVALID, INVALID, +/* [48] */ INVALID, INVALID, INVALID, INVALID, +/* [4C] */ INVALID, INVALID, INVALID, INVALID, + +/* [50] */ INVALID, INVALID, INVALID, INVALID, +/* [54] */ INVALID, INVALID, INVALID, INVALID, +/* [58] */ INVALID, INVALID, INVALID, INVALID, +/* [5C] */ INVALID, INVALID, INVALID, INVALID, + +/* [60] */ INVALID, INVALID, INVALID, INVALID, +/* [64] */ INVALID, INVALID, INVALID, INVALID, +/* [68] */ INVALID, INVALID, INVALID, INVALID, +/* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_MX), + +/* [70] */ INVALID, INVALID, INVALID, INVALID, +/* [74] */ INVALID, INVALID, INVALID, INVALID, +/* [78] */ INVALID, INVALID, INVALID, INVALID, +/* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_RX), + +/* [80] */ INVALID, INVALID, INVALID, INVALID, +/* [84] */ INVALID, INVALID, INVALID, INVALID, +/* [88] */ INVALID, INVALID, INVALID, INVALID, +/* [0C] */ INVALID, INVALID, INVALID, INVALID, + +/* [90] */ INVALID, INVALID, INVALID, INVALID, +/* [94] */ INVALID, INVALID, INVALID, INVALID, +/* [98] */ INVALID, INVALID, INVALID, INVALID, +/* [9C] */ INVALID, INVALID, INVALID, INVALID, + +/* [A0] */ INVALID, INVALID, INVALID, INVALID, +/* [A4] */ INVALID, INVALID, INVALID, INVALID, +/* [A8] */ INVALID, INVALID, INVALID, INVALID, +/* [AC] */ INVALID, INVALID, INVALID, INVALID, + +/* [B0] */ INVALID, INVALID, INVALID, INVALID, +/* [B4] */ INVALID, INVALID, INVALID, INVALID, +/* [B8] */ INVALID, INVALID, INVALID, INVALID, +/* [BC] */ INVALID, INVALID, INVALID, INVALID, + +/* [C0] */ INVALID, INVALID, INVALID, INVALID, +/* [C4] */ INVALID, INVALID, INVALID, INVALID, +/* [C8] */ INVALID, INVALID, INVALID, INVALID, +/* [CC] */ INVALID, INVALID, INVALID, INVALID, + +/* [D0] */ INVALID, INVALID, INVALID, INVALID, +/* [D4] */ INVALID, INVALID, INVALID, INVALID, +/* [D8] */ INVALID, INVALID, INVALID, INVALID, +/* [DC] */ INVALID, INVALID, INVALID, INVALID, + +/* [E0] */ INVALID, INVALID, INVALID, INVALID, +/* [E4] */ INVALID, INVALID, INVALID, INVALID, +/* [E8] */ INVALID, INVALID, INVALID, INVALID, +/* [EC] */ INVALID, INVALID, INVALID, INVALID, + +/* [F0] */ INVALID, INVALID, INVALID, INVALID, +/* [F4] */ INVALID, INVALID, INVALID, INVALID, +/* [F8] */ INVALID, INVALID, INVALID, INVALID, +/* [FC] */ INVALID, INVALID, INVALID, INVALID, +}; + /* * The following two tables are used to encode crc32 and movbe * since they share the same opcodes. @@ -2210,7 +2322,7 @@ const instable_t dis_distable[16][16] = { /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), }, { -/* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",MR), TNS("arpl",RMw), +/* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw), /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), @@ -2285,16 +2397,25 @@ const instable_t dis_distable[16][16] = { #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ /* - * These are the individual fields of a VEX prefix. + * These are the individual fields of a VEX/EVEX prefix. */ #define VEX_R 0x08 /* REX.R in 1's complement form */ #define VEX_X 0x04 /* REX.X in 1's complement form */ #define VEX_B 0x02 /* REX.B in 1's complement form */ + +/* Additional EVEX prefix definitions */ +#define EVEX_R 0x01 /* REX.R' in 1's complement form */ +#define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */ +#define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */ + /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ #define VEX_L 0x04 +/* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */ +#define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */ #define VEX_W 0x08 /* opcode specific, use like REX.W */ #define VEX_m 0x1F /* VEX m-mmmm field */ -#define VEX_v 0x78 /* VEX register specifier */ +#define EVEX_m 0x3 /* EVEX mm field */ +#define VEX_v 0x78 /* VEX/EVEX register specifier */ #define VEX_p 0x03 /* VEX pp field, opcode extension */ /* VEX m-mmmm field, only used by three bytes prefix */ @@ -2335,6 +2456,7 @@ static int isize64[] = {1, 2, 4, 8}; #define WORD_OPND 8 /* w-bit value indicating word size reg */ #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ +#define ZMM_OPND 11 /* "value" used to indicate a zmm reg */ /* * The AVX2 gather instructions are a bit of a mess. While there's a pattern, @@ -2512,6 +2634,155 @@ dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) } /* + * Adjust the instruction mnemonic with the appropriate suffix. + */ +/* ARGSUSED */ +static void +dtrace_evex_mnem_adjust(dis86_t *x, instable_t *dp, uint_t vex_W, + uint_t evex_byte2) +{ +#ifdef DIS_TEXT + if (dp == &dis_opAVX62[0x7f] || /* vmovdq */ + dp == &dis_opAVX62[0x6f]) { + /* Aligned or Unaligned? */ + if ((evex_byte2 & 0x3) == 0x01) { + (void) strlcat(x->d86_mnem, "a", OPLEN); + (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32", + OPLEN); + } else { + (void) strlcat(x->d86_mnem, "u", OPLEN); + switch (evex_byte2 & 0x81) { + case 0x0: + (void) strlcat(x->d86_mnem, "32", OPLEN); + break; + case 0x1: + (void) strlcat(x->d86_mnem, "8", OPLEN); + break; + case 0x80: + (void) strlcat(x->d86_mnem, "64", OPLEN); + break; + case 0x81: + (void) strlcat(x->d86_mnem, "16", OPLEN); + break; + } + } + + } else { + (void) strlcat(x->d86_mnem, vex_W != 0 ? "d" : "s", OPLEN); + } +#endif +} + +/* + * The following three functions adjust the register selection based on any + * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software + * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and + * section 2.6.2 Table 2-31. + */ +static void +dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg) +{ + if (reg != NULL) { + if ((VEX_R & evex_byte1) == 0) { + *reg += 8; + } + if ((EVEX_R & evex_byte1) == 0) { + *reg += 16; + } + } +} + +static void +dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m) +{ + if (r_m != NULL) { + if ((VEX_B & evex_byte1) == 0) { + *r_m += 8; + } + if ((VEX_X & evex_byte1) == 0) { + *r_m += 16; + } + } +} + +/* + * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36. + */ +static void +dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp) +{ + switch (evex_L) { + case 0x0: + *wbitp = XMM_OPND; + break; + case 0x1: + *wbitp = YMM_OPND; + break; + case 0x2: + *wbitp = ZMM_OPND; + break; + } +} + +/* + * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5. + * This currently only handles a subset of the possibilities. + */ +static void +dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) +{ + d86opnd_t *opnd = &x->d86_opnd[opindex]; + + if (x->d86_error) + return; + + /* Check disp8 bit in the ModR/M byte */ + if ((modrm & 0x80) == 0x80) + return; + + /* use evex_L to adjust the value */ + switch (L) { + case 0x0: + opnd->d86_value *= 16; + break; + case 0x1: + opnd->d86_value *= 32; + break; + case 0x2: + opnd->d86_value *= 64; + break; + } +} + +/* + * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30. + */ +/* ARGSUSED */ +static void +dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t evex_byte3) +{ +#ifdef DIS_TEXT + char *opnd = x->d86_opnd[1].d86_opnd; + int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; +#endif + if (x->d86_error) + return; + +#ifdef DIS_TEXT + if (opmask_reg != 0) { + /* Append the opmask register to operand 1 */ + (void) strlcat(opnd, "{", OPLEN); + (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN); + (void) strlcat(opnd, "}", OPLEN); + } + if ((evex_byte3 & EVEX_ZERO_MASK) != 0) { + /* Append the 'zeroing' modifier to operand 1 */ + (void) strlcat(opnd, "{z}", OPLEN); + } +#endif /* DIS_TEXT */ +} + +/* * Get an immediate operand of the given size, with sign extension. */ static void @@ -2539,6 +2810,7 @@ dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) case MM_OPND: case XMM_OPND: case YMM_OPND: + case ZMM_OPND: case SEG_OPND: case CONTROL_OPND: case DEBUG_OPND: @@ -2652,6 +2924,9 @@ dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) case YMM_OPND: (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); break; + case ZMM_OPND: + (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN); + break; case KOPMASK_OPND: (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); break; @@ -2792,10 +3067,13 @@ dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) regs = (char **)dis_REG64; if (x->d86_vsib != 0) { - if (wbit == YMM_OPND) /* NOTE this is not addr_size! */ + if (wbit == YMM_OPND) { /* NOTE this is not addr_size */ bregs = (char **)dis_YMMREG; - else + } else if (wbit == XMM_OPND) { bregs = (char **)dis_XMMREG; + } else { + bregs = (char **)dis_ZMMREG; + } sf = dis_vscale_factor; } else { bregs = regs; @@ -2930,6 +3208,8 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode) uint_t opcode5; /* low nibble of 2nd byte */ uint_t opcode6; /* high nibble of 3rd byte */ uint_t opcode7; /* low nibble of 3rd byte */ + uint_t opcode8; /* high nibble of 4th byte */ + uint_t opcode9; /* low nibble of 4th byte */ uint_t opcode_bytes = 1; /* @@ -2956,6 +3236,13 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode) uint_t vex_byte1 = 0; /* + * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r. + */ + uint_t evex_byte1 = 0; + uint_t evex_byte2 = 0; + uint_t evex_byte3 = 0; + + /* * For 32-bit mode, it should prefetch the next byte to * distinguish between AVX and les/lds */ @@ -2969,6 +3256,8 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode) uint_t vex_B = 1; uint_t vex_W = 0; uint_t vex_L; + uint_t evex_L; + uint_t evex_modrm; dis_gather_regs_t *vreg; #ifdef DIS_TEXT @@ -3097,6 +3386,75 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode) } } + /* + * The EVEX prefix and "bound" instruction share the same first byte. + * "bound" is only valid for 32-bit. For 64-bit this byte begins the + * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0. + */ + if (opcode1 == 0x6 && opcode2 == 0x2) { + /* + * An EVEX prefix is 4 bytes long, get the next 3 bytes. + */ + if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) + goto error; + + if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) { + /* + * Upper bits in 2nd byte == 0 is 'bound' instn. + * + * We've already read the byte so perform the + * equivalent of dtrace_get_modrm on the byte and set + * the flag to indicate we've already read it. + */ + char b = (opcode4 << 4) | opcode5; + + r_m = b & 0x7; + reg = (b >> 3) & 0x7; + mode = (b >> 6) & 0x3; + vex_prefetch = 1; + goto not_avx512; + } + + /* check for correct bits being 0 in 2nd byte */ + if ((opcode5 & 0xc) != 0) + goto error; + + if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) + goto error; + /* check for correct bit being 1 in 3rd byte */ + if ((opcode7 & 0x4) == 0) + goto error; + + if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0) + goto error; + + /* Reuse opcode1 & opcode2 to get the real opcode now */ + if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) + goto error; + + /* + * We only use the high nibble from the 2nd byte of the prefix + * and save it in the low bits of evex_byte1. This is because + * two of the bits in opcode5 are constant 0 (checked above), + * and the other two bits are captured in vex_m. Also, the VEX + * constants we check in evex_byte1 are against the low bits. + */ + evex_byte1 = opcode4; + evex_byte2 = (opcode6 << 4) | opcode7; + evex_byte3 = (opcode8 << 4) | opcode9; + + vex_m = opcode5 & EVEX_m; + vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3; + vex_W = (opcode6 & VEX_W) >> 3; + vex_p = opcode7 & VEX_p; + + /* Currently only 3 valid values for evex L'L: 00, 01, 10 */ + evex_L = (opcode8 & EVEX_L) >> 1; + + dp = (instable_t *)&dis_opAVX62[(opcode1 << 4) | opcode2]; + } +not_avx512: + if (vex_prefix == VEX_2bytes) { if (!vex_prefetch) { if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) @@ -3743,7 +4101,8 @@ dtrace_disx86(dis86_t *x, uint_t cpu_mode) * To handle PINSRD and PEXTRD */ (void) strlcat(x->d86_mnem, "d", OPLEN); - } else { + } else if (dp != &dis_distable[0x6][0x2]) { + /* bound instructions (0x62) have no suffix */ (void) strlcat(x->d86_mnem, types[opnd_size], OPLEN); } @@ -4285,6 +4644,8 @@ just_mem: case RM: case RM_66r: + if (vex_prefetch) + x->d86_got_modrm = 1; wbit = LONG_OPND; STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); break; @@ -5398,6 +5759,34 @@ L_VEX_RM: dtrace_get_operand(x, mode, r_m, wbit, 0); break; } + case EVEX_MX: + /* ModR/M.reg := op(ModR/M.rm) */ + x->d86_numopnds = 2; + dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); + dtrace_get_modrm(x, &mode, ®, &r_m); + evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; + dtrace_evex_adjust_reg(evex_byte1, ®); + dtrace_evex_adjust_rm(evex_byte1, &r_m); + dtrace_evex_adjust_reg_name(evex_L, &wbit); + dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); + dtrace_evex_adjust_z_opmask(x, evex_byte3); + dtrace_get_operand(x, mode, r_m, wbit, 0); + dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); + break; + case EVEX_RX: + /* ModR/M.rm := op(ModR/M.reg) */ + x->d86_numopnds = 2; + dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); + dtrace_get_modrm(x, &mode, ®, &r_m); + evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; + dtrace_evex_adjust_reg(evex_byte1, ®); + dtrace_evex_adjust_rm(evex_byte1, &r_m); + dtrace_evex_adjust_reg_name(evex_L, &wbit); + dtrace_get_operand(x, mode, r_m, wbit, 1); + dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); + dtrace_evex_adjust_z_opmask(x, evex_byte3); + dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); + break; /* an invalid op code */ case AM: case DM: diff --git a/usr/src/pkg/manifests/system-test-utiltest.mf b/usr/src/pkg/manifests/system-test-utiltest.mf index eacc8a3f52..a8cab5ba5c 100644 --- a/usr/src/pkg/manifests/system-test-utiltest.mf +++ b/usr/src/pkg/manifests/system-test-utiltest.mf @@ -42,6 +42,8 @@ file path=opt/util-tests/tests/dis/i386/32.avx.out mode=0555 file path=opt/util-tests/tests/dis/i386/32.avx.s mode=0555 file path=opt/util-tests/tests/dis/i386/32.avx2.out mode=0555 file path=opt/util-tests/tests/dis/i386/32.avx2.s mode=0555 +file path=opt/util-tests/tests/dis/i386/32.avx512.out mode=0555 +file path=opt/util-tests/tests/dis/i386/32.avx512.s mode=0555 file path=opt/util-tests/tests/dis/i386/32.bmi1.out mode=0555 file path=opt/util-tests/tests/dis/i386/32.bmi1.s mode=0555 file path=opt/util-tests/tests/dis/i386/32.bmi2.out mode=0555 @@ -86,6 +88,8 @@ file path=opt/util-tests/tests/dis/i386/64.avx.out mode=0555 file path=opt/util-tests/tests/dis/i386/64.avx.s mode=0555 file path=opt/util-tests/tests/dis/i386/64.avx2.out mode=0555 file path=opt/util-tests/tests/dis/i386/64.avx2.s mode=0555 +file path=opt/util-tests/tests/dis/i386/64.avx512.out mode=0555 +file path=opt/util-tests/tests/dis/i386/64.avx512.s mode=0555 file path=opt/util-tests/tests/dis/i386/64.bmi1.out mode=0555 file path=opt/util-tests/tests/dis/i386/64.bmi1.s mode=0555 file path=opt/util-tests/tests/dis/i386/64.bmi2.out mode=0555 diff --git a/usr/src/test/util-tests/tests/dis/Makefile b/usr/src/test/util-tests/tests/dis/Makefile index ccc5dfcb3f..53cf7ccd40 100644 --- a/usr/src/test/util-tests/tests/dis/Makefile +++ b/usr/src/test/util-tests/tests/dis/Makefile @@ -28,6 +28,7 @@ I386_TESTS = \ 32.adx \ 32.avx \ 32.avx2 \ + 32.avx512 \ 32.aes \ 32.bmi1 \ 32.bmi2 \ @@ -49,6 +50,7 @@ I386_TESTS = \ 32.xsave \ 64.avx \ 64.avx2 \ + 64.avx512 \ 64.adx \ 64.aes \ 64.bmi1 \ diff --git a/usr/src/test/util-tests/tests/dis/i386/32.avx.out b/usr/src/test/util-tests/tests/dis/i386/32.avx.out index 4bba31418d..12b56c60d0 100644 --- a/usr/src/test/util-tests/tests/dis/i386/32.avx.out +++ b/usr/src/test/util-tests/tests/dis/i386/32.avx.out @@ -1315,670 +1315,656 @@ libdis_test+0x1932: c4 e3 79 16 0b 23 vpextrd $0x23,%xmm1,(%ebx) libdis_test+0x1938: c4 e3 79 16 51 16 vpextrd $0x23,%xmm2,0x16(%ecx) 23 - libdis_test+0x193f: 62 f3 boundl %ebx,%esi - libdis_test+0x1941: fd std - libdis_test+0x1942: 08 16 orb %dl,(%esi) - libdis_test+0x1944: 0b 23 orl (%ebx),%esp - libdis_test+0x1946: 62 f3 boundl %ebx,%esi - libdis_test+0x1948: fd std - libdis_test+0x1949: 08 16 orb %dl,(%esi) - libdis_test+0x194b: 91 xchgl %ecx,%eax - libdis_test+0x194c: 16 pushl %ss - libdis_test+0x194d: 00 00 addb %al,(%eax) - libdis_test+0x194f: 00 23 addb %ah,(%ebx) - libdis_test+0x1951: c5 f9 c5 c0 23 vpextrw $0x23,%xmm0,%eax - libdis_test+0x1956: c4 e3 79 15 0b 23 vpextrw $0x23,%xmm1,(%ebx) - libdis_test+0x195c: c4 e3 79 15 51 16 vpextrw $0x23,%xmm2,0x16(%ecx) + libdis_test+0x193f: c4 e3 f9 16 0b 23 vpextrq $0x23,%xmm1,(%ebx) + libdis_test+0x1945: c4 e3 f9 16 51 16 vpextrq $0x23,%xmm2,0x16(%ecx) 23 - libdis_test+0x1963: c4 e2 71 02 d0 vphaddd %xmm0,%xmm1,%xmm2 - libdis_test+0x1968: c4 e2 61 02 20 vphaddd (%eax),%xmm3,%xmm4 - libdis_test+0x196d: c4 e2 51 02 71 42 vphaddd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1973: c4 e2 75 02 d0 vphaddd %ymm0,%ymm1,%ymm2 - libdis_test+0x1978: c4 e2 65 02 23 vphaddd (%ebx),%ymm3,%ymm4 - libdis_test+0x197d: c4 e2 55 02 72 42 vphaddd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1983: c4 e2 71 03 d0 vphaddsw %xmm0,%xmm1,%xmm2 - libdis_test+0x1988: c4 e2 61 03 20 vphaddsw (%eax),%xmm3,%xmm4 - libdis_test+0x198d: c4 e2 51 03 71 42 vphaddsw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1993: c4 e2 75 03 d0 vphaddsw %ymm0,%ymm1,%ymm2 - libdis_test+0x1998: c4 e2 65 03 23 vphaddsw (%ebx),%ymm3,%ymm4 - libdis_test+0x199d: c4 e2 55 03 72 42 vphaddsw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x19a3: c4 e2 71 01 d0 vphaddw %xmm0,%xmm1,%xmm2 - libdis_test+0x19a8: c4 e2 61 01 20 vphaddw (%eax),%xmm3,%xmm4 - libdis_test+0x19ad: c4 e2 51 01 71 42 vphaddw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x19b3: c4 e2 75 01 d0 vphaddw %ymm0,%ymm1,%ymm2 - libdis_test+0x19b8: c4 e2 65 01 23 vphaddw (%ebx),%ymm3,%ymm4 - libdis_test+0x19bd: c4 e2 55 01 72 42 vphaddw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x19c3: c4 e2 79 41 c8 vphminposuw %xmm0,%xmm1 - libdis_test+0x19c8: c4 e2 79 41 1e vphminposuw (%esi),%xmm3 - libdis_test+0x19cd: c4 e2 79 41 5f 42 vphminposuw 0x42(%edi),%xmm3 - libdis_test+0x19d3: c4 e2 71 06 d0 vphsubd %xmm0,%xmm1,%xmm2 - libdis_test+0x19d8: c4 e2 61 06 20 vphsubd (%eax),%xmm3,%xmm4 - libdis_test+0x19dd: c4 e2 51 06 71 42 vphsubd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x19e3: c4 e2 75 06 d0 vphsubd %ymm0,%ymm1,%ymm2 - libdis_test+0x19e8: c4 e2 65 06 23 vphsubd (%ebx),%ymm3,%ymm4 - libdis_test+0x19ed: c4 e2 55 06 72 42 vphsubd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x19f3: c4 e2 71 07 d0 vphsubsw %xmm0,%xmm1,%xmm2 - libdis_test+0x19f8: c4 e2 61 07 20 vphsubsw (%eax),%xmm3,%xmm4 - libdis_test+0x19fd: c4 e2 51 07 71 42 vphsubsw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1a03: c4 e2 75 07 d0 vphsubsw %ymm0,%ymm1,%ymm2 - libdis_test+0x1a08: c4 e2 65 07 23 vphsubsw (%ebx),%ymm3,%ymm4 - libdis_test+0x1a0d: c4 e2 55 07 72 42 vphsubsw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1a13: c4 e2 71 05 d0 vphsubw %xmm0,%xmm1,%xmm2 - libdis_test+0x1a18: c4 e2 61 05 20 vphsubw (%eax),%xmm3,%xmm4 - libdis_test+0x1a1d: c4 e2 51 05 71 42 vphsubw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1a23: c4 e2 75 05 d0 vphsubw %ymm0,%ymm1,%ymm2 - libdis_test+0x1a28: c4 e2 65 05 23 vphsubw (%ebx),%ymm3,%ymm4 - libdis_test+0x1a2d: c4 e2 55 05 72 42 vphsubw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1a33: c4 e3 79 20 c8 20 vpinsrb $0x20,%eax,%xmm0,%xmm1 - libdis_test+0x1a39: c4 e3 69 20 1b 20 vpinsrb $0x20,(%ebx),%xmm2,%xmm3 - libdis_test+0x1a3f: c4 e3 69 20 5b 10 vpinsrb $0x20,0x10(%ebx),%xmm2,%xmm3 + libdis_test+0x194c: c5 f9 c5 c0 23 vpextrw $0x23,%xmm0,%eax + libdis_test+0x1951: c4 e3 79 15 0b 23 vpextrw $0x23,%xmm1,(%ebx) + libdis_test+0x1957: c4 e3 79 15 51 16 vpextrw $0x23,%xmm2,0x16(%ecx) + 23 + libdis_test+0x195e: c4 e2 71 02 d0 vphaddd %xmm0,%xmm1,%xmm2 + libdis_test+0x1963: c4 e2 61 02 20 vphaddd (%eax),%xmm3,%xmm4 + libdis_test+0x1968: c4 e2 51 02 71 42 vphaddd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x196e: c4 e2 75 02 d0 vphaddd %ymm0,%ymm1,%ymm2 + libdis_test+0x1973: c4 e2 65 02 23 vphaddd (%ebx),%ymm3,%ymm4 + libdis_test+0x1978: c4 e2 55 02 72 42 vphaddd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x197e: c4 e2 71 03 d0 vphaddsw %xmm0,%xmm1,%xmm2 + libdis_test+0x1983: c4 e2 61 03 20 vphaddsw (%eax),%xmm3,%xmm4 + libdis_test+0x1988: c4 e2 51 03 71 42 vphaddsw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x198e: c4 e2 75 03 d0 vphaddsw %ymm0,%ymm1,%ymm2 + libdis_test+0x1993: c4 e2 65 03 23 vphaddsw (%ebx),%ymm3,%ymm4 + libdis_test+0x1998: c4 e2 55 03 72 42 vphaddsw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x199e: c4 e2 71 01 d0 vphaddw %xmm0,%xmm1,%xmm2 + libdis_test+0x19a3: c4 e2 61 01 20 vphaddw (%eax),%xmm3,%xmm4 + libdis_test+0x19a8: c4 e2 51 01 71 42 vphaddw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x19ae: c4 e2 75 01 d0 vphaddw %ymm0,%ymm1,%ymm2 + libdis_test+0x19b3: c4 e2 65 01 23 vphaddw (%ebx),%ymm3,%ymm4 + libdis_test+0x19b8: c4 e2 55 01 72 42 vphaddw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x19be: c4 e2 79 41 c8 vphminposuw %xmm0,%xmm1 + libdis_test+0x19c3: c4 e2 79 41 1e vphminposuw (%esi),%xmm3 + libdis_test+0x19c8: c4 e2 79 41 5f 42 vphminposuw 0x42(%edi),%xmm3 + libdis_test+0x19ce: c4 e2 71 06 d0 vphsubd %xmm0,%xmm1,%xmm2 + libdis_test+0x19d3: c4 e2 61 06 20 vphsubd (%eax),%xmm3,%xmm4 + libdis_test+0x19d8: c4 e2 51 06 71 42 vphsubd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x19de: c4 e2 75 06 d0 vphsubd %ymm0,%ymm1,%ymm2 + libdis_test+0x19e3: c4 e2 65 06 23 vphsubd (%ebx),%ymm3,%ymm4 + libdis_test+0x19e8: c4 e2 55 06 72 42 vphsubd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x19ee: c4 e2 71 07 d0 vphsubsw %xmm0,%xmm1,%xmm2 + libdis_test+0x19f3: c4 e2 61 07 20 vphsubsw (%eax),%xmm3,%xmm4 + libdis_test+0x19f8: c4 e2 51 07 71 42 vphsubsw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x19fe: c4 e2 75 07 d0 vphsubsw %ymm0,%ymm1,%ymm2 + libdis_test+0x1a03: c4 e2 65 07 23 vphsubsw (%ebx),%ymm3,%ymm4 + libdis_test+0x1a08: c4 e2 55 07 72 42 vphsubsw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1a0e: c4 e2 71 05 d0 vphsubw %xmm0,%xmm1,%xmm2 + libdis_test+0x1a13: c4 e2 61 05 20 vphsubw (%eax),%xmm3,%xmm4 + libdis_test+0x1a18: c4 e2 51 05 71 42 vphsubw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1a1e: c4 e2 75 05 d0 vphsubw %ymm0,%ymm1,%ymm2 + libdis_test+0x1a23: c4 e2 65 05 23 vphsubw (%ebx),%ymm3,%ymm4 + libdis_test+0x1a28: c4 e2 55 05 72 42 vphsubw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1a2e: c4 e3 79 20 c8 20 vpinsrb $0x20,%eax,%xmm0,%xmm1 + libdis_test+0x1a34: c4 e3 69 20 1b 20 vpinsrb $0x20,(%ebx),%xmm2,%xmm3 + libdis_test+0x1a3a: c4 e3 69 20 5b 10 vpinsrb $0x20,0x10(%ebx),%xmm2,%xmm3 + 20 + libdis_test+0x1a41: c4 e3 79 22 c8 20 vpinsrd $0x20,%eax,%xmm0,%xmm1 + libdis_test+0x1a47: c4 e3 69 22 1b 20 vpinsrd $0x20,(%ebx),%xmm2,%xmm3 + libdis_test+0x1a4d: c4 e3 69 22 5b 10 vpinsrd $0x20,0x10(%ebx),%xmm2,%xmm3 20 - libdis_test+0x1a46: c4 e3 79 22 c8 20 vpinsrd $0x20,%eax,%xmm0,%xmm1 - libdis_test+0x1a4c: c4 e3 69 22 1b 20 vpinsrd $0x20,(%ebx),%xmm2,%xmm3 - libdis_test+0x1a52: c4 e3 69 22 5b 10 vpinsrd $0x20,0x10(%ebx),%xmm2,%xmm3 + libdis_test+0x1a54: c4 e3 c9 22 1b 20 vpinsrq $0x20,(%ebx),%xmm6,%xmm3 + libdis_test+0x1a5a: c4 e3 c9 22 5b 10 vpinsrq $0x20,0x10(%ebx),%xmm6,%xmm3 20 - libdis_test+0x1a59: 62 f3 boundl %ebx,%esi - libdis_test+0x1a5b: ed inl (%dx) - libdis_test+0x1a5c: 08 22 orb %ah,(%edx) - libdis_test+0x1a5e: 1b 20 sbbl (%eax),%esp - libdis_test+0x1a60: 62 f3 boundl %ebx,%esi - libdis_test+0x1a62: ed inl (%dx) - libdis_test+0x1a63: 08 22 orb %ah,(%edx) - libdis_test+0x1a65: 5b popl %ebx - libdis_test+0x1a66: 02 20 addb (%eax),%ah - libdis_test+0x1a68: c5 f9 c4 c8 20 vpinsrw $0x20,%eax,%xmm0,%xmm1 - libdis_test+0x1a6d: c5 e9 c4 1b 20 vpinsrw $0x20,(%ebx),%xmm2,%xmm3 - libdis_test+0x1a72: c5 e9 c4 5b 10 20 vpinsrw $0x20,0x10(%ebx),%xmm2,%xmm3 - libdis_test+0x1a78: c4 e2 71 04 d0 vpmaddubsw %xmm0,%xmm1,%xmm2 - libdis_test+0x1a7d: c4 e2 61 04 20 vpmaddubsw (%eax),%xmm3,%xmm4 - libdis_test+0x1a82: c4 e2 51 04 71 42 vpmaddubsw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1a88: c4 e2 75 04 d0 vpmaddubsw %ymm0,%ymm1,%ymm2 - libdis_test+0x1a8d: c4 e2 65 04 23 vpmaddubsw (%ebx),%ymm3,%ymm4 - libdis_test+0x1a92: c4 e2 55 04 72 42 vpmaddubsw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1a98: c5 f1 f5 d0 vpmaddwd %xmm0,%xmm1,%xmm2 - libdis_test+0x1a9c: c5 e1 f5 20 vpmaddwd (%eax),%xmm3,%xmm4 - libdis_test+0x1aa0: c5 d1 f5 71 42 vpmaddwd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1aa5: c5 f5 f5 d0 vpmaddwd %ymm0,%ymm1,%ymm2 - libdis_test+0x1aa9: c5 e5 f5 23 vpmaddwd (%ebx),%ymm3,%ymm4 - libdis_test+0x1aad: c5 d5 f5 72 42 vpmaddwd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1ab2: c4 e2 71 3c d0 vpmaxsb %xmm0,%xmm1,%xmm2 - libdis_test+0x1ab7: c4 e2 61 3c 20 vpmaxsb (%eax),%xmm3,%xmm4 - libdis_test+0x1abc: c4 e2 51 3c 71 42 vpmaxsb 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1ac2: c4 e2 75 3c d0 vpmaxsb %ymm0,%ymm1,%ymm2 - libdis_test+0x1ac7: c4 e2 65 3c 23 vpmaxsb (%ebx),%ymm3,%ymm4 - libdis_test+0x1acc: c4 e2 55 3c 72 42 vpmaxsb 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1ad2: c4 e2 71 3d d0 vpmaxsd %xmm0,%xmm1,%xmm2 - libdis_test+0x1ad7: c4 e2 61 3d 20 vpmaxsd (%eax),%xmm3,%xmm4 - libdis_test+0x1adc: c4 e2 51 3d 71 42 vpmaxsd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1ae2: c4 e2 75 3d d0 vpmaxsd %ymm0,%ymm1,%ymm2 - libdis_test+0x1ae7: c4 e2 65 3d 23 vpmaxsd (%ebx),%ymm3,%ymm4 - libdis_test+0x1aec: c4 e2 55 3d 72 42 vpmaxsd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1af2: c5 f1 ee d0 vpmaxsw %xmm0,%xmm1,%xmm2 - libdis_test+0x1af6: c5 e1 ee 20 vpmaxsw (%eax),%xmm3,%xmm4 - libdis_test+0x1afa: c5 d1 ee 71 42 vpmaxsw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1aff: c5 f5 ee d0 vpmaxsw %ymm0,%ymm1,%ymm2 - libdis_test+0x1b03: c5 e5 ee 23 vpmaxsw (%ebx),%ymm3,%ymm4 - libdis_test+0x1b07: c5 d5 ee 72 42 vpmaxsw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1b0c: c5 f1 de d0 vpmaxub %xmm0,%xmm1,%xmm2 - libdis_test+0x1b10: c5 e1 de 20 vpmaxub (%eax),%xmm3,%xmm4 - libdis_test+0x1b14: c5 d1 de 71 42 vpmaxub 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1b19: c5 f5 de d0 vpmaxub %ymm0,%ymm1,%ymm2 - libdis_test+0x1b1d: c5 e5 de 23 vpmaxub (%ebx),%ymm3,%ymm4 - libdis_test+0x1b21: c5 d5 de 72 42 vpmaxub 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1b26: c4 e2 71 3f d0 vpmaxud %xmm0,%xmm1,%xmm2 - libdis_test+0x1b2b: c4 e2 61 3f 20 vpmaxud (%eax),%xmm3,%xmm4 - libdis_test+0x1b30: c4 e2 51 3f 71 42 vpmaxud 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1b36: c4 e2 75 3f d0 vpmaxud %ymm0,%ymm1,%ymm2 - libdis_test+0x1b3b: c4 e2 65 3f 23 vpmaxud (%ebx),%ymm3,%ymm4 - libdis_test+0x1b40: c4 e2 55 3f 72 42 vpmaxud 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1b46: c4 e2 71 3e d0 vpmaxuw %xmm0,%xmm1,%xmm2 - libdis_test+0x1b4b: c4 e2 61 3e 20 vpmaxuw (%eax),%xmm3,%xmm4 - libdis_test+0x1b50: c4 e2 51 3e 71 42 vpmaxuw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1b56: c4 e2 75 3e d0 vpmaxuw %ymm0,%ymm1,%ymm2 - libdis_test+0x1b5b: c4 e2 65 3e 23 vpmaxuw (%ebx),%ymm3,%ymm4 - libdis_test+0x1b60: c4 e2 55 3e 72 42 vpmaxuw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1b66: c4 e2 71 38 d0 vpminsb %xmm0,%xmm1,%xmm2 - libdis_test+0x1b6b: c4 e2 61 38 20 vpminsb (%eax),%xmm3,%xmm4 - libdis_test+0x1b70: c4 e2 51 38 71 42 vpminsb 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1b76: c4 e2 75 38 d0 vpminsb %ymm0,%ymm1,%ymm2 - libdis_test+0x1b7b: c4 e2 65 38 23 vpminsb (%ebx),%ymm3,%ymm4 - libdis_test+0x1b80: c4 e2 55 38 72 42 vpminsb 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1b86: c4 e2 71 39 d0 vpminsd %xmm0,%xmm1,%xmm2 - libdis_test+0x1b8b: c4 e2 61 39 20 vpminsd (%eax),%xmm3,%xmm4 - libdis_test+0x1b90: c4 e2 51 39 71 42 vpminsd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1b96: c4 e2 75 39 d0 vpminsd %ymm0,%ymm1,%ymm2 - libdis_test+0x1b9b: c4 e2 65 39 23 vpminsd (%ebx),%ymm3,%ymm4 - libdis_test+0x1ba0: c4 e2 55 39 72 42 vpminsd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1ba6: c5 f1 ea d0 vpminsw %xmm0,%xmm1,%xmm2 - libdis_test+0x1baa: c5 e1 ea 20 vpminsw (%eax),%xmm3,%xmm4 - libdis_test+0x1bae: c5 d1 ea 71 42 vpminsw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1bb3: c5 f5 ea d0 vpminsw %ymm0,%ymm1,%ymm2 - libdis_test+0x1bb7: c5 e5 ea 23 vpminsw (%ebx),%ymm3,%ymm4 - libdis_test+0x1bbb: c5 d5 ea 72 42 vpminsw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1bc0: c5 f1 da d0 vpminub %xmm0,%xmm1,%xmm2 - libdis_test+0x1bc4: c5 e1 da 20 vpminub (%eax),%xmm3,%xmm4 - libdis_test+0x1bc8: c5 d1 da 71 42 vpminub 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1bcd: c5 f5 da d0 vpminub %ymm0,%ymm1,%ymm2 - libdis_test+0x1bd1: c5 e5 da 23 vpminub (%ebx),%ymm3,%ymm4 - libdis_test+0x1bd5: c5 d5 da 72 42 vpminub 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1bda: c4 e2 71 3b d0 vpminud %xmm0,%xmm1,%xmm2 - libdis_test+0x1bdf: c4 e2 61 3b 20 vpminud (%eax),%xmm3,%xmm4 - libdis_test+0x1be4: c4 e2 51 3b 71 42 vpminud 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1bea: c4 e2 75 3b d0 vpminud %ymm0,%ymm1,%ymm2 - libdis_test+0x1bef: c4 e2 65 3b 23 vpminud (%ebx),%ymm3,%ymm4 - libdis_test+0x1bf4: c4 e2 55 3b 72 42 vpminud 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1bfa: c4 e2 71 3a d0 vpminuw %xmm0,%xmm1,%xmm2 - libdis_test+0x1bff: c4 e2 61 3a 20 vpminuw (%eax),%xmm3,%xmm4 - libdis_test+0x1c04: c4 e2 51 3a 71 42 vpminuw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1c0a: c4 e2 75 3a d0 vpminuw %ymm0,%ymm1,%ymm2 - libdis_test+0x1c0f: c4 e2 65 3a 23 vpminuw (%ebx),%ymm3,%ymm4 - libdis_test+0x1c14: c4 e2 55 3a 72 42 vpminuw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1c1a: c5 f9 d7 c0 vpmovmskb %xmm0,%eax - libdis_test+0x1c1e: c5 fd d7 d9 vpmovmskb %ymm1,%ebx - libdis_test+0x1c22: c4 e2 79 21 c8 vpmovsxbd %xmm0,%xmm1 - libdis_test+0x1c27: c4 e2 79 21 1e vpmovsxbd (%esi),%xmm3 - libdis_test+0x1c2c: c4 e2 79 21 5f 42 vpmovsxbd 0x42(%edi),%xmm3 - libdis_test+0x1c32: c4 e2 7d 21 f7 vpmovsxbd %ymm7,%ymm6 - libdis_test+0x1c37: c4 e2 7d 21 65 00 vpmovsxbd 0x0(%ebp),%ymm4 - libdis_test+0x1c3d: c4 e2 7d 21 64 24 vpmovsxbd 0x42(%esp),%ymm4 + libdis_test+0x1a61: c5 f9 c4 c8 20 vpinsrw $0x20,%eax,%xmm0,%xmm1 + libdis_test+0x1a66: c5 e9 c4 1b 20 vpinsrw $0x20,(%ebx),%xmm2,%xmm3 + libdis_test+0x1a6b: c5 e9 c4 5b 10 20 vpinsrw $0x20,0x10(%ebx),%xmm2,%xmm3 + libdis_test+0x1a71: c4 e2 71 04 d0 vpmaddubsw %xmm0,%xmm1,%xmm2 + libdis_test+0x1a76: c4 e2 61 04 20 vpmaddubsw (%eax),%xmm3,%xmm4 + libdis_test+0x1a7b: c4 e2 51 04 71 42 vpmaddubsw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1a81: c4 e2 75 04 d0 vpmaddubsw %ymm0,%ymm1,%ymm2 + libdis_test+0x1a86: c4 e2 65 04 23 vpmaddubsw (%ebx),%ymm3,%ymm4 + libdis_test+0x1a8b: c4 e2 55 04 72 42 vpmaddubsw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1a91: c5 f1 f5 d0 vpmaddwd %xmm0,%xmm1,%xmm2 + libdis_test+0x1a95: c5 e1 f5 20 vpmaddwd (%eax),%xmm3,%xmm4 + libdis_test+0x1a99: c5 d1 f5 71 42 vpmaddwd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1a9e: c5 f5 f5 d0 vpmaddwd %ymm0,%ymm1,%ymm2 + libdis_test+0x1aa2: c5 e5 f5 23 vpmaddwd (%ebx),%ymm3,%ymm4 + libdis_test+0x1aa6: c5 d5 f5 72 42 vpmaddwd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1aab: c4 e2 71 3c d0 vpmaxsb %xmm0,%xmm1,%xmm2 + libdis_test+0x1ab0: c4 e2 61 3c 20 vpmaxsb (%eax),%xmm3,%xmm4 + libdis_test+0x1ab5: c4 e2 51 3c 71 42 vpmaxsb 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1abb: c4 e2 75 3c d0 vpmaxsb %ymm0,%ymm1,%ymm2 + libdis_test+0x1ac0: c4 e2 65 3c 23 vpmaxsb (%ebx),%ymm3,%ymm4 + libdis_test+0x1ac5: c4 e2 55 3c 72 42 vpmaxsb 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1acb: c4 e2 71 3d d0 vpmaxsd %xmm0,%xmm1,%xmm2 + libdis_test+0x1ad0: c4 e2 61 3d 20 vpmaxsd (%eax),%xmm3,%xmm4 + libdis_test+0x1ad5: c4 e2 51 3d 71 42 vpmaxsd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1adb: c4 e2 75 3d d0 vpmaxsd %ymm0,%ymm1,%ymm2 + libdis_test+0x1ae0: c4 e2 65 3d 23 vpmaxsd (%ebx),%ymm3,%ymm4 + libdis_test+0x1ae5: c4 e2 55 3d 72 42 vpmaxsd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1aeb: c5 f1 ee d0 vpmaxsw %xmm0,%xmm1,%xmm2 + libdis_test+0x1aef: c5 e1 ee 20 vpmaxsw (%eax),%xmm3,%xmm4 + libdis_test+0x1af3: c5 d1 ee 71 42 vpmaxsw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1af8: c5 f5 ee d0 vpmaxsw %ymm0,%ymm1,%ymm2 + libdis_test+0x1afc: c5 e5 ee 23 vpmaxsw (%ebx),%ymm3,%ymm4 + libdis_test+0x1b00: c5 d5 ee 72 42 vpmaxsw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1b05: c5 f1 de d0 vpmaxub %xmm0,%xmm1,%xmm2 + libdis_test+0x1b09: c5 e1 de 20 vpmaxub (%eax),%xmm3,%xmm4 + libdis_test+0x1b0d: c5 d1 de 71 42 vpmaxub 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1b12: c5 f5 de d0 vpmaxub %ymm0,%ymm1,%ymm2 + libdis_test+0x1b16: c5 e5 de 23 vpmaxub (%ebx),%ymm3,%ymm4 + libdis_test+0x1b1a: c5 d5 de 72 42 vpmaxub 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1b1f: c4 e2 71 3f d0 vpmaxud %xmm0,%xmm1,%xmm2 + libdis_test+0x1b24: c4 e2 61 3f 20 vpmaxud (%eax),%xmm3,%xmm4 + libdis_test+0x1b29: c4 e2 51 3f 71 42 vpmaxud 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1b2f: c4 e2 75 3f d0 vpmaxud %ymm0,%ymm1,%ymm2 + libdis_test+0x1b34: c4 e2 65 3f 23 vpmaxud (%ebx),%ymm3,%ymm4 + libdis_test+0x1b39: c4 e2 55 3f 72 42 vpmaxud 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1b3f: c4 e2 71 3e d0 vpmaxuw %xmm0,%xmm1,%xmm2 + libdis_test+0x1b44: c4 e2 61 3e 20 vpmaxuw (%eax),%xmm3,%xmm4 + libdis_test+0x1b49: c4 e2 51 3e 71 42 vpmaxuw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1b4f: c4 e2 75 3e d0 vpmaxuw %ymm0,%ymm1,%ymm2 + libdis_test+0x1b54: c4 e2 65 3e 23 vpmaxuw (%ebx),%ymm3,%ymm4 + libdis_test+0x1b59: c4 e2 55 3e 72 42 vpmaxuw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1b5f: c4 e2 71 38 d0 vpminsb %xmm0,%xmm1,%xmm2 + libdis_test+0x1b64: c4 e2 61 38 20 vpminsb (%eax),%xmm3,%xmm4 + libdis_test+0x1b69: c4 e2 51 38 71 42 vpminsb 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1b6f: c4 e2 75 38 d0 vpminsb %ymm0,%ymm1,%ymm2 + libdis_test+0x1b74: c4 e2 65 38 23 vpminsb (%ebx),%ymm3,%ymm4 + libdis_test+0x1b79: c4 e2 55 38 72 42 vpminsb 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1b7f: c4 e2 71 39 d0 vpminsd %xmm0,%xmm1,%xmm2 + libdis_test+0x1b84: c4 e2 61 39 20 vpminsd (%eax),%xmm3,%xmm4 + libdis_test+0x1b89: c4 e2 51 39 71 42 vpminsd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1b8f: c4 e2 75 39 d0 vpminsd %ymm0,%ymm1,%ymm2 + libdis_test+0x1b94: c4 e2 65 39 23 vpminsd (%ebx),%ymm3,%ymm4 + libdis_test+0x1b99: c4 e2 55 39 72 42 vpminsd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1b9f: c5 f1 ea d0 vpminsw %xmm0,%xmm1,%xmm2 + libdis_test+0x1ba3: c5 e1 ea 20 vpminsw (%eax),%xmm3,%xmm4 + libdis_test+0x1ba7: c5 d1 ea 71 42 vpminsw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1bac: c5 f5 ea d0 vpminsw %ymm0,%ymm1,%ymm2 + libdis_test+0x1bb0: c5 e5 ea 23 vpminsw (%ebx),%ymm3,%ymm4 + libdis_test+0x1bb4: c5 d5 ea 72 42 vpminsw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1bb9: c5 f1 da d0 vpminub %xmm0,%xmm1,%xmm2 + libdis_test+0x1bbd: c5 e1 da 20 vpminub (%eax),%xmm3,%xmm4 + libdis_test+0x1bc1: c5 d1 da 71 42 vpminub 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1bc6: c5 f5 da d0 vpminub %ymm0,%ymm1,%ymm2 + libdis_test+0x1bca: c5 e5 da 23 vpminub (%ebx),%ymm3,%ymm4 + libdis_test+0x1bce: c5 d5 da 72 42 vpminub 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1bd3: c4 e2 71 3b d0 vpminud %xmm0,%xmm1,%xmm2 + libdis_test+0x1bd8: c4 e2 61 3b 20 vpminud (%eax),%xmm3,%xmm4 + libdis_test+0x1bdd: c4 e2 51 3b 71 42 vpminud 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1be3: c4 e2 75 3b d0 vpminud %ymm0,%ymm1,%ymm2 + libdis_test+0x1be8: c4 e2 65 3b 23 vpminud (%ebx),%ymm3,%ymm4 + libdis_test+0x1bed: c4 e2 55 3b 72 42 vpminud 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1bf3: c4 e2 71 3a d0 vpminuw %xmm0,%xmm1,%xmm2 + libdis_test+0x1bf8: c4 e2 61 3a 20 vpminuw (%eax),%xmm3,%xmm4 + libdis_test+0x1bfd: c4 e2 51 3a 71 42 vpminuw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1c03: c4 e2 75 3a d0 vpminuw %ymm0,%ymm1,%ymm2 + libdis_test+0x1c08: c4 e2 65 3a 23 vpminuw (%ebx),%ymm3,%ymm4 + libdis_test+0x1c0d: c4 e2 55 3a 72 42 vpminuw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1c13: c5 f9 d7 c0 vpmovmskb %xmm0,%eax + libdis_test+0x1c17: c5 fd d7 d9 vpmovmskb %ymm1,%ebx + libdis_test+0x1c1b: c4 e2 79 21 c8 vpmovsxbd %xmm0,%xmm1 + libdis_test+0x1c20: c4 e2 79 21 1e vpmovsxbd (%esi),%xmm3 + libdis_test+0x1c25: c4 e2 79 21 5f 42 vpmovsxbd 0x42(%edi),%xmm3 + libdis_test+0x1c2b: c4 e2 7d 21 f7 vpmovsxbd %ymm7,%ymm6 + libdis_test+0x1c30: c4 e2 7d 21 65 00 vpmovsxbd 0x0(%ebp),%ymm4 + libdis_test+0x1c36: c4 e2 7d 21 64 24 vpmovsxbd 0x42(%esp),%ymm4 42 - libdis_test+0x1c44: c4 e2 79 22 c8 vpmovsxbq %xmm0,%xmm1 - libdis_test+0x1c49: c4 e2 79 22 1e vpmovsxbq (%esi),%xmm3 - libdis_test+0x1c4e: c4 e2 79 22 5f 42 vpmovsxbq 0x42(%edi),%xmm3 - libdis_test+0x1c54: c4 e2 7d 22 f7 vpmovsxbq %ymm7,%ymm6 - libdis_test+0x1c59: c4 e2 7d 22 65 00 vpmovsxbq 0x0(%ebp),%ymm4 - libdis_test+0x1c5f: c4 e2 7d 22 64 24 vpmovsxbq 0x42(%esp),%ymm4 + libdis_test+0x1c3d: c4 e2 79 22 c8 vpmovsxbq %xmm0,%xmm1 + libdis_test+0x1c42: c4 e2 79 22 1e vpmovsxbq (%esi),%xmm3 + libdis_test+0x1c47: c4 e2 79 22 5f 42 vpmovsxbq 0x42(%edi),%xmm3 + libdis_test+0x1c4d: c4 e2 7d 22 f7 vpmovsxbq %ymm7,%ymm6 + libdis_test+0x1c52: c4 e2 7d 22 65 00 vpmovsxbq 0x0(%ebp),%ymm4 + libdis_test+0x1c58: c4 e2 7d 22 64 24 vpmovsxbq 0x42(%esp),%ymm4 42 - libdis_test+0x1c66: c4 e2 79 20 c8 vpmovsxbw %xmm0,%xmm1 - libdis_test+0x1c6b: c4 e2 79 20 1e vpmovsxbw (%esi),%xmm3 - libdis_test+0x1c70: c4 e2 79 20 5f 42 vpmovsxbw 0x42(%edi),%xmm3 - libdis_test+0x1c76: c4 e2 7d 20 f7 vpmovsxbw %ymm7,%ymm6 - libdis_test+0x1c7b: c4 e2 7d 20 65 00 vpmovsxbw 0x0(%ebp),%ymm4 - libdis_test+0x1c81: c4 e2 7d 20 64 24 vpmovsxbw 0x42(%esp),%ymm4 + libdis_test+0x1c5f: c4 e2 79 20 c8 vpmovsxbw %xmm0,%xmm1 + libdis_test+0x1c64: c4 e2 79 20 1e vpmovsxbw (%esi),%xmm3 + libdis_test+0x1c69: c4 e2 79 20 5f 42 vpmovsxbw 0x42(%edi),%xmm3 + libdis_test+0x1c6f: c4 e2 7d 20 f7 vpmovsxbw %ymm7,%ymm6 + libdis_test+0x1c74: c4 e2 7d 20 65 00 vpmovsxbw 0x0(%ebp),%ymm4 + libdis_test+0x1c7a: c4 e2 7d 20 64 24 vpmovsxbw 0x42(%esp),%ymm4 42 - libdis_test+0x1c88: c4 e2 79 25 c8 vpmovsxdq %xmm0,%xmm1 - libdis_test+0x1c8d: c4 e2 79 25 1e vpmovsxdq (%esi),%xmm3 - libdis_test+0x1c92: c4 e2 79 25 5f 42 vpmovsxdq 0x42(%edi),%xmm3 - libdis_test+0x1c98: c4 e2 7d 25 f7 vpmovsxdq %ymm7,%ymm6 - libdis_test+0x1c9d: c4 e2 7d 25 65 00 vpmovsxdq 0x0(%ebp),%ymm4 - libdis_test+0x1ca3: c4 e2 7d 25 64 24 vpmovsxdq 0x42(%esp),%ymm4 + libdis_test+0x1c81: c4 e2 79 25 c8 vpmovsxdq %xmm0,%xmm1 + libdis_test+0x1c86: c4 e2 79 25 1e vpmovsxdq (%esi),%xmm3 + libdis_test+0x1c8b: c4 e2 79 25 5f 42 vpmovsxdq 0x42(%edi),%xmm3 + libdis_test+0x1c91: c4 e2 7d 25 f7 vpmovsxdq %ymm7,%ymm6 + libdis_test+0x1c96: c4 e2 7d 25 65 00 vpmovsxdq 0x0(%ebp),%ymm4 + libdis_test+0x1c9c: c4 e2 7d 25 64 24 vpmovsxdq 0x42(%esp),%ymm4 42 - libdis_test+0x1caa: c4 e2 79 23 c8 vpmovsxwd %xmm0,%xmm1 - libdis_test+0x1caf: c4 e2 79 23 1e vpmovsxwd (%esi),%xmm3 - libdis_test+0x1cb4: c4 e2 79 23 5f 42 vpmovsxwd 0x42(%edi),%xmm3 - libdis_test+0x1cba: c4 e2 7d 23 f7 vpmovsxwd %ymm7,%ymm6 - libdis_test+0x1cbf: c4 e2 7d 23 65 00 vpmovsxwd 0x0(%ebp),%ymm4 - libdis_test+0x1cc5: c4 e2 7d 23 64 24 vpmovsxwd 0x42(%esp),%ymm4 + libdis_test+0x1ca3: c4 e2 79 23 c8 vpmovsxwd %xmm0,%xmm1 + libdis_test+0x1ca8: c4 e2 79 23 1e vpmovsxwd (%esi),%xmm3 + libdis_test+0x1cad: c4 e2 79 23 5f 42 vpmovsxwd 0x42(%edi),%xmm3 + libdis_test+0x1cb3: c4 e2 7d 23 f7 vpmovsxwd %ymm7,%ymm6 + libdis_test+0x1cb8: c4 e2 7d 23 65 00 vpmovsxwd 0x0(%ebp),%ymm4 + libdis_test+0x1cbe: c4 e2 7d 23 64 24 vpmovsxwd 0x42(%esp),%ymm4 42 - libdis_test+0x1ccc: c4 e2 79 24 c8 vpmovsxwq %xmm0,%xmm1 - libdis_test+0x1cd1: c4 e2 79 24 1e vpmovsxwq (%esi),%xmm3 - libdis_test+0x1cd6: c4 e2 79 24 5f 42 vpmovsxwq 0x42(%edi),%xmm3 - libdis_test+0x1cdc: c4 e2 7d 24 f7 vpmovsxwq %ymm7,%ymm6 - libdis_test+0x1ce1: c4 e2 7d 24 65 00 vpmovsxwq 0x0(%ebp),%ymm4 - libdis_test+0x1ce7: c4 e2 7d 24 64 24 vpmovsxwq 0x42(%esp),%ymm4 + libdis_test+0x1cc5: c4 e2 79 24 c8 vpmovsxwq %xmm0,%xmm1 + libdis_test+0x1cca: c4 e2 79 24 1e vpmovsxwq (%esi),%xmm3 + libdis_test+0x1ccf: c4 e2 79 24 5f 42 vpmovsxwq 0x42(%edi),%xmm3 + libdis_test+0x1cd5: c4 e2 7d 24 f7 vpmovsxwq %ymm7,%ymm6 + libdis_test+0x1cda: c4 e2 7d 24 65 00 vpmovsxwq 0x0(%ebp),%ymm4 + libdis_test+0x1ce0: c4 e2 7d 24 64 24 vpmovsxwq 0x42(%esp),%ymm4 42 - libdis_test+0x1cee: c4 e2 79 31 c8 vpmovzxbd %xmm0,%xmm1 - libdis_test+0x1cf3: c4 e2 79 31 1e vpmovzxbd (%esi),%xmm3 - libdis_test+0x1cf8: c4 e2 79 31 5f 42 vpmovzxbd 0x42(%edi),%xmm3 - libdis_test+0x1cfe: c4 e2 7d 31 f7 vpmovzxbd %ymm7,%ymm6 - libdis_test+0x1d03: c4 e2 7d 31 65 00 vpmovzxbd 0x0(%ebp),%ymm4 - libdis_test+0x1d09: c4 e2 7d 31 64 24 vpmovzxbd 0x42(%esp),%ymm4 + libdis_test+0x1ce7: c4 e2 79 31 c8 vpmovzxbd %xmm0,%xmm1 + libdis_test+0x1cec: c4 e2 79 31 1e vpmovzxbd (%esi),%xmm3 + libdis_test+0x1cf1: c4 e2 79 31 5f 42 vpmovzxbd 0x42(%edi),%xmm3 + libdis_test+0x1cf7: c4 e2 7d 31 f7 vpmovzxbd %ymm7,%ymm6 + libdis_test+0x1cfc: c4 e2 7d 31 65 00 vpmovzxbd 0x0(%ebp),%ymm4 + libdis_test+0x1d02: c4 e2 7d 31 64 24 vpmovzxbd 0x42(%esp),%ymm4 42 - libdis_test+0x1d10: c4 e2 79 32 c8 vpmovzxbq %xmm0,%xmm1 - libdis_test+0x1d15: c4 e2 79 32 1e vpmovzxbq (%esi),%xmm3 - libdis_test+0x1d1a: c4 e2 79 32 5f 42 vpmovzxbq 0x42(%edi),%xmm3 - libdis_test+0x1d20: c4 e2 7d 32 f7 vpmovzxbq %ymm7,%ymm6 - libdis_test+0x1d25: c4 e2 7d 32 65 00 vpmovzxbq 0x0(%ebp),%ymm4 - libdis_test+0x1d2b: c4 e2 7d 32 64 24 vpmovzxbq 0x42(%esp),%ymm4 + libdis_test+0x1d09: c4 e2 79 32 c8 vpmovzxbq %xmm0,%xmm1 + libdis_test+0x1d0e: c4 e2 79 32 1e vpmovzxbq (%esi),%xmm3 + libdis_test+0x1d13: c4 e2 79 32 5f 42 vpmovzxbq 0x42(%edi),%xmm3 + libdis_test+0x1d19: c4 e2 7d 32 f7 vpmovzxbq %ymm7,%ymm6 + libdis_test+0x1d1e: c4 e2 7d 32 65 00 vpmovzxbq 0x0(%ebp),%ymm4 + libdis_test+0x1d24: c4 e2 7d 32 64 24 vpmovzxbq 0x42(%esp),%ymm4 42 - libdis_test+0x1d32: c4 e2 79 30 c8 vpmovzxbw %xmm0,%xmm1 - libdis_test+0x1d37: c4 e2 79 30 1e vpmovzxbw (%esi),%xmm3 - libdis_test+0x1d3c: c4 e2 79 30 5f 42 vpmovzxbw 0x42(%edi),%xmm3 - libdis_test+0x1d42: c4 e2 7d 30 f7 vpmovzxbw %ymm7,%ymm6 - libdis_test+0x1d47: c4 e2 7d 30 65 00 vpmovzxbw 0x0(%ebp),%ymm4 - libdis_test+0x1d4d: c4 e2 7d 30 64 24 vpmovzxbw 0x42(%esp),%ymm4 + libdis_test+0x1d2b: c4 e2 79 30 c8 vpmovzxbw %xmm0,%xmm1 + libdis_test+0x1d30: c4 e2 79 30 1e vpmovzxbw (%esi),%xmm3 + libdis_test+0x1d35: c4 e2 79 30 5f 42 vpmovzxbw 0x42(%edi),%xmm3 + libdis_test+0x1d3b: c4 e2 7d 30 f7 vpmovzxbw %ymm7,%ymm6 + libdis_test+0x1d40: c4 e2 7d 30 65 00 vpmovzxbw 0x0(%ebp),%ymm4 + libdis_test+0x1d46: c4 e2 7d 30 64 24 vpmovzxbw 0x42(%esp),%ymm4 42 - libdis_test+0x1d54: c4 e2 79 35 c8 vpmovzxdq %xmm0,%xmm1 - libdis_test+0x1d59: c4 e2 79 35 1e vpmovzxdq (%esi),%xmm3 - libdis_test+0x1d5e: c4 e2 79 35 5f 42 vpmovzxdq 0x42(%edi),%xmm3 - libdis_test+0x1d64: c4 e2 7d 35 f7 vpmovzxdq %ymm7,%ymm6 - libdis_test+0x1d69: c4 e2 7d 35 65 00 vpmovzxdq 0x0(%ebp),%ymm4 - libdis_test+0x1d6f: c4 e2 7d 35 64 24 vpmovzxdq 0x42(%esp),%ymm4 + libdis_test+0x1d4d: c4 e2 79 35 c8 vpmovzxdq %xmm0,%xmm1 + libdis_test+0x1d52: c4 e2 79 35 1e vpmovzxdq (%esi),%xmm3 + libdis_test+0x1d57: c4 e2 79 35 5f 42 vpmovzxdq 0x42(%edi),%xmm3 + libdis_test+0x1d5d: c4 e2 7d 35 f7 vpmovzxdq %ymm7,%ymm6 + libdis_test+0x1d62: c4 e2 7d 35 65 00 vpmovzxdq 0x0(%ebp),%ymm4 + libdis_test+0x1d68: c4 e2 7d 35 64 24 vpmovzxdq 0x42(%esp),%ymm4 42 - libdis_test+0x1d76: c4 e2 79 33 c8 vpmovzxwd %xmm0,%xmm1 - libdis_test+0x1d7b: c4 e2 79 33 1e vpmovzxwd (%esi),%xmm3 - libdis_test+0x1d80: c4 e2 79 33 5f 42 vpmovzxwd 0x42(%edi),%xmm3 - libdis_test+0x1d86: c4 e2 7d 33 f7 vpmovzxwd %ymm7,%ymm6 - libdis_test+0x1d8b: c4 e2 7d 33 65 00 vpmovzxwd 0x0(%ebp),%ymm4 - libdis_test+0x1d91: c4 e2 7d 33 64 24 vpmovzxwd 0x42(%esp),%ymm4 + libdis_test+0x1d6f: c4 e2 79 33 c8 vpmovzxwd %xmm0,%xmm1 + libdis_test+0x1d74: c4 e2 79 33 1e vpmovzxwd (%esi),%xmm3 + libdis_test+0x1d79: c4 e2 79 33 5f 42 vpmovzxwd 0x42(%edi),%xmm3 + libdis_test+0x1d7f: c4 e2 7d 33 f7 vpmovzxwd %ymm7,%ymm6 + libdis_test+0x1d84: c4 e2 7d 33 65 00 vpmovzxwd 0x0(%ebp),%ymm4 + libdis_test+0x1d8a: c4 e2 7d 33 64 24 vpmovzxwd 0x42(%esp),%ymm4 42 - libdis_test+0x1d98: c4 e2 79 34 c8 vpmovzxwq %xmm0,%xmm1 - libdis_test+0x1d9d: c4 e2 79 34 1e vpmovzxwq (%esi),%xmm3 - libdis_test+0x1da2: c4 e2 79 34 5f 42 vpmovzxwq 0x42(%edi),%xmm3 - libdis_test+0x1da8: c4 e2 7d 34 f7 vpmovzxwq %ymm7,%ymm6 - libdis_test+0x1dad: c4 e2 7d 34 65 00 vpmovzxwq 0x0(%ebp),%ymm4 - libdis_test+0x1db3: c4 e2 7d 34 64 24 vpmovzxwq 0x42(%esp),%ymm4 + libdis_test+0x1d91: c4 e2 79 34 c8 vpmovzxwq %xmm0,%xmm1 + libdis_test+0x1d96: c4 e2 79 34 1e vpmovzxwq (%esi),%xmm3 + libdis_test+0x1d9b: c4 e2 79 34 5f 42 vpmovzxwq 0x42(%edi),%xmm3 + libdis_test+0x1da1: c4 e2 7d 34 f7 vpmovzxwq %ymm7,%ymm6 + libdis_test+0x1da6: c4 e2 7d 34 65 00 vpmovzxwq 0x0(%ebp),%ymm4 + libdis_test+0x1dac: c4 e2 7d 34 64 24 vpmovzxwq 0x42(%esp),%ymm4 42 - libdis_test+0x1dba: c4 e2 71 28 d0 vpmuldq %xmm0,%xmm1,%xmm2 - libdis_test+0x1dbf: c4 e2 61 28 20 vpmuldq (%eax),%xmm3,%xmm4 - libdis_test+0x1dc4: c4 e2 51 28 71 42 vpmuldq 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1dca: c4 e2 75 28 d0 vpmuldq %ymm0,%ymm1,%ymm2 - libdis_test+0x1dcf: c4 e2 65 28 23 vpmuldq (%ebx),%ymm3,%ymm4 - libdis_test+0x1dd4: c4 e2 55 28 72 42 vpmuldq 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1dda: c4 e2 71 0b d0 vpmulhrsw %xmm0,%xmm1,%xmm2 - libdis_test+0x1ddf: c4 e2 61 0b 20 vpmulhrsw (%eax),%xmm3,%xmm4 - libdis_test+0x1de4: c4 e2 51 0b 71 42 vpmulhrsw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1dea: c4 e2 75 0b d0 vpmulhrsw %ymm0,%ymm1,%ymm2 - libdis_test+0x1def: c4 e2 65 0b 23 vpmulhrsw (%ebx),%ymm3,%ymm4 - libdis_test+0x1df4: c4 e2 55 0b 72 42 vpmulhrsw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1dfa: c5 f1 e4 d0 vpmulhuw %xmm0,%xmm1,%xmm2 - libdis_test+0x1dfe: c5 e1 e4 20 vpmulhuw (%eax),%xmm3,%xmm4 - libdis_test+0x1e02: c5 d1 e4 71 42 vpmulhuw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1e07: c5 f5 e4 d0 vpmulhuw %ymm0,%ymm1,%ymm2 - libdis_test+0x1e0b: c5 e5 e4 23 vpmulhuw (%ebx),%ymm3,%ymm4 - libdis_test+0x1e0f: c5 d5 e4 72 42 vpmulhuw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1e14: c5 f1 e5 d0 vpmulhw %xmm0,%xmm1,%xmm2 - libdis_test+0x1e18: c5 e1 e5 20 vpmulhw (%eax),%xmm3,%xmm4 - libdis_test+0x1e1c: c5 d1 e5 71 42 vpmulhw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1e21: c5 f5 e5 d0 vpmulhw %ymm0,%ymm1,%ymm2 - libdis_test+0x1e25: c5 e5 e5 23 vpmulhw (%ebx),%ymm3,%ymm4 - libdis_test+0x1e29: c5 d5 e5 72 42 vpmulhw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1e2e: c4 e2 71 40 d0 vpmulld %xmm0,%xmm1,%xmm2 - libdis_test+0x1e33: c4 e2 61 40 20 vpmulld (%eax),%xmm3,%xmm4 - libdis_test+0x1e38: c4 e2 51 40 71 42 vpmulld 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1e3e: c4 e2 75 40 d0 vpmulld %ymm0,%ymm1,%ymm2 - libdis_test+0x1e43: c4 e2 65 40 23 vpmulld (%ebx),%ymm3,%ymm4 - libdis_test+0x1e48: c4 e2 55 40 72 42 vpmulld 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1e4e: c5 f1 d5 d0 vpmullw %xmm0,%xmm1,%xmm2 - libdis_test+0x1e52: c5 e1 d5 20 vpmullw (%eax),%xmm3,%xmm4 - libdis_test+0x1e56: c5 d1 d5 71 42 vpmullw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1e5b: c5 f5 d5 d0 vpmullw %ymm0,%ymm1,%ymm2 - libdis_test+0x1e5f: c5 e5 d5 23 vpmullw (%ebx),%ymm3,%ymm4 - libdis_test+0x1e63: c5 d5 d5 72 42 vpmullw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1e68: c5 f1 f4 d0 vpmuludq %xmm0,%xmm1,%xmm2 - libdis_test+0x1e6c: c5 e1 f4 20 vpmuludq (%eax),%xmm3,%xmm4 - libdis_test+0x1e70: c5 d1 f4 71 42 vpmuludq 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1e75: c5 f5 f4 d0 vpmuludq %ymm0,%ymm1,%ymm2 - libdis_test+0x1e79: c5 e5 f4 23 vpmuludq (%ebx),%ymm3,%ymm4 - libdis_test+0x1e7d: c5 d5 f4 72 42 vpmuludq 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1e82: c5 f1 eb d0 vpor %xmm0,%xmm1,%xmm2 - libdis_test+0x1e86: c5 e1 eb 20 vpor (%eax),%xmm3,%xmm4 - libdis_test+0x1e8a: c5 d1 eb 71 42 vpor 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1e8f: c5 f5 eb d0 vpor %ymm0,%ymm1,%ymm2 - libdis_test+0x1e93: c5 e5 eb 23 vpor (%ebx),%ymm3,%ymm4 - libdis_test+0x1e97: c5 d5 eb 72 42 vpor 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1e9c: c5 f1 f6 d0 vpsadbw %xmm0,%xmm1,%xmm2 - libdis_test+0x1ea0: c5 e1 f6 20 vpsadbw (%eax),%xmm3,%xmm4 - libdis_test+0x1ea4: c5 d1 f6 71 42 vpsadbw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1ea9: c5 f5 f6 d0 vpsadbw %ymm0,%ymm1,%ymm2 - libdis_test+0x1ead: c5 e5 f6 23 vpsadbw (%ebx),%ymm3,%ymm4 - libdis_test+0x1eb1: c5 d5 f6 72 42 vpsadbw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1eb6: c4 e2 71 00 d0 vpshufb %xmm0,%xmm1,%xmm2 - libdis_test+0x1ebb: c4 e2 61 00 20 vpshufb (%eax),%xmm3,%xmm4 - libdis_test+0x1ec0: c4 e2 51 00 71 42 vpshufb 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1ec6: c4 e2 75 00 d0 vpshufb %ymm0,%ymm1,%ymm2 - libdis_test+0x1ecb: c4 e2 65 00 23 vpshufb (%ebx),%ymm3,%ymm4 - libdis_test+0x1ed0: c4 e2 55 00 72 42 vpshufb 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1ed6: c5 f9 70 c8 42 vpshufd $0x42,%xmm0,%xmm1 - libdis_test+0x1edb: c5 f9 70 1e 23 vpshufd $0x23,(%esi),%xmm3 - libdis_test+0x1ee0: c5 f9 70 5f 42 42 vpshufd $0x42,0x42(%edi),%xmm3 - libdis_test+0x1ee6: c5 fd 70 c8 42 vpshufd $0x42,%ymm0,%ymm1 - libdis_test+0x1eeb: c5 fd 70 1e 23 vpshufd $0x23,(%esi),%ymm3 - libdis_test+0x1ef0: c5 fd 70 5f 42 42 vpshufd $0x42,0x42(%edi),%ymm3 - libdis_test+0x1ef6: c5 fa 70 c8 42 vpshufhw $0x42,%xmm0,%xmm1 - libdis_test+0x1efb: c5 fa 70 1e 23 vpshufhw $0x23,(%esi),%xmm3 - libdis_test+0x1f00: c5 fa 70 5f 42 42 vpshufhw $0x42,0x42(%edi),%xmm3 - libdis_test+0x1f06: c5 fe 70 c8 42 vpshufhw $0x42,%ymm0,%ymm1 - libdis_test+0x1f0b: c5 fe 70 1e 23 vpshufhw $0x23,(%esi),%ymm3 - libdis_test+0x1f10: c5 fe 70 5f 42 42 vpshufhw $0x42,0x42(%edi),%ymm3 - libdis_test+0x1f16: c5 fb 70 c8 42 vpshuflw $0x42,%xmm0,%xmm1 - libdis_test+0x1f1b: c5 fb 70 1e 23 vpshuflw $0x23,(%esi),%xmm3 - libdis_test+0x1f20: c5 fb 70 5f 42 42 vpshuflw $0x42,0x42(%edi),%xmm3 - libdis_test+0x1f26: c5 ff 70 c8 42 vpshuflw $0x42,%ymm0,%ymm1 - libdis_test+0x1f2b: c5 ff 70 1e 23 vpshuflw $0x23,(%esi),%ymm3 - libdis_test+0x1f30: c5 ff 70 5f 42 42 vpshuflw $0x42,0x42(%edi),%ymm3 - libdis_test+0x1f36: c4 e2 71 08 d0 vpsignb %xmm0,%xmm1,%xmm2 - libdis_test+0x1f3b: c4 e2 61 08 20 vpsignb (%eax),%xmm3,%xmm4 - libdis_test+0x1f40: c4 e2 51 08 71 42 vpsignb 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1f46: c4 e2 75 08 d0 vpsignb %ymm0,%ymm1,%ymm2 - libdis_test+0x1f4b: c4 e2 65 08 23 vpsignb (%ebx),%ymm3,%ymm4 - libdis_test+0x1f50: c4 e2 55 08 72 42 vpsignb 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1f56: c4 e2 71 0a d0 vpsignd %xmm0,%xmm1,%xmm2 - libdis_test+0x1f5b: c4 e2 61 0a 20 vpsignd (%eax),%xmm3,%xmm4 - libdis_test+0x1f60: c4 e2 51 0a 71 42 vpsignd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1f66: c4 e2 75 0a d0 vpsignd %ymm0,%ymm1,%ymm2 - libdis_test+0x1f6b: c4 e2 65 0a 23 vpsignd (%ebx),%ymm3,%ymm4 - libdis_test+0x1f70: c4 e2 55 0a 72 42 vpsignd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1f76: c4 e2 71 09 d0 vpsignw %xmm0,%xmm1,%xmm2 - libdis_test+0x1f7b: c4 e2 61 09 20 vpsignw (%eax),%xmm3,%xmm4 - libdis_test+0x1f80: c4 e2 51 09 71 42 vpsignw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x1f86: c4 e2 75 09 d0 vpsignw %ymm0,%ymm1,%ymm2 - libdis_test+0x1f8b: c4 e2 65 09 23 vpsignw (%ebx),%ymm3,%ymm4 - libdis_test+0x1f90: c4 e2 55 09 72 42 vpsignw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x1f96: c5 f1 f2 d0 vpslld %xmm0,%xmm1,%xmm2 - libdis_test+0x1f9a: c5 e1 f2 20 vpslld (%eax),%xmm3,%xmm4 - libdis_test+0x1f9e: c5 d9 f2 6b 10 vpslld 0x10(%ebx),%xmm4,%xmm5 - libdis_test+0x1fa3: c5 c1 72 f6 04 vpslld $0x4,%xmm6,%xmm7 - libdis_test+0x1fa8: c5 f5 f2 d0 vpslld %ymm0,%ymm1,%ymm2 - libdis_test+0x1fac: c5 e5 f2 20 vpslld (%eax),%ymm3,%ymm4 - libdis_test+0x1fb0: c5 dd f2 6b 10 vpslld 0x10(%ebx),%ymm4,%ymm5 - libdis_test+0x1fb5: c5 c5 72 f6 04 vpslld $0x4,%ymm6,%ymm7 - libdis_test+0x1fba: c5 f1 73 f8 07 vpslldq $0x7,%xmm0,%xmm1 - libdis_test+0x1fbf: c5 f5 73 f8 07 vpslldq $0x7,%ymm0,%ymm1 - libdis_test+0x1fc4: c5 f1 f3 d0 vpsllq %xmm0,%xmm1,%xmm2 - libdis_test+0x1fc8: c5 e1 f3 20 vpsllq (%eax),%xmm3,%xmm4 - libdis_test+0x1fcc: c5 d9 f3 6b 10 vpsllq 0x10(%ebx),%xmm4,%xmm5 - libdis_test+0x1fd1: c5 c1 73 f6 04 vpsllq $0x4,%xmm6,%xmm7 - libdis_test+0x1fd6: c5 f5 f3 d0 vpsllq %ymm0,%ymm1,%ymm2 - libdis_test+0x1fda: c5 e5 f3 20 vpsllq (%eax),%ymm3,%ymm4 - libdis_test+0x1fde: c5 dd f3 6b 10 vpsllq 0x10(%ebx),%ymm4,%ymm5 - libdis_test+0x1fe3: c5 c5 73 f6 04 vpsllq $0x4,%ymm6,%ymm7 - libdis_test+0x1fe8: c5 f1 f1 d0 vpsllw %xmm0,%xmm1,%xmm2 - libdis_test+0x1fec: c5 e1 f1 20 vpsllw (%eax),%xmm3,%xmm4 - libdis_test+0x1ff0: c5 d9 f1 6b 10 vpsllw 0x10(%ebx),%xmm4,%xmm5 - libdis_test+0x1ff5: c5 c1 71 f6 04 vpsllw $0x4,%xmm6,%xmm7 - libdis_test+0x1ffa: c5 f5 f1 d0 vpsllw %ymm0,%ymm1,%ymm2 - libdis_test+0x1ffe: c5 e5 f1 20 vpsllw (%eax),%ymm3,%ymm4 - libdis_test+0x2002: c5 dd f1 6b 10 vpsllw 0x10(%ebx),%ymm4,%ymm5 - libdis_test+0x2007: c5 c5 71 f6 04 vpsllw $0x4,%ymm6,%ymm7 - libdis_test+0x200c: c5 f1 e2 d0 vpsrad %xmm0,%xmm1,%xmm2 - libdis_test+0x2010: c5 e1 e2 20 vpsrad (%eax),%xmm3,%xmm4 - libdis_test+0x2014: c5 d9 e2 6b 10 vpsrad 0x10(%ebx),%xmm4,%xmm5 - libdis_test+0x2019: c5 c1 72 e6 04 vpsrad $0x4,%xmm6,%xmm7 - libdis_test+0x201e: c5 f5 e2 d0 vpsrad %ymm0,%ymm1,%ymm2 - libdis_test+0x2022: c5 e5 e2 20 vpsrad (%eax),%ymm3,%ymm4 - libdis_test+0x2026: c5 dd e2 6b 10 vpsrad 0x10(%ebx),%ymm4,%ymm5 - libdis_test+0x202b: c5 c5 72 e6 04 vpsrad $0x4,%ymm6,%ymm7 - libdis_test+0x2030: c5 f1 e1 d0 vpsraw %xmm0,%xmm1,%xmm2 - libdis_test+0x2034: c5 e1 e1 20 vpsraw (%eax),%xmm3,%xmm4 - libdis_test+0x2038: c5 d9 e1 6b 10 vpsraw 0x10(%ebx),%xmm4,%xmm5 - libdis_test+0x203d: c5 c1 71 e6 04 vpsraw $0x4,%xmm6,%xmm7 - libdis_test+0x2042: c5 f5 e1 d0 vpsraw %ymm0,%ymm1,%ymm2 - libdis_test+0x2046: c5 e5 e1 20 vpsraw (%eax),%ymm3,%ymm4 - libdis_test+0x204a: c5 dd e1 6b 10 vpsraw 0x10(%ebx),%ymm4,%ymm5 - libdis_test+0x204f: c5 c5 71 e6 04 vpsraw $0x4,%ymm6,%ymm7 - libdis_test+0x2054: c5 f1 d2 d0 vpsrld %xmm0,%xmm1,%xmm2 - libdis_test+0x2058: c5 e1 d2 20 vpsrld (%eax),%xmm3,%xmm4 - libdis_test+0x205c: c5 d9 d2 6b 10 vpsrld 0x10(%ebx),%xmm4,%xmm5 - libdis_test+0x2061: c5 c1 72 d6 04 vpsrld $0x4,%xmm6,%xmm7 - libdis_test+0x2066: c5 f5 d2 d0 vpsrld %ymm0,%ymm1,%ymm2 - libdis_test+0x206a: c5 e5 d2 20 vpsrld (%eax),%ymm3,%ymm4 - libdis_test+0x206e: c5 dd d2 6b 10 vpsrld 0x10(%ebx),%ymm4,%ymm5 - libdis_test+0x2073: c5 c5 72 d6 04 vpsrld $0x4,%ymm6,%ymm7 - libdis_test+0x2078: c5 f1 73 d8 07 vpsrldq $0x7,%xmm0,%xmm1 - libdis_test+0x207d: c5 f5 73 d8 07 vpsrldq $0x7,%ymm0,%ymm1 - libdis_test+0x2082: c5 f1 d3 d0 vpsrlq %xmm0,%xmm1,%xmm2 - libdis_test+0x2086: c5 e1 d3 20 vpsrlq (%eax),%xmm3,%xmm4 - libdis_test+0x208a: c5 d9 d3 6b 10 vpsrlq 0x10(%ebx),%xmm4,%xmm5 - libdis_test+0x208f: c5 c1 73 d6 04 vpsrlq $0x4,%xmm6,%xmm7 - libdis_test+0x2094: c5 f5 d3 d0 vpsrlq %ymm0,%ymm1,%ymm2 - libdis_test+0x2098: c5 e5 d3 20 vpsrlq (%eax),%ymm3,%ymm4 - libdis_test+0x209c: c5 dd d3 6b 10 vpsrlq 0x10(%ebx),%ymm4,%ymm5 - libdis_test+0x20a1: c5 c5 73 d6 04 vpsrlq $0x4,%ymm6,%ymm7 - libdis_test+0x20a6: c5 f1 d1 d0 vpsrlw %xmm0,%xmm1,%xmm2 - libdis_test+0x20aa: c5 e1 d1 20 vpsrlw (%eax),%xmm3,%xmm4 - libdis_test+0x20ae: c5 d9 d1 6b 10 vpsrlw 0x10(%ebx),%xmm4,%xmm5 - libdis_test+0x20b3: c5 c1 71 d6 04 vpsrlw $0x4,%xmm6,%xmm7 - libdis_test+0x20b8: c5 f5 d1 d0 vpsrlw %ymm0,%ymm1,%ymm2 - libdis_test+0x20bc: c5 e5 d1 20 vpsrlw (%eax),%ymm3,%ymm4 - libdis_test+0x20c0: c5 dd d1 6b 10 vpsrlw 0x10(%ebx),%ymm4,%ymm5 - libdis_test+0x20c5: c5 c5 71 d6 04 vpsrlw $0x4,%ymm6,%ymm7 - libdis_test+0x20ca: c5 f1 f8 d0 vpsubb %xmm0,%xmm1,%xmm2 - libdis_test+0x20ce: c5 e1 f8 20 vpsubb (%eax),%xmm3,%xmm4 - libdis_test+0x20d2: c5 d1 f8 71 42 vpsubb 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x20d7: c5 f5 f8 d0 vpsubb %ymm0,%ymm1,%ymm2 - libdis_test+0x20db: c5 e5 f8 23 vpsubb (%ebx),%ymm3,%ymm4 - libdis_test+0x20df: c5 d5 f8 72 42 vpsubb 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x20e4: c5 f1 fa d0 vpsubd %xmm0,%xmm1,%xmm2 - libdis_test+0x20e8: c5 e1 fa 20 vpsubd (%eax),%xmm3,%xmm4 - libdis_test+0x20ec: c5 d1 fa 71 42 vpsubd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x20f1: c5 f5 fa d0 vpsubd %ymm0,%ymm1,%ymm2 - libdis_test+0x20f5: c5 e5 fa 23 vpsubd (%ebx),%ymm3,%ymm4 - libdis_test+0x20f9: c5 d5 fa 72 42 vpsubd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x20fe: c5 f1 fb d0 vpsubq %xmm0,%xmm1,%xmm2 - libdis_test+0x2102: c5 e1 fb 20 vpsubq (%eax),%xmm3,%xmm4 - libdis_test+0x2106: c5 d1 fb 71 42 vpsubq 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x210b: c5 f5 fb d0 vpsubq %ymm0,%ymm1,%ymm2 - libdis_test+0x210f: c5 e5 fb 23 vpsubq (%ebx),%ymm3,%ymm4 - libdis_test+0x2113: c5 d5 fb 72 42 vpsubq 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2118: c5 f1 e8 d0 vpsubsb %xmm0,%xmm1,%xmm2 - libdis_test+0x211c: c5 e1 e8 20 vpsubsb (%eax),%xmm3,%xmm4 - libdis_test+0x2120: c5 d1 e8 71 42 vpsubsb 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2125: c5 f5 e8 d0 vpsubsb %ymm0,%ymm1,%ymm2 - libdis_test+0x2129: c5 e5 e8 23 vpsubsb (%ebx),%ymm3,%ymm4 - libdis_test+0x212d: c5 d5 e8 72 42 vpsubsb 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2132: c5 f1 e9 d0 vpsubsw %xmm0,%xmm1,%xmm2 - libdis_test+0x2136: c5 e1 e9 20 vpsubsw (%eax),%xmm3,%xmm4 - libdis_test+0x213a: c5 d1 e9 71 42 vpsubsw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x213f: c5 f5 e9 d0 vpsubsw %ymm0,%ymm1,%ymm2 - libdis_test+0x2143: c5 e5 e9 23 vpsubsw (%ebx),%ymm3,%ymm4 - libdis_test+0x2147: c5 d5 e9 72 42 vpsubsw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x214c: c5 f1 d8 d0 vpsubusb %xmm0,%xmm1,%xmm2 - libdis_test+0x2150: c5 e1 d8 20 vpsubusb (%eax),%xmm3,%xmm4 - libdis_test+0x2154: c5 d1 d8 71 42 vpsubusb 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2159: c5 f5 d8 d0 vpsubusb %ymm0,%ymm1,%ymm2 - libdis_test+0x215d: c5 e5 d8 23 vpsubusb (%ebx),%ymm3,%ymm4 - libdis_test+0x2161: c5 d5 d8 72 42 vpsubusb 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2166: c5 f1 d9 d0 vpsubusw %xmm0,%xmm1,%xmm2 - libdis_test+0x216a: c5 e1 d9 20 vpsubusw (%eax),%xmm3,%xmm4 - libdis_test+0x216e: c5 d1 d9 71 42 vpsubusw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2173: c5 f5 d9 d0 vpsubusw %ymm0,%ymm1,%ymm2 - libdis_test+0x2177: c5 e5 d9 23 vpsubusw (%ebx),%ymm3,%ymm4 - libdis_test+0x217b: c5 d5 d9 72 42 vpsubusw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2180: c5 f1 f9 d0 vpsubw %xmm0,%xmm1,%xmm2 - libdis_test+0x2184: c5 e1 f9 20 vpsubw (%eax),%xmm3,%xmm4 - libdis_test+0x2188: c5 d1 f9 71 42 vpsubw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x218d: c5 f5 f9 d0 vpsubw %ymm0,%ymm1,%ymm2 - libdis_test+0x2191: c5 e5 f9 23 vpsubw (%ebx),%ymm3,%ymm4 - libdis_test+0x2195: c5 d5 f9 72 42 vpsubw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x219a: c4 e2 79 17 c8 vptest %xmm0,%xmm1 - libdis_test+0x219f: c4 e2 79 17 1e vptest (%esi),%xmm3 - libdis_test+0x21a4: c4 e2 79 17 5f 42 vptest 0x42(%edi),%xmm3 - libdis_test+0x21aa: c4 e2 7d 17 f7 vptest %ymm7,%ymm6 - libdis_test+0x21af: c4 e2 7d 17 65 00 vptest 0x0(%ebp),%ymm4 - libdis_test+0x21b5: c4 e2 7d 17 64 24 vptest 0x42(%esp),%ymm4 + libdis_test+0x1db3: c4 e2 71 28 d0 vpmuldq %xmm0,%xmm1,%xmm2 + libdis_test+0x1db8: c4 e2 61 28 20 vpmuldq (%eax),%xmm3,%xmm4 + libdis_test+0x1dbd: c4 e2 51 28 71 42 vpmuldq 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1dc3: c4 e2 75 28 d0 vpmuldq %ymm0,%ymm1,%ymm2 + libdis_test+0x1dc8: c4 e2 65 28 23 vpmuldq (%ebx),%ymm3,%ymm4 + libdis_test+0x1dcd: c4 e2 55 28 72 42 vpmuldq 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1dd3: c4 e2 71 0b d0 vpmulhrsw %xmm0,%xmm1,%xmm2 + libdis_test+0x1dd8: c4 e2 61 0b 20 vpmulhrsw (%eax),%xmm3,%xmm4 + libdis_test+0x1ddd: c4 e2 51 0b 71 42 vpmulhrsw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1de3: c4 e2 75 0b d0 vpmulhrsw %ymm0,%ymm1,%ymm2 + libdis_test+0x1de8: c4 e2 65 0b 23 vpmulhrsw (%ebx),%ymm3,%ymm4 + libdis_test+0x1ded: c4 e2 55 0b 72 42 vpmulhrsw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1df3: c5 f1 e4 d0 vpmulhuw %xmm0,%xmm1,%xmm2 + libdis_test+0x1df7: c5 e1 e4 20 vpmulhuw (%eax),%xmm3,%xmm4 + libdis_test+0x1dfb: c5 d1 e4 71 42 vpmulhuw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1e00: c5 f5 e4 d0 vpmulhuw %ymm0,%ymm1,%ymm2 + libdis_test+0x1e04: c5 e5 e4 23 vpmulhuw (%ebx),%ymm3,%ymm4 + libdis_test+0x1e08: c5 d5 e4 72 42 vpmulhuw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1e0d: c5 f1 e5 d0 vpmulhw %xmm0,%xmm1,%xmm2 + libdis_test+0x1e11: c5 e1 e5 20 vpmulhw (%eax),%xmm3,%xmm4 + libdis_test+0x1e15: c5 d1 e5 71 42 vpmulhw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1e1a: c5 f5 e5 d0 vpmulhw %ymm0,%ymm1,%ymm2 + libdis_test+0x1e1e: c5 e5 e5 23 vpmulhw (%ebx),%ymm3,%ymm4 + libdis_test+0x1e22: c5 d5 e5 72 42 vpmulhw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1e27: c4 e2 71 40 d0 vpmulld %xmm0,%xmm1,%xmm2 + libdis_test+0x1e2c: c4 e2 61 40 20 vpmulld (%eax),%xmm3,%xmm4 + libdis_test+0x1e31: c4 e2 51 40 71 42 vpmulld 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1e37: c4 e2 75 40 d0 vpmulld %ymm0,%ymm1,%ymm2 + libdis_test+0x1e3c: c4 e2 65 40 23 vpmulld (%ebx),%ymm3,%ymm4 + libdis_test+0x1e41: c4 e2 55 40 72 42 vpmulld 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1e47: c5 f1 d5 d0 vpmullw %xmm0,%xmm1,%xmm2 + libdis_test+0x1e4b: c5 e1 d5 20 vpmullw (%eax),%xmm3,%xmm4 + libdis_test+0x1e4f: c5 d1 d5 71 42 vpmullw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1e54: c5 f5 d5 d0 vpmullw %ymm0,%ymm1,%ymm2 + libdis_test+0x1e58: c5 e5 d5 23 vpmullw (%ebx),%ymm3,%ymm4 + libdis_test+0x1e5c: c5 d5 d5 72 42 vpmullw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1e61: c5 f1 f4 d0 vpmuludq %xmm0,%xmm1,%xmm2 + libdis_test+0x1e65: c5 e1 f4 20 vpmuludq (%eax),%xmm3,%xmm4 + libdis_test+0x1e69: c5 d1 f4 71 42 vpmuludq 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1e6e: c5 f5 f4 d0 vpmuludq %ymm0,%ymm1,%ymm2 + libdis_test+0x1e72: c5 e5 f4 23 vpmuludq (%ebx),%ymm3,%ymm4 + libdis_test+0x1e76: c5 d5 f4 72 42 vpmuludq 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1e7b: c5 f1 eb d0 vpor %xmm0,%xmm1,%xmm2 + libdis_test+0x1e7f: c5 e1 eb 20 vpor (%eax),%xmm3,%xmm4 + libdis_test+0x1e83: c5 d1 eb 71 42 vpor 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1e88: c5 f5 eb d0 vpor %ymm0,%ymm1,%ymm2 + libdis_test+0x1e8c: c5 e5 eb 23 vpor (%ebx),%ymm3,%ymm4 + libdis_test+0x1e90: c5 d5 eb 72 42 vpor 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1e95: c5 f1 f6 d0 vpsadbw %xmm0,%xmm1,%xmm2 + libdis_test+0x1e99: c5 e1 f6 20 vpsadbw (%eax),%xmm3,%xmm4 + libdis_test+0x1e9d: c5 d1 f6 71 42 vpsadbw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1ea2: c5 f5 f6 d0 vpsadbw %ymm0,%ymm1,%ymm2 + libdis_test+0x1ea6: c5 e5 f6 23 vpsadbw (%ebx),%ymm3,%ymm4 + libdis_test+0x1eaa: c5 d5 f6 72 42 vpsadbw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1eaf: c4 e2 71 00 d0 vpshufb %xmm0,%xmm1,%xmm2 + libdis_test+0x1eb4: c4 e2 61 00 20 vpshufb (%eax),%xmm3,%xmm4 + libdis_test+0x1eb9: c4 e2 51 00 71 42 vpshufb 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1ebf: c4 e2 75 00 d0 vpshufb %ymm0,%ymm1,%ymm2 + libdis_test+0x1ec4: c4 e2 65 00 23 vpshufb (%ebx),%ymm3,%ymm4 + libdis_test+0x1ec9: c4 e2 55 00 72 42 vpshufb 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1ecf: c5 f9 70 c8 42 vpshufd $0x42,%xmm0,%xmm1 + libdis_test+0x1ed4: c5 f9 70 1e 23 vpshufd $0x23,(%esi),%xmm3 + libdis_test+0x1ed9: c5 f9 70 5f 42 42 vpshufd $0x42,0x42(%edi),%xmm3 + libdis_test+0x1edf: c5 fd 70 c8 42 vpshufd $0x42,%ymm0,%ymm1 + libdis_test+0x1ee4: c5 fd 70 1e 23 vpshufd $0x23,(%esi),%ymm3 + libdis_test+0x1ee9: c5 fd 70 5f 42 42 vpshufd $0x42,0x42(%edi),%ymm3 + libdis_test+0x1eef: c5 fa 70 c8 42 vpshufhw $0x42,%xmm0,%xmm1 + libdis_test+0x1ef4: c5 fa 70 1e 23 vpshufhw $0x23,(%esi),%xmm3 + libdis_test+0x1ef9: c5 fa 70 5f 42 42 vpshufhw $0x42,0x42(%edi),%xmm3 + libdis_test+0x1eff: c5 fe 70 c8 42 vpshufhw $0x42,%ymm0,%ymm1 + libdis_test+0x1f04: c5 fe 70 1e 23 vpshufhw $0x23,(%esi),%ymm3 + libdis_test+0x1f09: c5 fe 70 5f 42 42 vpshufhw $0x42,0x42(%edi),%ymm3 + libdis_test+0x1f0f: c5 fb 70 c8 42 vpshuflw $0x42,%xmm0,%xmm1 + libdis_test+0x1f14: c5 fb 70 1e 23 vpshuflw $0x23,(%esi),%xmm3 + libdis_test+0x1f19: c5 fb 70 5f 42 42 vpshuflw $0x42,0x42(%edi),%xmm3 + libdis_test+0x1f1f: c5 ff 70 c8 42 vpshuflw $0x42,%ymm0,%ymm1 + libdis_test+0x1f24: c5 ff 70 1e 23 vpshuflw $0x23,(%esi),%ymm3 + libdis_test+0x1f29: c5 ff 70 5f 42 42 vpshuflw $0x42,0x42(%edi),%ymm3 + libdis_test+0x1f2f: c4 e2 71 08 d0 vpsignb %xmm0,%xmm1,%xmm2 + libdis_test+0x1f34: c4 e2 61 08 20 vpsignb (%eax),%xmm3,%xmm4 + libdis_test+0x1f39: c4 e2 51 08 71 42 vpsignb 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1f3f: c4 e2 75 08 d0 vpsignb %ymm0,%ymm1,%ymm2 + libdis_test+0x1f44: c4 e2 65 08 23 vpsignb (%ebx),%ymm3,%ymm4 + libdis_test+0x1f49: c4 e2 55 08 72 42 vpsignb 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1f4f: c4 e2 71 0a d0 vpsignd %xmm0,%xmm1,%xmm2 + libdis_test+0x1f54: c4 e2 61 0a 20 vpsignd (%eax),%xmm3,%xmm4 + libdis_test+0x1f59: c4 e2 51 0a 71 42 vpsignd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1f5f: c4 e2 75 0a d0 vpsignd %ymm0,%ymm1,%ymm2 + libdis_test+0x1f64: c4 e2 65 0a 23 vpsignd (%ebx),%ymm3,%ymm4 + libdis_test+0x1f69: c4 e2 55 0a 72 42 vpsignd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1f6f: c4 e2 71 09 d0 vpsignw %xmm0,%xmm1,%xmm2 + libdis_test+0x1f74: c4 e2 61 09 20 vpsignw (%eax),%xmm3,%xmm4 + libdis_test+0x1f79: c4 e2 51 09 71 42 vpsignw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x1f7f: c4 e2 75 09 d0 vpsignw %ymm0,%ymm1,%ymm2 + libdis_test+0x1f84: c4 e2 65 09 23 vpsignw (%ebx),%ymm3,%ymm4 + libdis_test+0x1f89: c4 e2 55 09 72 42 vpsignw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x1f8f: c5 f1 f2 d0 vpslld %xmm0,%xmm1,%xmm2 + libdis_test+0x1f93: c5 e1 f2 20 vpslld (%eax),%xmm3,%xmm4 + libdis_test+0x1f97: c5 d9 f2 6b 10 vpslld 0x10(%ebx),%xmm4,%xmm5 + libdis_test+0x1f9c: c5 c1 72 f6 04 vpslld $0x4,%xmm6,%xmm7 + libdis_test+0x1fa1: c5 f5 f2 d0 vpslld %ymm0,%ymm1,%ymm2 + libdis_test+0x1fa5: c5 e5 f2 20 vpslld (%eax),%ymm3,%ymm4 + libdis_test+0x1fa9: c5 dd f2 6b 10 vpslld 0x10(%ebx),%ymm4,%ymm5 + libdis_test+0x1fae: c5 c5 72 f6 04 vpslld $0x4,%ymm6,%ymm7 + libdis_test+0x1fb3: c5 f1 73 f8 07 vpslldq $0x7,%xmm0,%xmm1 + libdis_test+0x1fb8: c5 f5 73 f8 07 vpslldq $0x7,%ymm0,%ymm1 + libdis_test+0x1fbd: c5 f1 f3 d0 vpsllq %xmm0,%xmm1,%xmm2 + libdis_test+0x1fc1: c5 e1 f3 20 vpsllq (%eax),%xmm3,%xmm4 + libdis_test+0x1fc5: c5 d9 f3 6b 10 vpsllq 0x10(%ebx),%xmm4,%xmm5 + libdis_test+0x1fca: c5 c1 73 f6 04 vpsllq $0x4,%xmm6,%xmm7 + libdis_test+0x1fcf: c5 f5 f3 d0 vpsllq %ymm0,%ymm1,%ymm2 + libdis_test+0x1fd3: c5 e5 f3 20 vpsllq (%eax),%ymm3,%ymm4 + libdis_test+0x1fd7: c5 dd f3 6b 10 vpsllq 0x10(%ebx),%ymm4,%ymm5 + libdis_test+0x1fdc: c5 c5 73 f6 04 vpsllq $0x4,%ymm6,%ymm7 + libdis_test+0x1fe1: c5 f1 f1 d0 vpsllw %xmm0,%xmm1,%xmm2 + libdis_test+0x1fe5: c5 e1 f1 20 vpsllw (%eax),%xmm3,%xmm4 + libdis_test+0x1fe9: c5 d9 f1 6b 10 vpsllw 0x10(%ebx),%xmm4,%xmm5 + libdis_test+0x1fee: c5 c1 71 f6 04 vpsllw $0x4,%xmm6,%xmm7 + libdis_test+0x1ff3: c5 f5 f1 d0 vpsllw %ymm0,%ymm1,%ymm2 + libdis_test+0x1ff7: c5 e5 f1 20 vpsllw (%eax),%ymm3,%ymm4 + libdis_test+0x1ffb: c5 dd f1 6b 10 vpsllw 0x10(%ebx),%ymm4,%ymm5 + libdis_test+0x2000: c5 c5 71 f6 04 vpsllw $0x4,%ymm6,%ymm7 + libdis_test+0x2005: c5 f1 e2 d0 vpsrad %xmm0,%xmm1,%xmm2 + libdis_test+0x2009: c5 e1 e2 20 vpsrad (%eax),%xmm3,%xmm4 + libdis_test+0x200d: c5 d9 e2 6b 10 vpsrad 0x10(%ebx),%xmm4,%xmm5 + libdis_test+0x2012: c5 c1 72 e6 04 vpsrad $0x4,%xmm6,%xmm7 + libdis_test+0x2017: c5 f5 e2 d0 vpsrad %ymm0,%ymm1,%ymm2 + libdis_test+0x201b: c5 e5 e2 20 vpsrad (%eax),%ymm3,%ymm4 + libdis_test+0x201f: c5 dd e2 6b 10 vpsrad 0x10(%ebx),%ymm4,%ymm5 + libdis_test+0x2024: c5 c5 72 e6 04 vpsrad $0x4,%ymm6,%ymm7 + libdis_test+0x2029: c5 f1 e1 d0 vpsraw %xmm0,%xmm1,%xmm2 + libdis_test+0x202d: c5 e1 e1 20 vpsraw (%eax),%xmm3,%xmm4 + libdis_test+0x2031: c5 d9 e1 6b 10 vpsraw 0x10(%ebx),%xmm4,%xmm5 + libdis_test+0x2036: c5 c1 71 e6 04 vpsraw $0x4,%xmm6,%xmm7 + libdis_test+0x203b: c5 f5 e1 d0 vpsraw %ymm0,%ymm1,%ymm2 + libdis_test+0x203f: c5 e5 e1 20 vpsraw (%eax),%ymm3,%ymm4 + libdis_test+0x2043: c5 dd e1 6b 10 vpsraw 0x10(%ebx),%ymm4,%ymm5 + libdis_test+0x2048: c5 c5 71 e6 04 vpsraw $0x4,%ymm6,%ymm7 + libdis_test+0x204d: c5 f1 d2 d0 vpsrld %xmm0,%xmm1,%xmm2 + libdis_test+0x2051: c5 e1 d2 20 vpsrld (%eax),%xmm3,%xmm4 + libdis_test+0x2055: c5 d9 d2 6b 10 vpsrld 0x10(%ebx),%xmm4,%xmm5 + libdis_test+0x205a: c5 c1 72 d6 04 vpsrld $0x4,%xmm6,%xmm7 + libdis_test+0x205f: c5 f5 d2 d0 vpsrld %ymm0,%ymm1,%ymm2 + libdis_test+0x2063: c5 e5 d2 20 vpsrld (%eax),%ymm3,%ymm4 + libdis_test+0x2067: c5 dd d2 6b 10 vpsrld 0x10(%ebx),%ymm4,%ymm5 + libdis_test+0x206c: c5 c5 72 d6 04 vpsrld $0x4,%ymm6,%ymm7 + libdis_test+0x2071: c5 f1 73 d8 07 vpsrldq $0x7,%xmm0,%xmm1 + libdis_test+0x2076: c5 f5 73 d8 07 vpsrldq $0x7,%ymm0,%ymm1 + libdis_test+0x207b: c5 f1 d3 d0 vpsrlq %xmm0,%xmm1,%xmm2 + libdis_test+0x207f: c5 e1 d3 20 vpsrlq (%eax),%xmm3,%xmm4 + libdis_test+0x2083: c5 d9 d3 6b 10 vpsrlq 0x10(%ebx),%xmm4,%xmm5 + libdis_test+0x2088: c5 c1 73 d6 04 vpsrlq $0x4,%xmm6,%xmm7 + libdis_test+0x208d: c5 f5 d3 d0 vpsrlq %ymm0,%ymm1,%ymm2 + libdis_test+0x2091: c5 e5 d3 20 vpsrlq (%eax),%ymm3,%ymm4 + libdis_test+0x2095: c5 dd d3 6b 10 vpsrlq 0x10(%ebx),%ymm4,%ymm5 + libdis_test+0x209a: c5 c5 73 d6 04 vpsrlq $0x4,%ymm6,%ymm7 + libdis_test+0x209f: c5 f1 d1 d0 vpsrlw %xmm0,%xmm1,%xmm2 + libdis_test+0x20a3: c5 e1 d1 20 vpsrlw (%eax),%xmm3,%xmm4 + libdis_test+0x20a7: c5 d9 d1 6b 10 vpsrlw 0x10(%ebx),%xmm4,%xmm5 + libdis_test+0x20ac: c5 c1 71 d6 04 vpsrlw $0x4,%xmm6,%xmm7 + libdis_test+0x20b1: c5 f5 d1 d0 vpsrlw %ymm0,%ymm1,%ymm2 + libdis_test+0x20b5: c5 e5 d1 20 vpsrlw (%eax),%ymm3,%ymm4 + libdis_test+0x20b9: c5 dd d1 6b 10 vpsrlw 0x10(%ebx),%ymm4,%ymm5 + libdis_test+0x20be: c5 c5 71 d6 04 vpsrlw $0x4,%ymm6,%ymm7 + libdis_test+0x20c3: c5 f1 f8 d0 vpsubb %xmm0,%xmm1,%xmm2 + libdis_test+0x20c7: c5 e1 f8 20 vpsubb (%eax),%xmm3,%xmm4 + libdis_test+0x20cb: c5 d1 f8 71 42 vpsubb 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x20d0: c5 f5 f8 d0 vpsubb %ymm0,%ymm1,%ymm2 + libdis_test+0x20d4: c5 e5 f8 23 vpsubb (%ebx),%ymm3,%ymm4 + libdis_test+0x20d8: c5 d5 f8 72 42 vpsubb 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x20dd: c5 f1 fa d0 vpsubd %xmm0,%xmm1,%xmm2 + libdis_test+0x20e1: c5 e1 fa 20 vpsubd (%eax),%xmm3,%xmm4 + libdis_test+0x20e5: c5 d1 fa 71 42 vpsubd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x20ea: c5 f5 fa d0 vpsubd %ymm0,%ymm1,%ymm2 + libdis_test+0x20ee: c5 e5 fa 23 vpsubd (%ebx),%ymm3,%ymm4 + libdis_test+0x20f2: c5 d5 fa 72 42 vpsubd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x20f7: c5 f1 fb d0 vpsubq %xmm0,%xmm1,%xmm2 + libdis_test+0x20fb: c5 e1 fb 20 vpsubq (%eax),%xmm3,%xmm4 + libdis_test+0x20ff: c5 d1 fb 71 42 vpsubq 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2104: c5 f5 fb d0 vpsubq %ymm0,%ymm1,%ymm2 + libdis_test+0x2108: c5 e5 fb 23 vpsubq (%ebx),%ymm3,%ymm4 + libdis_test+0x210c: c5 d5 fb 72 42 vpsubq 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2111: c5 f1 e8 d0 vpsubsb %xmm0,%xmm1,%xmm2 + libdis_test+0x2115: c5 e1 e8 20 vpsubsb (%eax),%xmm3,%xmm4 + libdis_test+0x2119: c5 d1 e8 71 42 vpsubsb 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x211e: c5 f5 e8 d0 vpsubsb %ymm0,%ymm1,%ymm2 + libdis_test+0x2122: c5 e5 e8 23 vpsubsb (%ebx),%ymm3,%ymm4 + libdis_test+0x2126: c5 d5 e8 72 42 vpsubsb 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x212b: c5 f1 e9 d0 vpsubsw %xmm0,%xmm1,%xmm2 + libdis_test+0x212f: c5 e1 e9 20 vpsubsw (%eax),%xmm3,%xmm4 + libdis_test+0x2133: c5 d1 e9 71 42 vpsubsw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2138: c5 f5 e9 d0 vpsubsw %ymm0,%ymm1,%ymm2 + libdis_test+0x213c: c5 e5 e9 23 vpsubsw (%ebx),%ymm3,%ymm4 + libdis_test+0x2140: c5 d5 e9 72 42 vpsubsw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2145: c5 f1 d8 d0 vpsubusb %xmm0,%xmm1,%xmm2 + libdis_test+0x2149: c5 e1 d8 20 vpsubusb (%eax),%xmm3,%xmm4 + libdis_test+0x214d: c5 d1 d8 71 42 vpsubusb 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2152: c5 f5 d8 d0 vpsubusb %ymm0,%ymm1,%ymm2 + libdis_test+0x2156: c5 e5 d8 23 vpsubusb (%ebx),%ymm3,%ymm4 + libdis_test+0x215a: c5 d5 d8 72 42 vpsubusb 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x215f: c5 f1 d9 d0 vpsubusw %xmm0,%xmm1,%xmm2 + libdis_test+0x2163: c5 e1 d9 20 vpsubusw (%eax),%xmm3,%xmm4 + libdis_test+0x2167: c5 d1 d9 71 42 vpsubusw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x216c: c5 f5 d9 d0 vpsubusw %ymm0,%ymm1,%ymm2 + libdis_test+0x2170: c5 e5 d9 23 vpsubusw (%ebx),%ymm3,%ymm4 + libdis_test+0x2174: c5 d5 d9 72 42 vpsubusw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2179: c5 f1 f9 d0 vpsubw %xmm0,%xmm1,%xmm2 + libdis_test+0x217d: c5 e1 f9 20 vpsubw (%eax),%xmm3,%xmm4 + libdis_test+0x2181: c5 d1 f9 71 42 vpsubw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2186: c5 f5 f9 d0 vpsubw %ymm0,%ymm1,%ymm2 + libdis_test+0x218a: c5 e5 f9 23 vpsubw (%ebx),%ymm3,%ymm4 + libdis_test+0x218e: c5 d5 f9 72 42 vpsubw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2193: c4 e2 79 17 c8 vptest %xmm0,%xmm1 + libdis_test+0x2198: c4 e2 79 17 1e vptest (%esi),%xmm3 + libdis_test+0x219d: c4 e2 79 17 5f 42 vptest 0x42(%edi),%xmm3 + libdis_test+0x21a3: c4 e2 7d 17 f7 vptest %ymm7,%ymm6 + libdis_test+0x21a8: c4 e2 7d 17 65 00 vptest 0x0(%ebp),%ymm4 + libdis_test+0x21ae: c4 e2 7d 17 64 24 vptest 0x42(%esp),%ymm4 42 - libdis_test+0x21bc: c5 f1 68 d0 vpunpckhbw %xmm0,%xmm1,%xmm2 - libdis_test+0x21c0: c5 e1 68 20 vpunpckhbw (%eax),%xmm3,%xmm4 - libdis_test+0x21c4: c5 d1 68 71 42 vpunpckhbw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x21c9: c5 f5 68 d0 vpunpckhbw %ymm0,%ymm1,%ymm2 - libdis_test+0x21cd: c5 e5 68 23 vpunpckhbw (%ebx),%ymm3,%ymm4 - libdis_test+0x21d1: c5 d5 68 72 42 vpunpckhbw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x21d6: c5 f1 6a d0 vpunpckhdq %xmm0,%xmm1,%xmm2 - libdis_test+0x21da: c5 e1 6a 20 vpunpckhdq (%eax),%xmm3,%xmm4 - libdis_test+0x21de: c5 d1 6a 71 42 vpunpckhdq 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x21e3: c5 f5 6a d0 vpunpckhdq %ymm0,%ymm1,%ymm2 - libdis_test+0x21e7: c5 e5 6a 23 vpunpckhdq (%ebx),%ymm3,%ymm4 - libdis_test+0x21eb: c5 d5 6a 72 42 vpunpckhdq 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x21f0: c5 f1 6d d0 vpunpckhqdq %xmm0,%xmm1,%xmm2 - libdis_test+0x21f4: c5 e1 6d 20 vpunpckhqdq (%eax),%xmm3,%xmm4 - libdis_test+0x21f8: c5 d1 6d 71 42 vpunpckhqdq 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x21fd: c5 f5 6d d0 vpunpckhqdq %ymm0,%ymm1,%ymm2 - libdis_test+0x2201: c5 e5 6d 23 vpunpckhqdq (%ebx),%ymm3,%ymm4 - libdis_test+0x2205: c5 d5 6d 72 42 vpunpckhqdq 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x220a: c5 f1 69 d0 vpunpckhwd %xmm0,%xmm1,%xmm2 - libdis_test+0x220e: c5 e1 69 20 vpunpckhwd (%eax),%xmm3,%xmm4 - libdis_test+0x2212: c5 d1 69 71 42 vpunpckhwd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2217: c5 f5 69 d0 vpunpckhwd %ymm0,%ymm1,%ymm2 - libdis_test+0x221b: c5 e5 69 23 vpunpckhwd (%ebx),%ymm3,%ymm4 - libdis_test+0x221f: c5 d5 69 72 42 vpunpckhwd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2224: c5 f1 60 d0 vpunpcklbw %xmm0,%xmm1,%xmm2 - libdis_test+0x2228: c5 e1 60 20 vpunpcklbw (%eax),%xmm3,%xmm4 - libdis_test+0x222c: c5 d1 60 71 42 vpunpcklbw 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2231: c5 f5 60 d0 vpunpcklbw %ymm0,%ymm1,%ymm2 - libdis_test+0x2235: c5 e5 60 23 vpunpcklbw (%ebx),%ymm3,%ymm4 - libdis_test+0x2239: c5 d5 60 72 42 vpunpcklbw 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x223e: c5 f1 62 d0 vpunpckldq %xmm0,%xmm1,%xmm2 - libdis_test+0x2242: c5 e1 62 20 vpunpckldq (%eax),%xmm3,%xmm4 - libdis_test+0x2246: c5 d1 62 71 42 vpunpckldq 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x224b: c5 f5 62 d0 vpunpckldq %ymm0,%ymm1,%ymm2 - libdis_test+0x224f: c5 e5 62 23 vpunpckldq (%ebx),%ymm3,%ymm4 - libdis_test+0x2253: c5 d5 62 72 42 vpunpckldq 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2258: c5 f1 6c d0 vpunpcklqdq %xmm0,%xmm1,%xmm2 - libdis_test+0x225c: c5 e1 6c 20 vpunpcklqdq (%eax),%xmm3,%xmm4 - libdis_test+0x2260: c5 d1 6c 71 42 vpunpcklqdq 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2265: c5 f5 6c d0 vpunpcklqdq %ymm0,%ymm1,%ymm2 - libdis_test+0x2269: c5 e5 6c 23 vpunpcklqdq (%ebx),%ymm3,%ymm4 - libdis_test+0x226d: c5 d5 6c 72 42 vpunpcklqdq 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2272: c5 f1 61 d0 vpunpcklwd %xmm0,%xmm1,%xmm2 - libdis_test+0x2276: c5 e1 61 20 vpunpcklwd (%eax),%xmm3,%xmm4 - libdis_test+0x227a: c5 d1 61 71 42 vpunpcklwd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x227f: c5 f5 61 d0 vpunpcklwd %ymm0,%ymm1,%ymm2 - libdis_test+0x2283: c5 e5 61 23 vpunpcklwd (%ebx),%ymm3,%ymm4 - libdis_test+0x2287: c5 d5 61 72 42 vpunpcklwd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x228c: c5 f1 ef d0 vpxor %xmm0,%xmm1,%xmm2 - libdis_test+0x2290: c5 e1 ef 20 vpxor (%eax),%xmm3,%xmm4 - libdis_test+0x2294: c5 d1 ef 71 42 vpxor 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2299: c5 f5 ef d0 vpxor %ymm0,%ymm1,%ymm2 - libdis_test+0x229d: c5 e5 ef 23 vpxor (%ebx),%ymm3,%ymm4 - libdis_test+0x22a1: c5 d5 ef 72 42 vpxor 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x22a6: c5 f8 53 c8 vrcpps %xmm0,%xmm1 - libdis_test+0x22aa: c5 f8 53 1e vrcpps (%esi),%xmm3 - libdis_test+0x22ae: c5 f8 53 5f 42 vrcpps 0x42(%edi),%xmm3 - libdis_test+0x22b3: c5 fc 53 f7 vrcpps %ymm7,%ymm6 - libdis_test+0x22b7: c5 fc 53 65 00 vrcpps 0x0(%ebp),%ymm4 - libdis_test+0x22bc: c5 fc 53 64 24 42 vrcpps 0x42(%esp),%ymm4 - libdis_test+0x22c2: c5 f2 53 d0 vrcpss %xmm0,%xmm1,%xmm2 - libdis_test+0x22c6: c5 e2 53 20 vrcpss (%eax),%xmm3,%xmm4 - libdis_test+0x22ca: c5 d2 53 71 42 vrcpss 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x22cf: c4 e3 79 09 c8 42 vroundpd $0x42,%xmm0,%xmm1 - libdis_test+0x22d5: c4 e3 79 09 1e 23 vroundpd $0x23,(%esi),%xmm3 - libdis_test+0x22db: c4 e3 79 09 5f 42 vroundpd $0x42,0x42(%edi),%xmm3 + libdis_test+0x21b5: c5 f1 68 d0 vpunpckhbw %xmm0,%xmm1,%xmm2 + libdis_test+0x21b9: c5 e1 68 20 vpunpckhbw (%eax),%xmm3,%xmm4 + libdis_test+0x21bd: c5 d1 68 71 42 vpunpckhbw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x21c2: c5 f5 68 d0 vpunpckhbw %ymm0,%ymm1,%ymm2 + libdis_test+0x21c6: c5 e5 68 23 vpunpckhbw (%ebx),%ymm3,%ymm4 + libdis_test+0x21ca: c5 d5 68 72 42 vpunpckhbw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x21cf: c5 f1 6a d0 vpunpckhdq %xmm0,%xmm1,%xmm2 + libdis_test+0x21d3: c5 e1 6a 20 vpunpckhdq (%eax),%xmm3,%xmm4 + libdis_test+0x21d7: c5 d1 6a 71 42 vpunpckhdq 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x21dc: c5 f5 6a d0 vpunpckhdq %ymm0,%ymm1,%ymm2 + libdis_test+0x21e0: c5 e5 6a 23 vpunpckhdq (%ebx),%ymm3,%ymm4 + libdis_test+0x21e4: c5 d5 6a 72 42 vpunpckhdq 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x21e9: c5 f1 6d d0 vpunpckhqdq %xmm0,%xmm1,%xmm2 + libdis_test+0x21ed: c5 e1 6d 20 vpunpckhqdq (%eax),%xmm3,%xmm4 + libdis_test+0x21f1: c5 d1 6d 71 42 vpunpckhqdq 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x21f6: c5 f5 6d d0 vpunpckhqdq %ymm0,%ymm1,%ymm2 + libdis_test+0x21fa: c5 e5 6d 23 vpunpckhqdq (%ebx),%ymm3,%ymm4 + libdis_test+0x21fe: c5 d5 6d 72 42 vpunpckhqdq 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2203: c5 f1 69 d0 vpunpckhwd %xmm0,%xmm1,%xmm2 + libdis_test+0x2207: c5 e1 69 20 vpunpckhwd (%eax),%xmm3,%xmm4 + libdis_test+0x220b: c5 d1 69 71 42 vpunpckhwd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2210: c5 f5 69 d0 vpunpckhwd %ymm0,%ymm1,%ymm2 + libdis_test+0x2214: c5 e5 69 23 vpunpckhwd (%ebx),%ymm3,%ymm4 + libdis_test+0x2218: c5 d5 69 72 42 vpunpckhwd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x221d: c5 f1 60 d0 vpunpcklbw %xmm0,%xmm1,%xmm2 + libdis_test+0x2221: c5 e1 60 20 vpunpcklbw (%eax),%xmm3,%xmm4 + libdis_test+0x2225: c5 d1 60 71 42 vpunpcklbw 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x222a: c5 f5 60 d0 vpunpcklbw %ymm0,%ymm1,%ymm2 + libdis_test+0x222e: c5 e5 60 23 vpunpcklbw (%ebx),%ymm3,%ymm4 + libdis_test+0x2232: c5 d5 60 72 42 vpunpcklbw 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2237: c5 f1 62 d0 vpunpckldq %xmm0,%xmm1,%xmm2 + libdis_test+0x223b: c5 e1 62 20 vpunpckldq (%eax),%xmm3,%xmm4 + libdis_test+0x223f: c5 d1 62 71 42 vpunpckldq 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2244: c5 f5 62 d0 vpunpckldq %ymm0,%ymm1,%ymm2 + libdis_test+0x2248: c5 e5 62 23 vpunpckldq (%ebx),%ymm3,%ymm4 + libdis_test+0x224c: c5 d5 62 72 42 vpunpckldq 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2251: c5 f1 6c d0 vpunpcklqdq %xmm0,%xmm1,%xmm2 + libdis_test+0x2255: c5 e1 6c 20 vpunpcklqdq (%eax),%xmm3,%xmm4 + libdis_test+0x2259: c5 d1 6c 71 42 vpunpcklqdq 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x225e: c5 f5 6c d0 vpunpcklqdq %ymm0,%ymm1,%ymm2 + libdis_test+0x2262: c5 e5 6c 23 vpunpcklqdq (%ebx),%ymm3,%ymm4 + libdis_test+0x2266: c5 d5 6c 72 42 vpunpcklqdq 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x226b: c5 f1 61 d0 vpunpcklwd %xmm0,%xmm1,%xmm2 + libdis_test+0x226f: c5 e1 61 20 vpunpcklwd (%eax),%xmm3,%xmm4 + libdis_test+0x2273: c5 d1 61 71 42 vpunpcklwd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2278: c5 f5 61 d0 vpunpcklwd %ymm0,%ymm1,%ymm2 + libdis_test+0x227c: c5 e5 61 23 vpunpcklwd (%ebx),%ymm3,%ymm4 + libdis_test+0x2280: c5 d5 61 72 42 vpunpcklwd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2285: c5 f1 ef d0 vpxor %xmm0,%xmm1,%xmm2 + libdis_test+0x2289: c5 e1 ef 20 vpxor (%eax),%xmm3,%xmm4 + libdis_test+0x228d: c5 d1 ef 71 42 vpxor 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2292: c5 f5 ef d0 vpxor %ymm0,%ymm1,%ymm2 + libdis_test+0x2296: c5 e5 ef 23 vpxor (%ebx),%ymm3,%ymm4 + libdis_test+0x229a: c5 d5 ef 72 42 vpxor 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x229f: c5 f8 53 c8 vrcpps %xmm0,%xmm1 + libdis_test+0x22a3: c5 f8 53 1e vrcpps (%esi),%xmm3 + libdis_test+0x22a7: c5 f8 53 5f 42 vrcpps 0x42(%edi),%xmm3 + libdis_test+0x22ac: c5 fc 53 f7 vrcpps %ymm7,%ymm6 + libdis_test+0x22b0: c5 fc 53 65 00 vrcpps 0x0(%ebp),%ymm4 + libdis_test+0x22b5: c5 fc 53 64 24 42 vrcpps 0x42(%esp),%ymm4 + libdis_test+0x22bb: c5 f2 53 d0 vrcpss %xmm0,%xmm1,%xmm2 + libdis_test+0x22bf: c5 e2 53 20 vrcpss (%eax),%xmm3,%xmm4 + libdis_test+0x22c3: c5 d2 53 71 42 vrcpss 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x22c8: c4 e3 79 09 c8 42 vroundpd $0x42,%xmm0,%xmm1 + libdis_test+0x22ce: c4 e3 79 09 1e 23 vroundpd $0x23,(%esi),%xmm3 + libdis_test+0x22d4: c4 e3 79 09 5f 42 vroundpd $0x42,0x42(%edi),%xmm3 42 - libdis_test+0x22e2: c4 e3 7d 09 c8 42 vroundpd $0x42,%ymm0,%ymm1 - libdis_test+0x22e8: c4 e3 7d 09 1e 23 vroundpd $0x23,(%esi),%ymm3 - libdis_test+0x22ee: c4 e3 7d 09 5f 42 vroundpd $0x42,0x42(%edi),%ymm3 + libdis_test+0x22db: c4 e3 7d 09 c8 42 vroundpd $0x42,%ymm0,%ymm1 + libdis_test+0x22e1: c4 e3 7d 09 1e 23 vroundpd $0x23,(%esi),%ymm3 + libdis_test+0x22e7: c4 e3 7d 09 5f 42 vroundpd $0x42,0x42(%edi),%ymm3 42 - libdis_test+0x22f5: c4 e3 79 08 c8 42 vroundps $0x42,%xmm0,%xmm1 - libdis_test+0x22fb: c4 e3 79 08 1e 23 vroundps $0x23,(%esi),%xmm3 - libdis_test+0x2301: c4 e3 79 08 5f 42 vroundps $0x42,0x42(%edi),%xmm3 + libdis_test+0x22ee: c4 e3 79 08 c8 42 vroundps $0x42,%xmm0,%xmm1 + libdis_test+0x22f4: c4 e3 79 08 1e 23 vroundps $0x23,(%esi),%xmm3 + libdis_test+0x22fa: c4 e3 79 08 5f 42 vroundps $0x42,0x42(%edi),%xmm3 42 - libdis_test+0x2308: c4 e3 7d 08 c8 42 vroundps $0x42,%ymm0,%ymm1 - libdis_test+0x230e: c4 e3 7d 08 1e 23 vroundps $0x23,(%esi),%ymm3 - libdis_test+0x2314: c4 e3 7d 08 5f 42 vroundps $0x42,0x42(%edi),%ymm3 + libdis_test+0x2301: c4 e3 7d 08 c8 42 vroundps $0x42,%ymm0,%ymm1 + libdis_test+0x2307: c4 e3 7d 08 1e 23 vroundps $0x23,(%esi),%ymm3 + libdis_test+0x230d: c4 e3 7d 08 5f 42 vroundps $0x42,0x42(%edi),%ymm3 42 - libdis_test+0x231b: c4 e3 51 0b fb 48 vroundsd $0x48,%xmm3,%xmm5,%xmm7 - libdis_test+0x2321: c4 e3 69 0b 23 48 vroundsd $0x48,(%ebx),%xmm2,%xmm4 - libdis_test+0x2327: c4 e3 71 0b 73 08 vroundsd $0x48,0x8(%ebx),%xmm1,%xmm6 + libdis_test+0x2314: c4 e3 51 0b fb 48 vroundsd $0x48,%xmm3,%xmm5,%xmm7 + libdis_test+0x231a: c4 e3 69 0b 23 48 vroundsd $0x48,(%ebx),%xmm2,%xmm4 + libdis_test+0x2320: c4 e3 71 0b 73 08 vroundsd $0x48,0x8(%ebx),%xmm1,%xmm6 48 - libdis_test+0x232e: c4 e3 51 0a fb 48 vroundss $0x48,%xmm3,%xmm5,%xmm7 - libdis_test+0x2334: c4 e3 69 0a 23 48 vroundss $0x48,(%ebx),%xmm2,%xmm4 - libdis_test+0x233a: c4 e3 71 0a 73 08 vroundss $0x48,0x8(%ebx),%xmm1,%xmm6 + libdis_test+0x2327: c4 e3 51 0a fb 48 vroundss $0x48,%xmm3,%xmm5,%xmm7 + libdis_test+0x232d: c4 e3 69 0a 23 48 vroundss $0x48,(%ebx),%xmm2,%xmm4 + libdis_test+0x2333: c4 e3 71 0a 73 08 vroundss $0x48,0x8(%ebx),%xmm1,%xmm6 48 - libdis_test+0x2341: c5 f8 52 c8 vrsqrtps %xmm0,%xmm1 - libdis_test+0x2345: c5 f8 52 1e vrsqrtps (%esi),%xmm3 - libdis_test+0x2349: c5 f8 52 5f 42 vrsqrtps 0x42(%edi),%xmm3 - libdis_test+0x234e: c5 fc 52 f7 vrsqrtps %ymm7,%ymm6 - libdis_test+0x2352: c5 fc 52 65 00 vrsqrtps 0x0(%ebp),%ymm4 - libdis_test+0x2357: c5 fc 52 64 24 42 vrsqrtps 0x42(%esp),%ymm4 - libdis_test+0x235d: c5 f2 52 d0 vrsqrtss %xmm0,%xmm1,%xmm2 - libdis_test+0x2361: c5 e2 52 20 vrsqrtss (%eax),%xmm3,%xmm4 - libdis_test+0x2365: c5 d2 52 71 42 vrsqrtss 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x236a: c5 d1 c6 fb 48 vshufpd $0x48,%xmm3,%xmm5,%xmm7 - libdis_test+0x236f: c5 e9 c6 23 48 vshufpd $0x48,(%ebx),%xmm2,%xmm4 - libdis_test+0x2374: c5 f1 c6 73 08 48 vshufpd $0x48,0x8(%ebx),%xmm1,%xmm6 - libdis_test+0x237a: c5 d5 c6 fb 48 vshufpd $0x48,%ymm3,%ymm5,%ymm7 - libdis_test+0x237f: c5 ed c6 23 48 vshufpd $0x48,(%ebx),%ymm2,%ymm4 - libdis_test+0x2384: c5 f5 c6 73 08 48 vshufpd $0x48,0x8(%ebx),%ymm1,%ymm6 - libdis_test+0x238a: c5 d0 c6 fb 48 vshufps $0x48,%xmm3,%xmm5,%xmm7 - libdis_test+0x238f: c5 e8 c6 23 48 vshufps $0x48,(%ebx),%xmm2,%xmm4 - libdis_test+0x2394: c5 f0 c6 73 08 48 vshufps $0x48,0x8(%ebx),%xmm1,%xmm6 - libdis_test+0x239a: c5 d4 c6 fb 48 vshufps $0x48,%ymm3,%ymm5,%ymm7 - libdis_test+0x239f: c5 ec c6 23 48 vshufps $0x48,(%ebx),%ymm2,%ymm4 - libdis_test+0x23a4: c5 f4 c6 73 08 48 vshufps $0x48,0x8(%ebx),%ymm1,%ymm6 - libdis_test+0x23aa: c5 f9 51 c8 vsqrtpd %xmm0,%xmm1 - libdis_test+0x23ae: c5 f9 51 1e vsqrtpd (%esi),%xmm3 - libdis_test+0x23b2: c5 f9 51 5f 42 vsqrtpd 0x42(%edi),%xmm3 - libdis_test+0x23b7: c5 fd 51 f7 vsqrtpd %ymm7,%ymm6 - libdis_test+0x23bb: c5 fd 51 65 00 vsqrtpd 0x0(%ebp),%ymm4 - libdis_test+0x23c0: c5 fd 51 64 24 42 vsqrtpd 0x42(%esp),%ymm4 - libdis_test+0x23c6: c5 f8 51 c8 vsqrtps %xmm0,%xmm1 - libdis_test+0x23ca: c5 f8 51 1e vsqrtps (%esi),%xmm3 - libdis_test+0x23ce: c5 f8 51 5f 42 vsqrtps 0x42(%edi),%xmm3 - libdis_test+0x23d3: c5 fc 51 f7 vsqrtps %ymm7,%ymm6 - libdis_test+0x23d7: c5 fc 51 65 00 vsqrtps 0x0(%ebp),%ymm4 - libdis_test+0x23dc: c5 fc 51 64 24 42 vsqrtps 0x42(%esp),%ymm4 - libdis_test+0x23e2: c5 f3 51 d0 vsqrtsd %xmm0,%xmm1,%xmm2 - libdis_test+0x23e6: c5 e3 51 20 vsqrtsd (%eax),%xmm3,%xmm4 - libdis_test+0x23ea: c5 d3 51 71 42 vsqrtsd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x23ef: c5 f2 51 d0 vsqrtss %xmm0,%xmm1,%xmm2 - libdis_test+0x23f3: c5 e2 51 20 vsqrtss (%eax),%xmm3,%xmm4 - libdis_test+0x23f7: c5 d2 51 71 42 vsqrtss 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x23fc: c5 f8 ae 1a vstmxcsr (%edx) - libdis_test+0x2400: c5 f8 ae 5a 08 vstmxcsr 0x8(%edx) - libdis_test+0x2405: c5 f1 5c d0 vsubpd %xmm0,%xmm1,%xmm2 - libdis_test+0x2409: c5 e1 5c 20 vsubpd (%eax),%xmm3,%xmm4 - libdis_test+0x240d: c5 d1 5c 71 42 vsubpd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2412: c5 f5 5c d0 vsubpd %ymm0,%ymm1,%ymm2 - libdis_test+0x2416: c5 e5 5c 23 vsubpd (%ebx),%ymm3,%ymm4 - libdis_test+0x241a: c5 d5 5c 72 42 vsubpd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x241f: c5 f0 5c d0 vsubps %xmm0,%xmm1,%xmm2 - libdis_test+0x2423: c5 e0 5c 20 vsubps (%eax),%xmm3,%xmm4 - libdis_test+0x2427: c5 d0 5c 71 42 vsubps 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x242c: c5 f4 5c d0 vsubps %ymm0,%ymm1,%ymm2 - libdis_test+0x2430: c5 e4 5c 23 vsubps (%ebx),%ymm3,%ymm4 - libdis_test+0x2434: c5 d4 5c 72 42 vsubps 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2439: c5 f3 5c d0 vsubsd %xmm0,%xmm1,%xmm2 - libdis_test+0x243d: c5 e3 5c 20 vsubsd (%eax),%xmm3,%xmm4 - libdis_test+0x2441: c5 d3 5c 71 42 vsubsd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2446: c5 f2 5c d0 vsubss %xmm0,%xmm1,%xmm2 - libdis_test+0x244a: c5 e2 5c 20 vsubss (%eax),%xmm3,%xmm4 - libdis_test+0x244e: c5 d2 5c 71 42 vsubss 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2453: c4 e2 79 0f c8 vtestpd %xmm0,%xmm1 - libdis_test+0x2458: c4 e2 79 0f 1e vtestpd (%esi),%xmm3 - libdis_test+0x245d: c4 e2 79 0f 5f 42 vtestpd 0x42(%edi),%xmm3 - libdis_test+0x2463: c4 e2 7d 0f f7 vtestpd %ymm7,%ymm6 - libdis_test+0x2468: c4 e2 7d 0f 65 00 vtestpd 0x0(%ebp),%ymm4 - libdis_test+0x246e: c4 e2 7d 0f 64 24 vtestpd 0x42(%esp),%ymm4 + libdis_test+0x233a: c5 f8 52 c8 vrsqrtps %xmm0,%xmm1 + libdis_test+0x233e: c5 f8 52 1e vrsqrtps (%esi),%xmm3 + libdis_test+0x2342: c5 f8 52 5f 42 vrsqrtps 0x42(%edi),%xmm3 + libdis_test+0x2347: c5 fc 52 f7 vrsqrtps %ymm7,%ymm6 + libdis_test+0x234b: c5 fc 52 65 00 vrsqrtps 0x0(%ebp),%ymm4 + libdis_test+0x2350: c5 fc 52 64 24 42 vrsqrtps 0x42(%esp),%ymm4 + libdis_test+0x2356: c5 f2 52 d0 vrsqrtss %xmm0,%xmm1,%xmm2 + libdis_test+0x235a: c5 e2 52 20 vrsqrtss (%eax),%xmm3,%xmm4 + libdis_test+0x235e: c5 d2 52 71 42 vrsqrtss 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2363: c5 d1 c6 fb 48 vshufpd $0x48,%xmm3,%xmm5,%xmm7 + libdis_test+0x2368: c5 e9 c6 23 48 vshufpd $0x48,(%ebx),%xmm2,%xmm4 + libdis_test+0x236d: c5 f1 c6 73 08 48 vshufpd $0x48,0x8(%ebx),%xmm1,%xmm6 + libdis_test+0x2373: c5 d5 c6 fb 48 vshufpd $0x48,%ymm3,%ymm5,%ymm7 + libdis_test+0x2378: c5 ed c6 23 48 vshufpd $0x48,(%ebx),%ymm2,%ymm4 + libdis_test+0x237d: c5 f5 c6 73 08 48 vshufpd $0x48,0x8(%ebx),%ymm1,%ymm6 + libdis_test+0x2383: c5 d0 c6 fb 48 vshufps $0x48,%xmm3,%xmm5,%xmm7 + libdis_test+0x2388: c5 e8 c6 23 48 vshufps $0x48,(%ebx),%xmm2,%xmm4 + libdis_test+0x238d: c5 f0 c6 73 08 48 vshufps $0x48,0x8(%ebx),%xmm1,%xmm6 + libdis_test+0x2393: c5 d4 c6 fb 48 vshufps $0x48,%ymm3,%ymm5,%ymm7 + libdis_test+0x2398: c5 ec c6 23 48 vshufps $0x48,(%ebx),%ymm2,%ymm4 + libdis_test+0x239d: c5 f4 c6 73 08 48 vshufps $0x48,0x8(%ebx),%ymm1,%ymm6 + libdis_test+0x23a3: c5 f9 51 c8 vsqrtpd %xmm0,%xmm1 + libdis_test+0x23a7: c5 f9 51 1e vsqrtpd (%esi),%xmm3 + libdis_test+0x23ab: c5 f9 51 5f 42 vsqrtpd 0x42(%edi),%xmm3 + libdis_test+0x23b0: c5 fd 51 f7 vsqrtpd %ymm7,%ymm6 + libdis_test+0x23b4: c5 fd 51 65 00 vsqrtpd 0x0(%ebp),%ymm4 + libdis_test+0x23b9: c5 fd 51 64 24 42 vsqrtpd 0x42(%esp),%ymm4 + libdis_test+0x23bf: c5 f8 51 c8 vsqrtps %xmm0,%xmm1 + libdis_test+0x23c3: c5 f8 51 1e vsqrtps (%esi),%xmm3 + libdis_test+0x23c7: c5 f8 51 5f 42 vsqrtps 0x42(%edi),%xmm3 + libdis_test+0x23cc: c5 fc 51 f7 vsqrtps %ymm7,%ymm6 + libdis_test+0x23d0: c5 fc 51 65 00 vsqrtps 0x0(%ebp),%ymm4 + libdis_test+0x23d5: c5 fc 51 64 24 42 vsqrtps 0x42(%esp),%ymm4 + libdis_test+0x23db: c5 f3 51 d0 vsqrtsd %xmm0,%xmm1,%xmm2 + libdis_test+0x23df: c5 e3 51 20 vsqrtsd (%eax),%xmm3,%xmm4 + libdis_test+0x23e3: c5 d3 51 71 42 vsqrtsd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x23e8: c5 f2 51 d0 vsqrtss %xmm0,%xmm1,%xmm2 + libdis_test+0x23ec: c5 e2 51 20 vsqrtss (%eax),%xmm3,%xmm4 + libdis_test+0x23f0: c5 d2 51 71 42 vsqrtss 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x23f5: c5 f8 ae 1a vstmxcsr (%edx) + libdis_test+0x23f9: c5 f8 ae 5a 08 vstmxcsr 0x8(%edx) + libdis_test+0x23fe: c5 f1 5c d0 vsubpd %xmm0,%xmm1,%xmm2 + libdis_test+0x2402: c5 e1 5c 20 vsubpd (%eax),%xmm3,%xmm4 + libdis_test+0x2406: c5 d1 5c 71 42 vsubpd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x240b: c5 f5 5c d0 vsubpd %ymm0,%ymm1,%ymm2 + libdis_test+0x240f: c5 e5 5c 23 vsubpd (%ebx),%ymm3,%ymm4 + libdis_test+0x2413: c5 d5 5c 72 42 vsubpd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2418: c5 f0 5c d0 vsubps %xmm0,%xmm1,%xmm2 + libdis_test+0x241c: c5 e0 5c 20 vsubps (%eax),%xmm3,%xmm4 + libdis_test+0x2420: c5 d0 5c 71 42 vsubps 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2425: c5 f4 5c d0 vsubps %ymm0,%ymm1,%ymm2 + libdis_test+0x2429: c5 e4 5c 23 vsubps (%ebx),%ymm3,%ymm4 + libdis_test+0x242d: c5 d4 5c 72 42 vsubps 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2432: c5 f3 5c d0 vsubsd %xmm0,%xmm1,%xmm2 + libdis_test+0x2436: c5 e3 5c 20 vsubsd (%eax),%xmm3,%xmm4 + libdis_test+0x243a: c5 d3 5c 71 42 vsubsd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x243f: c5 f2 5c d0 vsubss %xmm0,%xmm1,%xmm2 + libdis_test+0x2443: c5 e2 5c 20 vsubss (%eax),%xmm3,%xmm4 + libdis_test+0x2447: c5 d2 5c 71 42 vsubss 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x244c: c4 e2 79 0f c8 vtestpd %xmm0,%xmm1 + libdis_test+0x2451: c4 e2 79 0f 1e vtestpd (%esi),%xmm3 + libdis_test+0x2456: c4 e2 79 0f 5f 42 vtestpd 0x42(%edi),%xmm3 + libdis_test+0x245c: c4 e2 7d 0f f7 vtestpd %ymm7,%ymm6 + libdis_test+0x2461: c4 e2 7d 0f 65 00 vtestpd 0x0(%ebp),%ymm4 + libdis_test+0x2467: c4 e2 7d 0f 64 24 vtestpd 0x42(%esp),%ymm4 42 - libdis_test+0x2475: c4 e2 79 0e c8 vtestps %xmm0,%xmm1 - libdis_test+0x247a: c4 e2 79 0e 1e vtestps (%esi),%xmm3 - libdis_test+0x247f: c4 e2 79 0e 5f 42 vtestps 0x42(%edi),%xmm3 - libdis_test+0x2485: c4 e2 7d 0e f7 vtestps %ymm7,%ymm6 - libdis_test+0x248a: c4 e2 7d 0e 65 00 vtestps 0x0(%ebp),%ymm4 - libdis_test+0x2490: c4 e2 7d 0e 64 24 vtestps 0x42(%esp),%ymm4 + libdis_test+0x246e: c4 e2 79 0e c8 vtestps %xmm0,%xmm1 + libdis_test+0x2473: c4 e2 79 0e 1e vtestps (%esi),%xmm3 + libdis_test+0x2478: c4 e2 79 0e 5f 42 vtestps 0x42(%edi),%xmm3 + libdis_test+0x247e: c4 e2 7d 0e f7 vtestps %ymm7,%ymm6 + libdis_test+0x2483: c4 e2 7d 0e 65 00 vtestps 0x0(%ebp),%ymm4 + libdis_test+0x2489: c4 e2 7d 0e 64 24 vtestps 0x42(%esp),%ymm4 42 - libdis_test+0x2497: c5 f9 2e c8 vucomisd %xmm0,%xmm1 - libdis_test+0x249b: c5 f9 2e 1e vucomisd (%esi),%xmm3 - libdis_test+0x249f: c5 f9 2e 5f 42 vucomisd 0x42(%edi),%xmm3 - libdis_test+0x24a4: c5 f8 2e c8 vucomiss %xmm0,%xmm1 - libdis_test+0x24a8: c5 f8 2e 1e vucomiss (%esi),%xmm3 - libdis_test+0x24ac: c5 f8 2e 5f 42 vucomiss 0x42(%edi),%xmm3 - libdis_test+0x24b1: c5 f1 15 d0 vunpckhpd %xmm0,%xmm1,%xmm2 - libdis_test+0x24b5: c5 e1 15 20 vunpckhpd (%eax),%xmm3,%xmm4 - libdis_test+0x24b9: c5 d1 15 71 42 vunpckhpd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x24be: c5 f5 15 d0 vunpckhpd %ymm0,%ymm1,%ymm2 - libdis_test+0x24c2: c5 e5 15 23 vunpckhpd (%ebx),%ymm3,%ymm4 - libdis_test+0x24c6: c5 d5 15 72 42 vunpckhpd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x24cb: c5 f0 15 d0 vunpckhps %xmm0,%xmm1,%xmm2 - libdis_test+0x24cf: c5 e0 15 20 vunpckhps (%eax),%xmm3,%xmm4 - libdis_test+0x24d3: c5 d0 15 71 42 vunpckhps 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x24d8: c5 f4 15 d0 vunpckhps %ymm0,%ymm1,%ymm2 - libdis_test+0x24dc: c5 e4 15 23 vunpckhps (%ebx),%ymm3,%ymm4 - libdis_test+0x24e0: c5 d4 15 72 42 vunpckhps 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x24e5: c5 f1 14 d0 vunpcklpd %xmm0,%xmm1,%xmm2 - libdis_test+0x24e9: c5 e1 14 20 vunpcklpd (%eax),%xmm3,%xmm4 - libdis_test+0x24ed: c5 d1 14 71 42 vunpcklpd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x24f2: c5 f5 14 d0 vunpcklpd %ymm0,%ymm1,%ymm2 - libdis_test+0x24f6: c5 e5 14 23 vunpcklpd (%ebx),%ymm3,%ymm4 - libdis_test+0x24fa: c5 d5 14 72 42 vunpcklpd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x24ff: c5 f0 14 d0 vunpcklps %xmm0,%xmm1,%xmm2 - libdis_test+0x2503: c5 e0 14 20 vunpcklps (%eax),%xmm3,%xmm4 - libdis_test+0x2507: c5 d0 14 71 42 vunpcklps 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x250c: c5 f4 14 d0 vunpcklps %ymm0,%ymm1,%ymm2 - libdis_test+0x2510: c5 e4 14 23 vunpcklps (%ebx),%ymm3,%ymm4 - libdis_test+0x2514: c5 d4 14 72 42 vunpcklps 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2519: c5 f1 57 d0 vxorpd %xmm0,%xmm1,%xmm2 - libdis_test+0x251d: c5 e1 57 20 vxorpd (%eax),%xmm3,%xmm4 - libdis_test+0x2521: c5 d1 57 71 42 vxorpd 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2526: c5 f5 57 d0 vxorpd %ymm0,%ymm1,%ymm2 - libdis_test+0x252a: c5 e5 57 23 vxorpd (%ebx),%ymm3,%ymm4 - libdis_test+0x252e: c5 d5 57 72 42 vxorpd 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x2533: c5 f0 57 d0 vxorps %xmm0,%xmm1,%xmm2 - libdis_test+0x2537: c5 e0 57 20 vxorps (%eax),%xmm3,%xmm4 - libdis_test+0x253b: c5 d0 57 71 42 vxorps 0x42(%ecx),%xmm5,%xmm6 - libdis_test+0x2540: c5 f4 57 d0 vxorps %ymm0,%ymm1,%ymm2 - libdis_test+0x2544: c5 e4 57 23 vxorps (%ebx),%ymm3,%ymm4 - libdis_test+0x2548: c5 d4 57 72 42 vxorps 0x42(%edx),%ymm5,%ymm6 - libdis_test+0x254d: c5 fc 77 vzeroall - libdis_test+0x2550: c5 f8 77 vzeroupper + libdis_test+0x2490: c5 f9 2e c8 vucomisd %xmm0,%xmm1 + libdis_test+0x2494: c5 f9 2e 1e vucomisd (%esi),%xmm3 + libdis_test+0x2498: c5 f9 2e 5f 42 vucomisd 0x42(%edi),%xmm3 + libdis_test+0x249d: c5 f8 2e c8 vucomiss %xmm0,%xmm1 + libdis_test+0x24a1: c5 f8 2e 1e vucomiss (%esi),%xmm3 + libdis_test+0x24a5: c5 f8 2e 5f 42 vucomiss 0x42(%edi),%xmm3 + libdis_test+0x24aa: c5 f1 15 d0 vunpckhpd %xmm0,%xmm1,%xmm2 + libdis_test+0x24ae: c5 e1 15 20 vunpckhpd (%eax),%xmm3,%xmm4 + libdis_test+0x24b2: c5 d1 15 71 42 vunpckhpd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x24b7: c5 f5 15 d0 vunpckhpd %ymm0,%ymm1,%ymm2 + libdis_test+0x24bb: c5 e5 15 23 vunpckhpd (%ebx),%ymm3,%ymm4 + libdis_test+0x24bf: c5 d5 15 72 42 vunpckhpd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x24c4: c5 f0 15 d0 vunpckhps %xmm0,%xmm1,%xmm2 + libdis_test+0x24c8: c5 e0 15 20 vunpckhps (%eax),%xmm3,%xmm4 + libdis_test+0x24cc: c5 d0 15 71 42 vunpckhps 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x24d1: c5 f4 15 d0 vunpckhps %ymm0,%ymm1,%ymm2 + libdis_test+0x24d5: c5 e4 15 23 vunpckhps (%ebx),%ymm3,%ymm4 + libdis_test+0x24d9: c5 d4 15 72 42 vunpckhps 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x24de: c5 f1 14 d0 vunpcklpd %xmm0,%xmm1,%xmm2 + libdis_test+0x24e2: c5 e1 14 20 vunpcklpd (%eax),%xmm3,%xmm4 + libdis_test+0x24e6: c5 d1 14 71 42 vunpcklpd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x24eb: c5 f5 14 d0 vunpcklpd %ymm0,%ymm1,%ymm2 + libdis_test+0x24ef: c5 e5 14 23 vunpcklpd (%ebx),%ymm3,%ymm4 + libdis_test+0x24f3: c5 d5 14 72 42 vunpcklpd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x24f8: c5 f0 14 d0 vunpcklps %xmm0,%xmm1,%xmm2 + libdis_test+0x24fc: c5 e0 14 20 vunpcklps (%eax),%xmm3,%xmm4 + libdis_test+0x2500: c5 d0 14 71 42 vunpcklps 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2505: c5 f4 14 d0 vunpcklps %ymm0,%ymm1,%ymm2 + libdis_test+0x2509: c5 e4 14 23 vunpcklps (%ebx),%ymm3,%ymm4 + libdis_test+0x250d: c5 d4 14 72 42 vunpcklps 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2512: c5 f1 57 d0 vxorpd %xmm0,%xmm1,%xmm2 + libdis_test+0x2516: c5 e1 57 20 vxorpd (%eax),%xmm3,%xmm4 + libdis_test+0x251a: c5 d1 57 71 42 vxorpd 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x251f: c5 f5 57 d0 vxorpd %ymm0,%ymm1,%ymm2 + libdis_test+0x2523: c5 e5 57 23 vxorpd (%ebx),%ymm3,%ymm4 + libdis_test+0x2527: c5 d5 57 72 42 vxorpd 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x252c: c5 f0 57 d0 vxorps %xmm0,%xmm1,%xmm2 + libdis_test+0x2530: c5 e0 57 20 vxorps (%eax),%xmm3,%xmm4 + libdis_test+0x2534: c5 d0 57 71 42 vxorps 0x42(%ecx),%xmm5,%xmm6 + libdis_test+0x2539: c5 f4 57 d0 vxorps %ymm0,%ymm1,%ymm2 + libdis_test+0x253d: c5 e4 57 23 vxorps (%ebx),%ymm3,%ymm4 + libdis_test+0x2541: c5 d4 57 72 42 vxorps 0x42(%edx),%ymm5,%ymm6 + libdis_test+0x2546: c5 fc 77 vzeroall + libdis_test+0x2549: c5 f8 77 vzeroupper diff --git a/usr/src/test/util-tests/tests/dis/i386/32.avx.s b/usr/src/test/util-tests/tests/dis/i386/32.avx.s index 5c1a523539..3fd6f0f4a1 100644 --- a/usr/src/test/util-tests/tests/dis/i386/32.avx.s +++ b/usr/src/test/util-tests/tests/dis/i386/32.avx.s @@ -1578,8 +1578,15 @@ libdis_test: vpextrd $0x23, %xmm1, (%ebx) vpextrd $0x23, %xmm2, 0x16(%ecx) - vpextrq $0x23, %xmm1, (%ebx) - vpextrq $0x23, %xmm2, 0x16(%ecx) + /* + * gas will assemble the following two instructions with an EVEX + * prefix. Force the VEX encoding with the correct W bit for the 3-byte + * VEX prefix. + * vpextrq $0x23, %xmm1, (%ebx) + * vpextrq $0x23, %xmm2, 0x16(%ecx) + */ + .byte 0xc4, 0xe3, 0xf9, 0x16, 0x0b, 0x23 + .byte 0xc4, 0xe3, 0xf9, 0x16, 0x51, 0x16, 0x23 vpextrw $0x23, %xmm0, %eax vpextrw $0x23, %xmm1, (%ebx) @@ -1639,8 +1646,15 @@ libdis_test: vpinsrd $0x20, (%ebx), %xmm2, %xmm3 vpinsrd $0x20, 0x10(%ebx), %xmm2, %xmm3 - vpinsrq $0x20, (%ebx), %xmm2, %xmm3 - vpinsrq $0x20, 0x10(%ebx), %xmm2, %xmm3 + /* + * gas will assemble the following two instructions with an EVEX + * prefix. Force the VEX encoding with the correct W bit for the 3-byte + * VEX prefix. + * vpinsrq $0x20, (%ebx), %xmm2, %xmm3 + * vpinsrq $0x20, 0x10(%ebx), %xmm2, %xmm3 + */ + .byte 0xc4, 0xe3, 0xc9, 0x22, 0x1b, 0x20 + .byte 0xc4, 0xe3, 0xc9, 0x22, 0x5b, 0x10, 0x20 vpinsrw $0x20, %eax, %xmm0, %xmm1 vpinsrw $0x20, (%ebx), %xmm2, %xmm3 diff --git a/usr/src/test/util-tests/tests/dis/i386/32.avx512.out b/usr/src/test/util-tests/tests/dis/i386/32.avx512.out new file mode 100644 index 0000000000..9eb45c38cd --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/i386/32.avx512.out @@ -0,0 +1,97 @@ + libdis_test: 62 03 bound %eax,(%ebx) + libdis_test+0x2: c5 f8 28 c8 vmovaps %xmm0,%xmm1 + libdis_test+0x6: c5 f8 28 da vmovaps %xmm2,%xmm3 + libdis_test+0xa: c5 f8 28 ec vmovaps %xmm4,%xmm5 + libdis_test+0xe: c5 f8 28 fe vmovaps %xmm6,%xmm7 + libdis_test+0x12: c5 fc 28 c8 vmovaps %ymm0,%ymm1 + libdis_test+0x16: c5 fc 28 da vmovaps %ymm2,%ymm3 + libdis_test+0x1a: c5 fc 28 ec vmovaps %ymm4,%ymm5 + libdis_test+0x1e: c5 fc 28 fe vmovaps %ymm6,%ymm7 + libdis_test+0x22: 62 f1 7c 48 28 c8 vmovaps %zmm0,%zmm1 + libdis_test+0x28: 62 f1 7c 48 28 da vmovaps %zmm2,%zmm3 + libdis_test+0x2e: 62 f1 7c 48 28 ec vmovaps %zmm4,%zmm5 + libdis_test+0x34: 62 f1 7c 48 28 fe vmovaps %zmm6,%zmm7 + libdis_test+0x3a: 62 f1 7c 48 29 a4 vmovaps %zmm4,0x8(%esp) + 24 08 00 00 00 + libdis_test+0x45: 62 f1 7c 48 28 9c vmovaps 0x8(%esp),%zmm3 + 24 08 00 00 00 + libdis_test+0x50: 62 f1 7c c9 28 f9 vmovaps %zmm1,%zmm7{%k1}{z} + libdis_test+0x56: 62 f1 7c 4f 28 e6 vmovaps %zmm6,%zmm4{%k7} + libdis_test+0x5c: 62 f1 7c c8 28 da vmovaps %zmm2,%zmm3{z} + libdis_test+0x62: 62 f1 7c 8b 28 d7 vmovaps %xmm7,%xmm2{%k3}{z} + libdis_test+0x68: 62 f1 7c 2d 28 d9 vmovaps %ymm1,%ymm3{%k5} + libdis_test+0x6e: 62 f1 fd 48 28 fa vmovapd %zmm2,%zmm7 + libdis_test+0x74: 62 f1 7c 48 11 bd vmovups %zmm7,0x20(%ebp) + 20 00 00 00 + libdis_test+0x7e: 62 f1 7c 48 10 bc vmovups 0x8(%esp),%zmm7 + 24 08 00 00 00 + libdis_test+0x89: 62 f1 7c c8 10 18 vmovups (%eax),%zmm3{z} + libdis_test+0x8f: 62 f1 fd 4a 10 0c vmovupd (%esp),%zmm1{%k2} + 24 + libdis_test+0x96: 62 f1 fd 48 11 34 vmovupd %zmm6,(%esp) + 24 + libdis_test+0x9d: 62 f1 7c 48 29 2c vmovaps %zmm5,(%esp) + 24 + libdis_test+0xa4: 62 f1 7c 48 29 ac vmovaps %zmm5,0x20(%esp) + 24 20 00 00 00 + libdis_test+0xaf: 62 f1 7c 48 29 64 vmovaps %zmm4,0x40(%esp) + 24 01 + libdis_test+0xb7: 62 f1 7c 48 29 a4 vmovaps %zmm4,0x60(%esp) + 24 60 00 00 00 + libdis_test+0xc2: 62 f1 7c 48 29 64 vmovaps %zmm4,0x80(%esp) + 24 02 + libdis_test+0xca: 62 f1 7c 48 29 64 vmovaps %zmm4,-0x80(%esp) + 24 fe + libdis_test+0xd2: 62 f1 7c 48 29 a4 vmovaps %zmm4,-0x20(%esp) + 24 e0 ff ff ff + libdis_test+0xdd: 62 f1 7c 48 28 2c vmovaps (%esp),%zmm5 + 24 + libdis_test+0xe4: 62 f1 7c 48 28 ac vmovaps 0x20(%esp),%zmm5 + 24 20 00 00 00 + libdis_test+0xef: 62 f1 7c 48 28 6c vmovaps 0x40(%esp),%zmm5 + 24 01 + libdis_test+0xf7: 62 f1 7c 48 28 ac vmovaps 0x60(%esp),%zmm5 + 24 60 00 00 00 + libdis_test+0x102: 62 f1 7c 48 28 6c vmovaps 0x80(%esp),%zmm5 + 24 02 + libdis_test+0x10a: 62 f1 7c 48 28 6c vmovaps -0x80(%esp),%zmm5 + 24 fe + libdis_test+0x112: 62 f1 7c 48 28 ac vmovaps -0x20(%esp),%zmm5 + 24 e0 ff ff ff + libdis_test+0x11d: 62 f1 7d 48 7f 74 vmovdqa32 %zmm6,0x100(%esp) + 24 04 + libdis_test+0x125: 62 f1 7d 28 7f 74 vmovdqa32 %ymm6,0x100(%esp) + 24 08 + libdis_test+0x12d: 62 f1 7d 08 7f 74 vmovdqa32 %xmm6,0x100(%esp) + 24 10 + libdis_test+0x135: 62 f1 7d 48 6f 30 vmovdqa32 (%eax),%zmm6 + libdis_test+0x13b: 62 f1 7d 28 6f 30 vmovdqa32 (%eax),%ymm6 + libdis_test+0x141: 62 f1 7d 08 6f 30 vmovdqa32 (%eax),%xmm6 + libdis_test+0x147: 62 f1 fd 48 7f 74 vmovdqa64 %zmm6,0x100(%esp) + 24 04 + libdis_test+0x14f: 62 f1 fd 28 7f 74 vmovdqa64 %ymm6,0x100(%esp) + 24 08 + libdis_test+0x157: 62 f1 fd 08 7f 74 vmovdqa64 %xmm6,0x100(%esp) + 24 10 + libdis_test+0x15f: 62 f1 fd 48 6f 74 vmovdqa64 0x800(%esp),%zmm6 + 24 20 + libdis_test+0x167: 62 f1 fd 28 6f 74 vmovdqa64 0x800(%esp),%ymm6 + 24 40 + libdis_test+0x16f: 62 f1 fd 08 6f b4 vmovdqa64 0x800(%esp),%xmm6 + 24 00 08 00 00 + libdis_test+0x17a: 62 f1 7f 48 7f 04 vmovdqu8 %zmm0,(%esp) + 24 + libdis_test+0x181: 62 f1 ff 48 7f 04 vmovdqu16 %zmm0,(%esp) + 24 + libdis_test+0x188: 62 f1 7e 48 7f 04 vmovdqu32 %zmm0,(%esp) + 24 + libdis_test+0x18f: 62 f1 fe 48 7f 04 vmovdqu64 %zmm0,(%esp) + 24 + libdis_test+0x196: 62 f1 7f 48 6f 04 vmovdqu8 (%esp),%zmm0 + 24 + libdis_test+0x19d: 62 f1 ff 48 6f 04 vmovdqu16 (%esp),%zmm0 + 24 + libdis_test+0x1a4: 62 f1 7e 48 6f 04 vmovdqu32 (%esp),%zmm0 + 24 + libdis_test+0x1ab: 62 f1 fe 48 6f 04 vmovdqu64 (%esp),%zmm0 + 24 diff --git a/usr/src/test/util-tests/tests/dis/i386/32.avx512.s b/usr/src/test/util-tests/tests/dis/i386/32.avx512.s new file mode 100755 index 0000000000..adcdae36da --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/i386/32.avx512.s @@ -0,0 +1,100 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2017 Joyent, Inc. + */ + +/* + * Basic test for AVX512 mov instructions + */ + +.text +.align 16 +.globl libdis_test +.type libdis_test, @function +libdis_test: + /* bound is not AVX512, but shares the 0x62 opcode on 32-bit. */ + bound %eax, (%ebx) + + vmovaps %xmm0, %xmm1 + vmovaps %xmm2, %xmm3 + vmovaps %xmm4, %xmm5 + vmovaps %xmm6, %xmm7 + + vmovaps %ymm0, %ymm1 + vmovaps %ymm2, %ymm3 + vmovaps %ymm4, %ymm5 + vmovaps %ymm6, %ymm7 + + vmovaps %zmm0, %zmm1 + vmovaps %zmm2, %zmm3 + vmovaps %zmm4, %zmm5 + vmovaps %zmm6, %zmm7 + + vmovaps %zmm4, 0x8(%esp) + vmovaps 0x8(%esp), %zmm3 + vmovaps %zmm1, %zmm7{%k1}{z} + vmovaps %zmm6, %zmm4{%k7} + vmovaps %zmm2, %zmm3{z} + + vmovaps %xmm7, %xmm2{%k3}{z} + vmovaps %ymm1, %ymm3{%k5} + + vmovapd %zmm2, %zmm7 + + vmovups %zmm7, 0x20(%ebp) + vmovups 0x8(%esp), %zmm7 + vmovups (%eax), %zmm3{z} + + vmovupd (%esp), %zmm1{%k2} + vmovupd %zmm6, (%esp) + + /* Test offset handling for both disp8*N and full. */ + vmovaps %zmm5, (%esp) + vmovaps %zmm5, 0x20(%esp) + vmovaps %zmm4, 0x40(%esp) + vmovaps %zmm4, 0x60(%esp) + vmovaps %zmm4, 0x80(%esp) + vmovaps %zmm4, -0x80(%esp) + vmovaps %zmm4, -0x20(%esp) + + vmovaps (%esp), %zmm5 + vmovaps 0x20(%esp), %zmm5 + vmovaps 0x40(%esp), %zmm5 + vmovaps 0x60(%esp), %zmm5 + vmovaps 0x80(%esp), %zmm5 + vmovaps -0x80(%esp), %zmm5 + vmovaps -0x20(%esp), %zmm5 + + vmovdqa32 %zmm6, 0x100(%esp) + vmovdqa32 %ymm6, 0x100(%esp) + vmovdqa32 %xmm6, 0x100(%esp) + vmovdqa32 (%eax), %zmm6 + vmovdqa32 (%eax), %ymm6 + vmovdqa32 (%eax), %xmm6 + + vmovdqa64 %zmm6, 0x100(%esp) + vmovdqa64 %ymm6, 0x100(%esp) + vmovdqa64 %xmm6, 0x100(%esp) + vmovdqa64 0x800(%esp), %zmm6 + vmovdqa64 0x800(%esp), %ymm6 + vmovdqa64 0x800(%esp), %xmm6 + + vmovdqu8 %zmm0, (%esp) + vmovdqu16 %zmm0, (%esp) + vmovdqu32 %zmm0, (%esp) + vmovdqu64 %zmm0, (%esp) + vmovdqu8 (%esp), %zmm0 + vmovdqu16 (%esp), %zmm0 + vmovdqu32 (%esp), %zmm0 + vmovdqu64 (%esp), %zmm0 +.size libdis_test, [.-libdis_test] diff --git a/usr/src/test/util-tests/tests/dis/i386/64.avx512.out b/usr/src/test/util-tests/tests/dis/i386/64.avx512.out new file mode 100644 index 0000000000..b4a325086b --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/i386/64.avx512.out @@ -0,0 +1,162 @@ + libdis_test: c5 f8 28 c8 vmovaps %xmm0,%xmm1 + libdis_test+0x4: c5 f8 28 da vmovaps %xmm2,%xmm3 + libdis_test+0x8: c5 f8 28 ec vmovaps %xmm4,%xmm5 + libdis_test+0xc: c5 f8 28 fe vmovaps %xmm6,%xmm7 + libdis_test+0x10: c4 41 78 28 c8 vmovaps %xmm8,%xmm9 + libdis_test+0x15: c4 41 78 28 da vmovaps %xmm10,%xmm11 + libdis_test+0x1a: c4 41 78 28 ec vmovaps %xmm12,%xmm13 + libdis_test+0x1f: c4 41 78 28 fe vmovaps %xmm14,%xmm15 + libdis_test+0x24: 62 a1 7c 08 28 c8 vmovaps %xmm16,%xmm17 + libdis_test+0x2a: 62 a1 7c 08 28 da vmovaps %xmm18,%xmm19 + libdis_test+0x30: 62 a1 7c 08 28 ec vmovaps %xmm20,%xmm21 + libdis_test+0x36: 62 a1 7c 08 28 fe vmovaps %xmm22,%xmm23 + libdis_test+0x3c: 62 01 7c 08 28 c8 vmovaps %xmm24,%xmm25 + libdis_test+0x42: 62 01 7c 08 28 da vmovaps %xmm26,%xmm27 + libdis_test+0x48: 62 01 7c 08 28 ec vmovaps %xmm28,%xmm29 + libdis_test+0x4e: 62 01 7c 08 28 fe vmovaps %xmm30,%xmm31 + libdis_test+0x54: c5 fc 28 c8 vmovaps %ymm0,%ymm1 + libdis_test+0x58: c5 fc 28 da vmovaps %ymm2,%ymm3 + libdis_test+0x5c: c5 fc 28 ec vmovaps %ymm4,%ymm5 + libdis_test+0x60: c5 fc 28 fe vmovaps %ymm6,%ymm7 + libdis_test+0x64: c4 41 7c 28 c8 vmovaps %ymm8,%ymm9 + libdis_test+0x69: c4 41 7c 28 da vmovaps %ymm10,%ymm11 + libdis_test+0x6e: c4 41 7c 28 ec vmovaps %ymm12,%ymm13 + libdis_test+0x73: c4 41 7c 28 fe vmovaps %ymm14,%ymm15 + libdis_test+0x78: 62 a1 7c 28 28 c8 vmovaps %ymm16,%ymm17 + libdis_test+0x7e: 62 a1 7c 28 28 da vmovaps %ymm18,%ymm19 + libdis_test+0x84: 62 a1 7c 28 28 ec vmovaps %ymm20,%ymm21 + libdis_test+0x8a: 62 a1 7c 28 28 fe vmovaps %ymm22,%ymm23 + libdis_test+0x90: 62 01 7c 28 28 c8 vmovaps %ymm24,%ymm25 + libdis_test+0x96: 62 01 7c 28 28 da vmovaps %ymm26,%ymm27 + libdis_test+0x9c: 62 01 7c 28 28 ec vmovaps %ymm28,%ymm29 + libdis_test+0xa2: 62 01 7c 28 28 fe vmovaps %ymm30,%ymm31 + libdis_test+0xa8: 62 f1 7c 48 28 c8 vmovaps %zmm0,%zmm1 + libdis_test+0xae: 62 f1 7c 48 28 da vmovaps %zmm2,%zmm3 + libdis_test+0xb4: 62 f1 7c 48 28 ec vmovaps %zmm4,%zmm5 + libdis_test+0xba: 62 f1 7c 48 28 fe vmovaps %zmm6,%zmm7 + libdis_test+0xc0: 62 51 7c 48 28 c8 vmovaps %zmm8,%zmm9 + libdis_test+0xc6: 62 51 7c 48 28 da vmovaps %zmm10,%zmm11 + libdis_test+0xcc: 62 51 7c 48 28 ec vmovaps %zmm12,%zmm13 + libdis_test+0xd2: 62 51 7c 48 28 fe vmovaps %zmm14,%zmm15 + libdis_test+0xd8: 62 a1 7c 48 28 c8 vmovaps %zmm16,%zmm17 + libdis_test+0xde: 62 a1 7c 48 28 da vmovaps %zmm18,%zmm19 + libdis_test+0xe4: 62 a1 7c 48 28 ec vmovaps %zmm20,%zmm21 + libdis_test+0xea: 62 a1 7c 48 28 fe vmovaps %zmm22,%zmm23 + libdis_test+0xf0: 62 01 7c 48 28 c8 vmovaps %zmm24,%zmm25 + libdis_test+0xf6: 62 01 7c 48 28 da vmovaps %zmm26,%zmm27 + libdis_test+0xfc: 62 01 7c 48 28 ec vmovaps %zmm28,%zmm29 + libdis_test+0x102: 62 01 7c 48 28 fe vmovaps %zmm30,%zmm31 + libdis_test+0x108: 62 61 7c 48 29 84 vmovaps %zmm24,0x8(%rsp) + 24 08 00 00 00 + libdis_test+0x113: 62 61 7c 48 28 bc vmovaps 0x8(%rsp),%zmm31 + 24 08 00 00 00 + libdis_test+0x11e: 62 c1 7c c9 28 cd vmovaps %zmm13,%zmm17{%k1}{z} + libdis_test+0x124: 62 21 7c 4f 28 c0 vmovaps %zmm16,%zmm24{%k7} + libdis_test+0x12a: 62 01 7c c8 28 ec vmovaps %zmm28,%zmm29{z} + libdis_test+0x130: 62 21 7c 08 28 c8 vmovaps %xmm16,%xmm25 + libdis_test+0x136: 62 e1 7c 8b 28 e7 vmovaps %xmm7,%xmm20{%k3}{z} + libdis_test+0x13c: 62 e1 7c 28 28 c1 vmovaps %ymm1,%ymm16 + libdis_test+0x142: 62 21 7c 2d 28 f3 vmovaps %ymm19,%ymm30{%k5} + libdis_test+0x148: 62 f1 fd 48 28 fa vmovapd %zmm2,%zmm7 + libdis_test+0x14e: 62 21 fd 08 28 c8 vmovapd %xmm16,%xmm25 + libdis_test+0x154: 62 21 fd 28 28 e8 vmovapd %ymm16,%ymm29 + libdis_test+0x15a: 62 f1 7c 48 11 bd vmovups %zmm7,0x20(%rbp) + 20 00 00 00 + libdis_test+0x164: 62 e1 7c 48 10 8c vmovups 0x8(%rsp),%zmm17 + 24 08 00 00 00 + libdis_test+0x16f: 62 e1 7c c8 10 38 vmovups (%rax),%zmm23{z} + libdis_test+0x175: 62 21 7c 08 10 c8 vmovups %xmm16,%xmm25 + libdis_test+0x17b: 62 21 7c 28 10 e8 vmovups %ymm16,%ymm29 + libdis_test+0x181: 62 41 fd 4a 10 3a vmovupd (%r10),%zmm31{%k2} + libdis_test+0x187: 62 c1 fd 48 11 03 vmovupd %zmm16,(%r11) + libdis_test+0x18d: 62 21 fd 08 10 c8 vmovupd %xmm16,%xmm25 + libdis_test+0x193: 62 21 fd 28 10 e8 vmovupd %ymm16,%ymm29 + libdis_test+0x199: 62 61 7c 48 29 0c vmovaps %zmm25,(%rsp) + 24 + libdis_test+0x1a0: 62 61 7c 48 29 8c vmovaps %zmm25,0x20(%rsp) + 24 20 00 00 00 + libdis_test+0x1ab: 62 61 7c 48 29 44 vmovaps %zmm24,0x40(%rsp) + 24 01 + libdis_test+0x1b3: 62 61 7c 48 29 84 vmovaps %zmm24,0x60(%rsp) + 24 60 00 00 00 + libdis_test+0x1be: 62 61 7c 48 29 44 vmovaps %zmm24,0x80(%rsp) + 24 02 + libdis_test+0x1c6: 62 61 7c 48 29 44 vmovaps %zmm24,-0x80(%rsp) + 24 fe + libdis_test+0x1ce: 62 61 7c 48 29 84 vmovaps %zmm24,-0x20(%rsp) + 24 e0 ff ff ff + libdis_test+0x1d9: 62 61 7c 28 29 84 vmovaps %ymm24,0x10(%rsp) + 24 10 00 00 00 + libdis_test+0x1e4: 62 61 7c 28 29 44 vmovaps %ymm24,0x20(%rsp) + 24 01 + libdis_test+0x1ec: 62 61 7c 28 29 44 vmovaps %ymm24,0x40(%rsp) + 24 02 + libdis_test+0x1f4: 62 61 7c 08 29 84 vmovaps %xmm24,0x8(%rsp) + 24 08 00 00 00 + libdis_test+0x1ff: 62 61 7c 08 29 44 vmovaps %xmm24,0x10(%rsp) + 24 01 + libdis_test+0x207: 62 61 7c 08 29 44 vmovaps %xmm24,0x20(%rsp) + 24 02 + libdis_test+0x20f: 62 61 7c 48 28 0c vmovaps (%rsp),%zmm25 + 24 + libdis_test+0x216: 62 61 7c 48 28 8c vmovaps 0x20(%rsp),%zmm25 + 24 20 00 00 00 + libdis_test+0x221: 62 61 7c 48 28 4c vmovaps 0x40(%rsp),%zmm25 + 24 01 + libdis_test+0x229: 62 61 7c 48 28 8c vmovaps 0x60(%rsp),%zmm25 + 24 60 00 00 00 + libdis_test+0x234: 62 61 7c 48 28 4c vmovaps 0x80(%rsp),%zmm25 + 24 02 + libdis_test+0x23c: 62 61 7c 48 28 4c vmovaps -0x80(%rsp),%zmm25 + 24 fe + libdis_test+0x244: 62 61 7c 48 28 8c vmovaps -0x20(%rsp),%zmm25 + 24 e0 ff ff ff + libdis_test+0x24f: 62 61 7c 28 28 8c vmovaps 0x10(%rsp),%ymm25 + 24 10 00 00 00 + libdis_test+0x25a: 62 61 7c 28 28 4c vmovaps 0x20(%rsp),%ymm25 + 24 01 + libdis_test+0x262: 62 61 7c 28 28 4c vmovaps 0x40(%rsp),%ymm25 + 24 02 + libdis_test+0x26a: 62 61 7c 08 28 8c vmovaps 0x8(%rsp),%xmm25 + 24 08 00 00 00 + libdis_test+0x275: 62 61 7c 08 28 4c vmovaps 0x10(%rsp),%xmm25 + 24 01 + libdis_test+0x27d: 62 61 7c 08 28 4c vmovaps 0x20(%rsp),%xmm25 + 24 02 + libdis_test+0x285: 62 f1 7d 48 7f 74 vmovdqa32 %zmm6,0x100(%rsp) + 24 04 + libdis_test+0x28d: 62 61 7d 28 7f 54 vmovdqa32 %ymm26,0x100(%rsp) + 24 08 + libdis_test+0x295: 62 e1 7d 08 7f 44 vmovdqa32 %xmm16,0x100(%rsp) + 24 10 + libdis_test+0x29d: 62 f1 7d 48 6f 31 vmovdqa32 (%rcx),%zmm6 + libdis_test+0x2a3: 62 61 7d 28 6f 11 vmovdqa32 (%rcx),%ymm26 + libdis_test+0x2a9: 62 e1 7d 08 6f 01 vmovdqa32 (%rcx),%xmm16 + libdis_test+0x2af: 62 e1 fd 48 7f 44 vmovdqa64 %zmm16,0x100(%rsp) + 24 04 + libdis_test+0x2b7: 62 61 fd 28 7f 54 vmovdqa64 %ymm26,0x100(%rsp) + 24 08 + libdis_test+0x2bf: 62 e1 fd 08 7f 44 vmovdqa64 %xmm16,0x100(%rsp) + 24 10 + libdis_test+0x2c7: 62 e1 fd 48 6f 44 vmovdqa64 0x800(%rsp),%zmm16 + 24 20 + libdis_test+0x2cf: 62 61 fd 28 6f 54 vmovdqa64 0x800(%rsp),%ymm26 + 24 40 + libdis_test+0x2d7: 62 e1 fd 08 6f 84 vmovdqa64 0x800(%rsp),%xmm16 + 24 00 08 00 00 + libdis_test+0x2e2: 62 e1 7f 48 7f 24 vmovdqu8 %zmm20,(%rsp) + 24 + libdis_test+0x2e9: 62 e1 ff 48 7f 24 vmovdqu16 %zmm20,(%rsp) + 24 + libdis_test+0x2f0: 62 e1 7e 48 7f 24 vmovdqu32 %zmm20,(%rsp) + 24 + libdis_test+0x2f7: 62 e1 fe 48 7f 24 vmovdqu64 %zmm20,(%rsp) + 24 + libdis_test+0x2fe: 62 e1 7f 48 6f 24 vmovdqu8 (%rsp),%zmm20 + 24 + libdis_test+0x305: 62 e1 ff 48 6f 24 vmovdqu16 (%rsp),%zmm20 + 24 + libdis_test+0x30c: 62 e1 7e 48 6f 24 vmovdqu32 (%rsp),%zmm20 + 24 + libdis_test+0x313: 62 e1 fe 48 6f 24 vmovdqu64 (%rsp),%zmm20 + 24 diff --git a/usr/src/test/util-tests/tests/dis/i386/64.avx512.s b/usr/src/test/util-tests/tests/dis/i386/64.avx512.s new file mode 100755 index 0000000000..f038534dbf --- /dev/null +++ b/usr/src/test/util-tests/tests/dis/i386/64.avx512.s @@ -0,0 +1,157 @@ +/* + * This file and its contents are supplied under the terms of the + * Common Development and Distribution License ("CDDL"), version 1.0. + * You may only use this file in accordance with the terms of version + * 1.0 of the CDDL. + * + * A full copy of the text of the CDDL should have accompanied this + * source. A copy of the CDDL is also available via the Internet at + * http://www.illumos.org/license/CDDL. + */ + +/* + * Copyright 2017 Joyent, Inc. + */ + +/* + * Basic test for AVX512 mov instructions + */ + +.text +.align 16 +.globl libdis_test +.type libdis_test, @function +libdis_test: + vmovaps %xmm0, %xmm1 + vmovaps %xmm2, %xmm3 + vmovaps %xmm4, %xmm5 + vmovaps %xmm6, %xmm7 + vmovaps %xmm8, %xmm9 + vmovaps %xmm10, %xmm11 + vmovaps %xmm12, %xmm13 + vmovaps %xmm14, %xmm15 + vmovaps %xmm16, %xmm17 + vmovaps %xmm18, %xmm19 + vmovaps %xmm20, %xmm21 + vmovaps %xmm22, %xmm23 + vmovaps %xmm24, %xmm25 + vmovaps %xmm26, %xmm27 + vmovaps %xmm28, %xmm29 + vmovaps %xmm30, %xmm31 + + vmovaps %ymm0, %ymm1 + vmovaps %ymm2, %ymm3 + vmovaps %ymm4, %ymm5 + vmovaps %ymm6, %ymm7 + vmovaps %ymm8, %ymm9 + vmovaps %ymm10, %ymm11 + vmovaps %ymm12, %ymm13 + vmovaps %ymm14, %ymm15 + vmovaps %ymm16, %ymm17 + vmovaps %ymm18, %ymm19 + vmovaps %ymm20, %ymm21 + vmovaps %ymm22, %ymm23 + vmovaps %ymm24, %ymm25 + vmovaps %ymm26, %ymm27 + vmovaps %ymm28, %ymm29 + vmovaps %ymm30, %ymm31 + + vmovaps %zmm0, %zmm1 + vmovaps %zmm2, %zmm3 + vmovaps %zmm4, %zmm5 + vmovaps %zmm6, %zmm7 + vmovaps %zmm8, %zmm9 + vmovaps %zmm10, %zmm11 + vmovaps %zmm12, %zmm13 + vmovaps %zmm14, %zmm15 + vmovaps %zmm16, %zmm17 + vmovaps %zmm18, %zmm19 + vmovaps %zmm20, %zmm21 + vmovaps %zmm22, %zmm23 + vmovaps %zmm24, %zmm25 + vmovaps %zmm26, %zmm27 + vmovaps %zmm28, %zmm29 + vmovaps %zmm30, %zmm31 + + vmovaps %zmm24, 0x8(%rsp) + vmovaps 0x8(%rsp), %zmm31 + vmovaps %zmm13, %zmm17{%k1}{z} + vmovaps %zmm16, %zmm24{%k7} + vmovaps %zmm28, %zmm29{z} + + vmovaps %xmm16, %xmm25 + vmovaps %xmm7, %xmm20{%k3}{z} + vmovaps %ymm1, %ymm16 + vmovaps %ymm19, %ymm30{%k5} + + vmovapd %zmm2, %zmm7 + vmovapd %xmm16, %xmm25 + vmovapd %ymm16, %ymm29 + + vmovups %zmm7, 0x20(%rbp) + vmovups 0x8(%rsp), %zmm17 + vmovups (%rax), %zmm23{z} + vmovups %xmm16, %xmm25 + vmovups %ymm16, %ymm29 + + vmovupd (%r10), %zmm31{%k2} + vmovupd %zmm16, (%r11) + vmovupd %xmm16, %xmm25 + vmovupd %ymm16, %ymm29 + + /* Test offset handling for both disp8*N and full. */ + vmovaps %zmm25, (%rsp) + vmovaps %zmm25, 0x20(%rsp) + vmovaps %zmm24, 0x40(%rsp) + vmovaps %zmm24, 0x60(%rsp) + vmovaps %zmm24, 0x80(%rsp) + vmovaps %zmm24, -0x80(%rsp) + vmovaps %zmm24, -0x20(%rsp) + + vmovaps %ymm24, 0x10(%rsp) + vmovaps %ymm24, 0x20(%rsp) + vmovaps %ymm24, 0x40(%rsp) + + vmovaps %xmm24, 0x8(%rsp) + vmovaps %xmm24, 0x10(%rsp) + vmovaps %xmm24, 0x20(%rsp) + + vmovaps (%rsp), %zmm25 + vmovaps 0x20(%rsp), %zmm25 + vmovaps 0x40(%rsp), %zmm25 + vmovaps 0x60(%rsp), %zmm25 + vmovaps 0x80(%rsp), %zmm25 + vmovaps -0x80(%rsp), %zmm25 + vmovaps -0x20(%rsp), %zmm25 + + vmovaps 0x10(%rsp), %ymm25 + vmovaps 0x20(%rsp), %ymm25 + vmovaps 0x40(%rsp), %ymm25 + + vmovaps 0x8(%rsp), %xmm25 + vmovaps 0x10(%rsp), %xmm25 + vmovaps 0x20(%rsp), %xmm25 + + vmovdqa32 %zmm6, 0x100(%rsp) + vmovdqa32 %ymm26, 0x100(%rsp) + vmovdqa32 %xmm16, 0x100(%rsp) + vmovdqa32 (%rcx), %zmm6 + vmovdqa32 (%rcx), %ymm26 + vmovdqa32 (%rcx), %xmm16 + + vmovdqa64 %zmm16, 0x100(%rsp) + vmovdqa64 %ymm26, 0x100(%rsp) + vmovdqa64 %xmm16, 0x100(%rsp) + vmovdqa64 0x800(%rsp), %zmm16 + vmovdqa64 0x800(%rsp), %ymm26 + vmovdqa64 0x800(%rsp), %xmm16 + + vmovdqu8 %zmm20, (%rsp) + vmovdqu16 %zmm20, (%rsp) + vmovdqu32 %zmm20, (%rsp) + vmovdqu64 %zmm20, (%rsp) + vmovdqu8 (%rsp), %zmm20 + vmovdqu16 (%rsp), %zmm20 + vmovdqu32 (%rsp), %zmm20 + vmovdqu64 (%rsp), %zmm20 +.size libdis_test, [.-libdis_test] -- 2.11.4.GIT