4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
23 * Copyright (c) 1992, 2010, Oracle and/or its affiliates. All rights reserved.
26 * Copyright (c) 2010, Intel Corporation.
27 * All rights reserved.
30 * Copyright 2018 Joyent, Inc.
31 * Copyright 2013 Nexenta Systems, Inc. All rights reserved.
34 #include <sys/types.h>
35 #include <sys/thread.h>
36 #include <sys/cpuvar.h>
38 #include <sys/t_lock.h>
39 #include <sys/param.h>
42 #include <sys/class.h>
43 #include <sys/cmn_err.h>
44 #include <sys/debug.h>
46 #include <sys/asm_linkage.h>
47 #include <sys/x_call.h>
48 #include <sys/systm.h>
50 #include <sys/vtrace.h>
53 #include <vm/seg_kmem.h>
54 #include <vm/seg_kp.h>
55 #include <sys/segments.h>
57 #include <sys/stack.h>
58 #include <sys/smp_impldefs.h>
59 #include <sys/x86_archext.h>
60 #include <sys/machsystm.h>
61 #include <sys/traptrace.h>
62 #include <sys/clock.h>
63 #include <sys/cpc_impl.h>
66 #include <sys/dtrace.h>
67 #include <sys/archsystm.h>
69 #include <sys/reboot.h>
70 #include <sys/kdi_machimpl.h>
71 #include <vm/hat_i86.h>
72 #include <vm/vm_dep.h>
73 #include <sys/memnode.h>
74 #include <sys/pci_cfgspace.h>
75 #include <sys/mach_mmu.h>
76 #include <sys/sysmacros.h>
77 #include <sys/cpu_module.h>
78 #include <sys/ontrap.h>
80 struct cpu cpus
[1] __aligned(MMU_PAGESIZE
);
81 struct cpu
*cpu
[NCPU
] = {&cpus
[0]};
82 struct cpu
*cpu_free_list
;
83 cpu_core_t cpu_core
[NCPU
];
85 #define cpu_next_free cpu_prev
88 * Useful for disabling MP bring-up on a MP capable system.
93 * to be set by a PSM to indicate what cpus
94 * are sitting around on the system.
99 * This variable is used by the hat layer to decide whether or not
100 * critical sections are needed to prevent race conditions. For sun4m,
101 * this variable is set once enough MP initialization has been done in
102 * order to allow cross calls.
104 int flushes_require_xcalls
;
106 cpuset_t cpu_ready_set
; /* initialized in startup() */
108 static void mp_startup_boot(void);
109 static void mp_startup_hotplug(void);
111 static void cpu_sep_enable(void);
112 static void cpu_sep_disable(void);
113 static void cpu_asysc_enable(void);
114 static void cpu_asysc_disable(void);
117 * Init CPU info - get CPU type info for processor_info system call.
120 init_cpu_info(struct cpu
*cp
)
122 processor_info_t
*pi
= &cp
->cpu_type_info
;
125 * Get clock-frequency property for the CPU.
127 pi
->pi_clock
= cpu_freq
;
130 * Current frequency in Hz.
132 cp
->cpu_curr_clock
= cpu_freq_hz
;
135 * Supported frequencies.
137 if (cp
->cpu_supp_freqs
== NULL
) {
138 cpu_set_supp_freqs(cp
, NULL
);
141 (void) strcpy(pi
->pi_processor_type
, "i386");
143 (void) strcpy(pi
->pi_fputypes
, "i387 compatible");
145 cp
->cpu_idstr
= kmem_zalloc(CPU_IDSTRLEN
, KM_SLEEP
);
146 cp
->cpu_brandstr
= kmem_zalloc(CPU_IDSTRLEN
, KM_SLEEP
);
149 * If called for the BSP, cp is equal to current CPU.
150 * For non-BSPs, cpuid info of cp is not ready yet, so use cpuid info
151 * of current CPU as default values for cpu_idstr and cpu_brandstr.
152 * They will be corrected in mp_startup_common() after cpuid_pass1()
153 * has been invoked on target CPU.
155 (void) cpuid_getidstr(CPU
, cp
->cpu_idstr
, CPU_IDSTRLEN
);
156 (void) cpuid_getbrandstr(CPU
, cp
->cpu_brandstr
, CPU_IDSTRLEN
);
160 * Configure syscall support on this CPU.
164 init_cpu_syscall(struct cpu
*cp
)
168 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
169 is_x86_feature(x86_featureset
, X86FSET_ASYSC
)) {
173 * The syscall instruction imposes a certain ordering on
174 * segment selectors, so we double-check that ordering
177 CTASSERT(KDS_SEL
== KCS_SEL
+ 8);
178 CTASSERT(UDS_SEL
== U32CS_SEL
+ 8);
179 CTASSERT(UCS_SEL
== U32CS_SEL
+ 16);
182 * Turn syscall/sysret extensions on.
187 * Program the magic registers ..
190 ((uint64_t)(U32CS_SEL
<< 16 | KCS_SEL
)) << 32);
191 if (kpti_enable
== 1) {
193 (uint64_t)(uintptr_t)tr_sys_syscall
);
195 (uint64_t)(uintptr_t)tr_sys_syscall32
);
198 (uint64_t)(uintptr_t)sys_syscall
);
200 (uint64_t)(uintptr_t)sys_syscall32
);
204 * This list of flags is masked off the incoming
205 * %rfl when we enter the kernel.
207 flags
= PS_IE
| PS_T
;
208 if (is_x86_feature(x86_featureset
, X86FSET_SMAP
) == B_TRUE
)
210 wrmsr(MSR_AMD_SFMASK
, flags
);
214 * On 64-bit kernels on Nocona machines, the 32-bit syscall
215 * variant isn't available to 32-bit applications, but sysenter is.
217 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
218 is_x86_feature(x86_featureset
, X86FSET_SEP
)) {
221 * The sysenter instruction imposes a certain ordering on
222 * segment selectors, so we double-check that ordering
223 * here. See "sysenter" in Intel document 245471-012, "IA-32
224 * Intel Architecture Software Developer's Manual Volume 2:
225 * Instruction Set Reference"
227 CTASSERT(KDS_SEL
== KCS_SEL
+ 8);
229 CTASSERT(U32CS_SEL
== ((KCS_SEL
+ 16) | 3));
230 CTASSERT(UDS_SEL
== U32CS_SEL
+ 8);
235 * resume() sets this value to the base of the threads stack
236 * via a context handler.
238 wrmsr(MSR_INTC_SEP_ESP
, 0);
240 if (kpti_enable
== 1) {
241 wrmsr(MSR_INTC_SEP_EIP
,
242 (uint64_t)(uintptr_t)tr_sys_sysenter
);
244 wrmsr(MSR_INTC_SEP_EIP
,
245 (uint64_t)(uintptr_t)sys_sysenter
);
253 * Configure per-cpu ID GDT
256 init_cpu_id_gdt(struct cpu
*cp
)
258 /* Write cpu_id into limit field of GDT for usermode retrieval */
260 set_usegd(&cp
->cpu_gdt
[GDT_CPUID
], SDP_SHORT
, NULL
, cp
->cpu_id
,
261 SDT_MEMRODA
, SEL_UPL
, SDP_BYTES
, SDP_OP32
);
262 #elif defined(__i386)
263 set_usegd(&cp
->cpu_gdt
[GDT_CPUID
], NULL
, cp
->cpu_id
, SDT_MEMRODA
,
264 SEL_UPL
, SDP_BYTES
, SDP_OP32
);
269 * Multiprocessor initialization.
271 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the
272 * startup and idle threads for the specified CPU.
273 * Parameter boot is true for boot time operations and is false for CPU
277 mp_cpu_configure_common(int cpun
, boolean_t boot
)
283 extern int idle_cpu_prefer_mwait
;
284 extern void cpu_idle_mwait();
286 extern void cpu_idle();
289 trap_trace_ctl_t
*ttc
= &trap_trace_ctl
[cpun
];
292 ASSERT(MUTEX_HELD(&cpu_lock
));
293 ASSERT(cpun
< NCPU
&& cpu
[cpun
] == NULL
);
295 if (cpu_free_list
== NULL
) {
296 cp
= kmem_zalloc(sizeof (*cp
), KM_SLEEP
);
299 cpu_free_list
= cp
->cpu_next_free
;
302 cp
->cpu_m
.mcpu_istamp
= cpun
<< 16;
304 /* Create per CPU specific threads in the process p0. */
308 * Initialize the dispatcher first.
312 cpu_vm_data_init(cp
);
315 * Allocate and initialize the startup thread for this CPU.
316 * Interrupt and process switch stacks get allocated later
317 * when the CPU starts running.
319 tp
= thread_create(NULL
, 0, NULL
, NULL
, 0, procp
,
320 TS_STOPPED
, maxclsyspri
);
323 * Set state to TS_ONPROC since this thread will start running
324 * as soon as the CPU comes online.
326 * All the other fields of the thread structure are setup by
329 THREAD_ONPROC(tp
, cp
);
331 tp
->t_bound_cpu
= cp
;
332 tp
->t_affinitycnt
= 1;
334 tp
->t_disp_queue
= cp
->cpu_disp
;
337 * Setup thread to start in mp_startup_common.
340 tp
->t_sp
= (uintptr_t)(sp
- MINFRAME
);
342 tp
->t_sp
-= STACK_ENTRY_ALIGN
; /* fake a call */
345 * Setup thread start entry point for boot or hotplug.
348 tp
->t_pc
= (uintptr_t)mp_startup_boot
;
350 tp
->t_pc
= (uintptr_t)mp_startup_hotplug
;
357 cp
->cpu_dispthread
= tp
;
358 cp
->cpu_dispatch_pri
= DISP_PRIO(tp
);
361 * cpu_base_spl must be set explicitly here to prevent any blocking
362 * operations in mp_startup_common from causing the spl of the cpu
363 * to drop to 0 (allowing device interrupts before we're ready) in
365 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY.
366 * As an extra bit of security on DEBUG kernels, this is enforced with
367 * an assertion in mp_startup_common() -- before cpu_base_spl is set
368 * to its proper value.
370 cp
->cpu_base_spl
= ipltospl(LOCK_LEVEL
);
373 * Now, initialize per-CPU idle thread for this CPU.
375 tp
= thread_create(NULL
, PAGESIZE
, idle
, NULL
, 0, procp
, TS_ONPROC
, -1);
377 cp
->cpu_idle_thread
= tp
;
380 tp
->t_bound_cpu
= cp
;
381 tp
->t_affinitycnt
= 1;
383 tp
->t_disp_queue
= cp
->cpu_disp
;
386 * Bootstrap the CPU's PG data
388 pg_cpu_bootstrap(cp
);
391 * Perform CPC initialization on the new CPU.
396 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2
399 setup_vaddr_for_ppcopy(cp
);
402 * Allocate page for new GDT and initialize from current GDT.
404 ASSERT((sizeof (*cp
->cpu_gdt
) * NGDT
) <= PAGESIZE
);
405 cp
->cpu_gdt
= kmem_zalloc(PAGESIZE
, KM_SLEEP
);
406 bcopy(CPU
->cpu_gdt
, cp
->cpu_gdt
, (sizeof (*cp
->cpu_gdt
) * NGDT
));
412 set_usegd(&cp
->cpu_gdt
[GDT_GS
], cp
, sizeof (struct cpu
) -1, SDT_MEMRWA
,
417 * Allocate pages for the CPU LDT.
419 cp
->cpu_m
.mcpu_ldt
= kmem_zalloc(LDT_CPU_SIZE
, KM_SLEEP
);
420 cp
->cpu_m
.mcpu_ldt_len
= 0;
423 * Allocate a per-CPU IDT and initialize the new IDT to the currently
426 ASSERT((sizeof (*CPU
->cpu_idt
) * NIDT
) <= PAGESIZE
);
427 cp
->cpu_idt
= kmem_alloc(PAGESIZE
, KM_SLEEP
);
428 bcopy(CPU
->cpu_idt
, cp
->cpu_idt
, PAGESIZE
);
431 * alloc space for cpuid info
433 cpuid_alloc_space(cp
);
435 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) &&
436 idle_cpu_prefer_mwait
) {
437 VERIFY0(cpuid_mwait_alloc(cp
));
438 cp
->cpu_m
.mcpu_idle_cpu
= cpu_idle_mwait
;
440 cp
->cpu_m
.mcpu_idle_cpu
= cpu_idle
;
447 * alloc space for ucode_info
449 ucode_alloc_space(cp
);
455 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers
457 ttc
->ttc_first
= (uintptr_t)kmem_zalloc(trap_trace_bufsize
, KM_SLEEP
);
458 ttc
->ttc_next
= ttc
->ttc_first
;
459 ttc
->ttc_limit
= ttc
->ttc_first
+ trap_trace_bufsize
;
463 * Record that we have another CPU.
466 * Initialize the interrupt threads for this CPU
468 cpu_intr_alloc(cp
, NINTR_THREADS
);
470 cp
->cpu_flags
= CPU_OFFLINE
| CPU_QUIESCED
| CPU_POWEROFF
;
474 * Add CPU to list of available CPUs. It'll be on the active list
475 * after mp_startup_common().
483 * Undo what was done in mp_cpu_configure_common
486 mp_cpu_unconfigure_common(struct cpu
*cp
, int error
)
488 ASSERT(MUTEX_HELD(&cpu_lock
));
491 * Remove the CPU from the list of available CPUs.
493 cpu_del_unit(cp
->cpu_id
);
495 if (error
== ETIMEDOUT
) {
497 * The cpu was started, but never *seemed* to run any
498 * code in the kernel; it's probably off spinning in its
499 * own private world, though with potential references to
500 * our kmem-allocated IDTs and GDTs (for example).
502 * Worse still, it may actually wake up some time later,
503 * so rather than guess what it might or might not do, we
504 * leave the fundamental data structures intact.
511 * At this point, the only threads bound to this CPU should
512 * special per-cpu threads: it's idle thread, it's pause threads,
513 * and it's interrupt threads. Clean these up.
515 cpu_destroy_bound_threads(cp
);
516 cp
->cpu_idle_thread
= NULL
;
519 * Free the interrupt stack.
522 cp
->cpu_intr_stack
- (INTR_STACK_SIZE
- SA(MINFRAME
)));
523 cp
->cpu_intr_stack
= NULL
;
527 * Discard the trap trace buffer
530 trap_trace_ctl_t
*ttc
= &trap_trace_ctl
[cp
->cpu_id
];
532 kmem_free((void *)ttc
->ttc_first
, trap_trace_bufsize
);
533 ttc
->ttc_first
= (uintptr_t)NULL
;
539 ucode_free_space(cp
);
541 /* Free CPU ID string and brand string. */
543 kmem_free(cp
->cpu_idstr
, CPU_IDSTRLEN
);
544 cp
->cpu_idstr
= NULL
;
546 if (cp
->cpu_brandstr
) {
547 kmem_free(cp
->cpu_brandstr
, CPU_IDSTRLEN
);
548 cp
->cpu_brandstr
= NULL
;
551 if (cp
->cpu_m
.mcpu_mwait
!= NULL
) {
552 cpuid_mwait_free(cp
);
553 cp
->cpu_m
.mcpu_mwait
= NULL
;
555 cpuid_free_space(cp
);
557 if (cp
->cpu_idt
!= CPU
->cpu_idt
)
558 kmem_free(cp
->cpu_idt
, PAGESIZE
);
561 kmem_free(cp
->cpu_m
.mcpu_ldt
, LDT_CPU_SIZE
);
562 cp
->cpu_m
.mcpu_ldt
= NULL
;
563 cp
->cpu_m
.mcpu_ldt_len
= 0;
565 kmem_free(cp
->cpu_gdt
, PAGESIZE
);
568 if (cp
->cpu_supp_freqs
!= NULL
) {
569 size_t len
= strlen(cp
->cpu_supp_freqs
) + 1;
570 kmem_free(cp
->cpu_supp_freqs
, len
);
571 cp
->cpu_supp_freqs
= NULL
;
574 teardown_vaddr_for_ppcopy(cp
);
578 cp
->cpu_dispthread
= NULL
;
579 cp
->cpu_thread
= NULL
; /* discarded by cpu_destroy_bound_threads() */
581 cpu_vm_data_destroy(cp
);
587 bzero(cp
, sizeof (*cp
));
588 cp
->cpu_next_free
= cpu_free_list
;
593 * Apply workarounds for known errata, and warn about those that are absent.
595 * System vendors occasionally create configurations which contain different
596 * revisions of the CPUs that are almost but not exactly the same. At the
597 * time of writing, this meant that their clock rates were the same, their
598 * feature sets were the same, but the required workaround were -not-
599 * necessarily the same. So, this routine is invoked on -every- CPU soon
600 * after starting to make sure that the resulting system contains the most
601 * pessimal set of workarounds needed to cope with *any* of the CPUs in the
604 * workaround_errata is invoked early in mlsetup() for CPU 0, and in
605 * mp_startup_common() for all slave CPUs. Slaves process workaround_errata
606 * prior to acknowledging their readiness to the master, so this routine will
607 * never be executed by multiple CPUs in parallel, thus making updates to
610 * These workarounds are based on Rev 3.57 of the Revision Guide for
611 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005.
614 #if defined(OPTERON_ERRATUM_88)
615 int opteron_erratum_88
; /* if non-zero -> at least one cpu has it */
618 #if defined(OPTERON_ERRATUM_91)
619 int opteron_erratum_91
; /* if non-zero -> at least one cpu has it */
622 #if defined(OPTERON_ERRATUM_93)
623 int opteron_erratum_93
; /* if non-zero -> at least one cpu has it */
626 #if defined(OPTERON_ERRATUM_95)
627 int opteron_erratum_95
; /* if non-zero -> at least one cpu has it */
630 #if defined(OPTERON_ERRATUM_100)
631 int opteron_erratum_100
; /* if non-zero -> at least one cpu has it */
634 #if defined(OPTERON_ERRATUM_108)
635 int opteron_erratum_108
; /* if non-zero -> at least one cpu has it */
638 #if defined(OPTERON_ERRATUM_109)
639 int opteron_erratum_109
; /* if non-zero -> at least one cpu has it */
642 #if defined(OPTERON_ERRATUM_121)
643 int opteron_erratum_121
; /* if non-zero -> at least one cpu has it */
646 #if defined(OPTERON_ERRATUM_122)
647 int opteron_erratum_122
; /* if non-zero -> at least one cpu has it */
650 #if defined(OPTERON_ERRATUM_123)
651 int opteron_erratum_123
; /* if non-zero -> at least one cpu has it */
654 #if defined(OPTERON_ERRATUM_131)
655 int opteron_erratum_131
; /* if non-zero -> at least one cpu has it */
658 #if defined(OPTERON_WORKAROUND_6336786)
659 int opteron_workaround_6336786
; /* non-zero -> WA relevant and applied */
660 int opteron_workaround_6336786_UP
= 0; /* Not needed for UP */
663 #if defined(OPTERON_WORKAROUND_6323525)
664 int opteron_workaround_6323525
; /* if non-zero -> at least one cpu has it */
667 #if defined(OPTERON_ERRATUM_298)
668 int opteron_erratum_298
;
671 #if defined(OPTERON_ERRATUM_721)
672 int opteron_erratum_721
;
676 workaround_warning(cpu_t
*cp
, uint_t erratum
)
678 cmn_err(CE_WARN
, "cpu%d: no workaround for erratum %u",
679 cp
->cpu_id
, erratum
);
683 workaround_applied(uint_t erratum
)
685 if (erratum
> 1000000)
686 cmn_err(CE_CONT
, "?workaround applied for cpu issue #%d\n",
689 cmn_err(CE_CONT
, "?workaround applied for cpu erratum #%d\n",
694 msr_warning(cpu_t
*cp
, const char *rw
, uint_t msr
, int error
)
696 cmn_err(CE_WARN
, "cpu%d: couldn't %smsr 0x%x, error %d",
697 cp
->cpu_id
, rw
, msr
, error
);
701 * Determine the number of nodes in a Hammer / Greyhound / Griffin family
705 opteron_get_nnodes(void)
707 static uint_t nnodes
= 0;
714 * This routine uses a PCI config space based mechanism
715 * for retrieving the number of nodes in the system.
716 * Device 24, function 0, offset 0x60 as used here is not
717 * AMD processor architectural, and may not work on processor
718 * families other than those listed below.
720 * Callers of this routine must ensure that we're running on
721 * a processor which supports this mechanism.
722 * The assertion below is meant to catch calls on unsupported
725 family
= cpuid_getfamily(CPU
);
726 ASSERT(family
== 0xf || family
== 0x10 || family
== 0x11);
730 * Obtain the number of nodes in the system from
731 * bits [6:4] of the Node ID register on node 0.
733 * The actual node count is NodeID[6:4] + 1
735 * The Node ID register is accessed via function 0,
736 * offset 0x60. Node 0 is device 24.
738 nnodes
= ((pci_getl_func(0, 24, 0, 0x60) & 0x70) >> 4) + 1;
744 do_erratum_298(struct cpu
*cpu
)
746 static int osvwrc
= -3;
747 extern int osvw_opteron_erratum(cpu_t
*, uint_t
);
750 * L2 Eviction May Occur During Processor Operation To Set
751 * Accessed or Dirty Bit.
754 osvwrc
= osvw_opteron_erratum(cpu
, 298);
756 /* osvw return codes should be consistent for all cpus */
757 ASSERT(osvwrc
== osvw_opteron_erratum(cpu
, 298));
761 case 0: /* erratum is not present: do nothing */
763 case 1: /* erratum is present: BIOS workaround applied */
765 * check if workaround is actually in place and issue warning
768 if (((rdmsr(MSR_AMD_HWCR
) & AMD_HWCR_TLBCACHEDIS
) == 0) ||
769 ((rdmsr(MSR_AMD_BU_CFG
) & AMD_BU_CFG_E298
) == 0)) {
770 #if defined(OPTERON_ERRATUM_298)
771 opteron_erratum_298
++;
773 workaround_warning(cpu
, 298);
778 case -1: /* cannot determine via osvw: check cpuid */
779 if ((cpuid_opteron_erratum(cpu
, 298) > 0) &&
780 (((rdmsr(MSR_AMD_HWCR
) & AMD_HWCR_TLBCACHEDIS
) == 0) ||
781 ((rdmsr(MSR_AMD_BU_CFG
) & AMD_BU_CFG_E298
) == 0))) {
782 #if defined(OPTERON_ERRATUM_298)
783 opteron_erratum_298
++;
785 workaround_warning(cpu
, 298);
795 workaround_errata(struct cpu
*cpu
)
802 if (cpuid_opteron_erratum(cpu
, 88) > 0) {
804 * SWAPGS May Fail To Read Correct GS Base
806 #if defined(OPTERON_ERRATUM_88)
808 * The workaround is an mfence in the relevant assembler code
810 opteron_erratum_88
++;
812 workaround_warning(cpu
, 88);
817 if (cpuid_opteron_erratum(cpu
, 91) > 0) {
819 * Software Prefetches May Report A Page Fault
821 #if defined(OPTERON_ERRATUM_91)
825 opteron_erratum_91
++;
827 workaround_warning(cpu
, 91);
832 if (cpuid_opteron_erratum(cpu
, 93) > 0) {
834 * RSM Auto-Halt Restart Returns to Incorrect RIP
836 #if defined(OPTERON_ERRATUM_93)
840 opteron_erratum_93
++;
842 workaround_warning(cpu
, 93);
848 if (cpuid_opteron_erratum(cpu
, 95) > 0) {
850 * RET Instruction May Return to Incorrect EIP
852 #if defined(OPTERON_ERRATUM_95)
855 * Workaround this by ensuring that 32-bit user code and
856 * 64-bit kernel code never occupy the same address
859 if (_userlimit32
> 0xc0000000ul
)
860 *(uintptr_t *)&_userlimit32
= 0xc0000000ul
;
863 ASSERT((uint32_t)COREHEAP_BASE
== 0xc0000000u
);
864 opteron_erratum_95
++;
867 workaround_warning(cpu
, 95);
872 if (cpuid_opteron_erratum(cpu
, 100) > 0) {
874 * Compatibility Mode Branches Transfer to Illegal Address
876 #if defined(OPTERON_ERRATUM_100)
880 opteron_erratum_100
++;
882 workaround_warning(cpu
, 100);
888 if (cpuid_opteron_erratum(cpu
, 108) > 0) {
890 * CPUID Instruction May Return Incorrect Model Number In
893 #if defined(OPTERON_ERRATUM_108)
895 * (Our cpuid-handling code corrects the model number on
899 workaround_warning(cpu
, 108);
905 if (cpuid_opteron_erratum(cpu
, 109) > 0) do {
907 * Certain Reverse REP MOVS May Produce Unpredictable Behavior
909 #if defined(OPTERON_ERRATUM_109)
911 * The "workaround" is to print a warning to upgrade the BIOS
914 const uint_t msr
= MSR_AMD_PATCHLEVEL
;
917 if ((err
= checked_rdmsr(msr
, &value
)) != 0) {
918 msr_warning(cpu
, "rd", msr
, err
);
919 workaround_warning(cpu
, 109);
923 opteron_erratum_109
++;
925 workaround_warning(cpu
, 109);
928 /*CONSTANTCONDITION*/
932 if (cpuid_opteron_erratum(cpu
, 121) > 0) {
934 * Sequential Execution Across Non_Canonical Boundary Caused
937 #if defined(OPTERON_ERRATUM_121)
940 * Erratum 121 is only present in long (64 bit) mode.
941 * Workaround is to include the page immediately before the
942 * va hole to eliminate the possibility of system hangs due to
943 * sequential execution across the va hole boundary.
945 if (opteron_erratum_121
)
946 opteron_erratum_121
++;
949 hole_start
-= PAGESIZE
;
952 * hole_start not yet initialized by
953 * mmu_init. Initialize hole_start
954 * with value to be subtracted.
956 hole_start
= PAGESIZE
;
958 opteron_erratum_121
++;
962 workaround_warning(cpu
, 121);
968 if (cpuid_opteron_erratum(cpu
, 122) > 0) do {
970 * TLB Flush Filter May Cause Coherency Problem in
971 * Multiprocessor Systems
973 #if defined(OPTERON_ERRATUM_122)
975 const uint_t msr
= MSR_AMD_HWCR
;
979 * Erratum 122 is only present in MP configurations (multi-core
980 * or multi-processor).
983 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
985 if (!opteron_erratum_122
&& xpv_nr_phys_cpus() == 1)
988 if (!opteron_erratum_122
&& opteron_get_nnodes() == 1 &&
989 cpuid_get_ncpu_per_chip(cpu
) == 1)
992 /* disable TLB Flush Filter */
994 if ((error
= checked_rdmsr(msr
, &value
)) != 0) {
995 msr_warning(cpu
, "rd", msr
, error
);
996 workaround_warning(cpu
, 122);
999 value
|= (uint64_t)AMD_HWCR_FFDIS
;
1000 if ((error
= checked_wrmsr(msr
, value
)) != 0) {
1001 msr_warning(cpu
, "wr", msr
, error
);
1002 workaround_warning(cpu
, 122);
1006 opteron_erratum_122
++;
1008 workaround_warning(cpu
, 122);
1011 /*CONSTANTCONDITION*/
1015 if (cpuid_opteron_erratum(cpu
, 123) > 0) do {
1017 * Bypassed Reads May Cause Data Corruption of System Hang in
1018 * Dual Core Processors
1020 #if defined(OPTERON_ERRATUM_123)
1022 const uint_t msr
= MSR_AMD_PATCHLEVEL
;
1026 * Erratum 123 applies only to multi-core cpus.
1028 if (cpuid_get_ncpu_per_chip(cpu
) < 2)
1031 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
1035 * The "workaround" is to print a warning to upgrade the BIOS
1037 if ((err
= checked_rdmsr(msr
, &value
)) != 0) {
1038 msr_warning(cpu
, "rd", msr
, err
);
1039 workaround_warning(cpu
, 123);
1043 opteron_erratum_123
++;
1045 workaround_warning(cpu
, 123);
1049 /*CONSTANTCONDITION*/
1053 if (cpuid_opteron_erratum(cpu
, 131) > 0) do {
1055 * Multiprocessor Systems with Four or More Cores May Deadlock
1056 * Waiting for a Probe Response
1058 #if defined(OPTERON_ERRATUM_131)
1060 const uint_t msr
= MSR_AMD_NB_CFG
;
1061 const uint64_t wabits
=
1062 AMD_NB_CFG_SRQ_HEARTBEAT
| AMD_NB_CFG_SRQ_SPR
;
1066 * Erratum 131 applies to any system with four or more cores.
1068 if (opteron_erratum_131
)
1071 if (!DOMAIN_IS_INITDOMAIN(xen_info
))
1073 if (xpv_nr_phys_cpus() < 4)
1076 if (opteron_get_nnodes() * cpuid_get_ncpu_per_chip(cpu
) < 4)
1080 * Print a warning if neither of the workarounds for
1081 * erratum 131 is present.
1083 if ((error
= checked_rdmsr(msr
, &nbcfg
)) != 0) {
1084 msr_warning(cpu
, "rd", msr
, error
);
1085 workaround_warning(cpu
, 131);
1087 } else if ((nbcfg
& wabits
) == 0) {
1088 opteron_erratum_131
++;
1090 /* cannot have both workarounds set */
1091 ASSERT((nbcfg
& wabits
) != wabits
);
1094 workaround_warning(cpu
, 131);
1097 /*CONSTANTCONDITION*/
1101 * This isn't really an erratum, but for convenience the
1102 * detection/workaround code lives here and in cpuid_opteron_erratum.
1104 if (cpuid_opteron_erratum(cpu
, 6336786) > 0) {
1105 #if defined(OPTERON_WORKAROUND_6336786)
1107 * Disable C1-Clock ramping on multi-core/multi-processor
1108 * K8 platforms to guard against TSC drift.
1110 if (opteron_workaround_6336786
) {
1111 opteron_workaround_6336786
++;
1113 } else if ((DOMAIN_IS_INITDOMAIN(xen_info
) &&
1114 xpv_nr_phys_cpus() > 1) ||
1115 opteron_workaround_6336786_UP
) {
1117 * XXPV Hmm. We can't walk the Northbridges on
1118 * the hypervisor; so just complain and drive
1119 * on. This probably needs to be fixed in
1120 * the hypervisor itself.
1122 opteron_workaround_6336786
++;
1123 workaround_warning(cpu
, 6336786);
1125 } else if ((opteron_get_nnodes() *
1126 cpuid_get_ncpu_per_chip(cpu
) > 1) ||
1127 opteron_workaround_6336786_UP
) {
1129 uint_t node
, nnodes
;
1132 nnodes
= opteron_get_nnodes();
1133 for (node
= 0; node
< nnodes
; node
++) {
1135 * Clear PMM7[1:0] (function 3, offset 0x87)
1136 * Northbridge device is the node id + 24.
1138 data
= pci_getb_func(0, node
+ 24, 3, 0x87);
1140 pci_putb_func(0, node
+ 24, 3, 0x87, data
);
1142 opteron_workaround_6336786
++;
1146 workaround_warning(cpu
, 6336786);
1153 * Mutex primitives don't work as expected.
1155 if (cpuid_opteron_erratum(cpu
, 6323525) > 0) {
1156 #if defined(OPTERON_WORKAROUND_6323525)
1158 * This problem only occurs with 2 or more cores. If bit in
1159 * MSR_AMD_BU_CFG set, then not applicable. The workaround
1160 * is to patch the semaphone routines with the lfence
1161 * instruction to provide necessary load memory barrier with
1162 * possible subsequent read-modify-write ops.
1164 * It is too early in boot to call the patch routine so
1165 * set erratum variable to be done in startup_end().
1167 if (opteron_workaround_6323525
) {
1168 opteron_workaround_6323525
++;
1170 } else if (is_x86_feature(x86_featureset
, X86FSET_SSE2
)) {
1171 if (DOMAIN_IS_INITDOMAIN(xen_info
)) {
1173 * XXPV Use dom0_msr here when extended
1174 * operations are supported?
1176 if (xpv_nr_phys_cpus() > 1)
1177 opteron_workaround_6323525
++;
1180 * We have no way to tell how many physical
1181 * cpus there are, or even if this processor
1182 * has the problem, so enable the workaround
1183 * unconditionally (at some performance cost).
1185 opteron_workaround_6323525
++;
1188 } else if (is_x86_feature(x86_featureset
, X86FSET_SSE2
) &&
1189 ((opteron_get_nnodes() *
1190 cpuid_get_ncpu_per_chip(cpu
)) > 1)) {
1191 if ((xrdmsr(MSR_AMD_BU_CFG
) & (UINT64_C(1) << 33)) == 0)
1192 opteron_workaround_6323525
++;
1196 workaround_warning(cpu
, 6323525);
1201 missing
+= do_erratum_298(cpu
);
1203 if (cpuid_opteron_erratum(cpu
, 721) > 0) {
1204 #if defined(OPTERON_ERRATUM_721)
1207 if (!on_trap(&otd
, OT_DATA_ACCESS
))
1208 wrmsr(MSR_AMD_DE_CFG
,
1209 rdmsr(MSR_AMD_DE_CFG
) | AMD_DE_CFG_E721
);
1212 opteron_erratum_721
++;
1214 workaround_warning(cpu
, 721);
1223 workaround_errata_end()
1225 #if defined(OPTERON_ERRATUM_88)
1226 if (opteron_erratum_88
)
1227 workaround_applied(88);
1229 #if defined(OPTERON_ERRATUM_91)
1230 if (opteron_erratum_91
)
1231 workaround_applied(91);
1233 #if defined(OPTERON_ERRATUM_93)
1234 if (opteron_erratum_93
)
1235 workaround_applied(93);
1237 #if defined(OPTERON_ERRATUM_95)
1238 if (opteron_erratum_95
)
1239 workaround_applied(95);
1241 #if defined(OPTERON_ERRATUM_100)
1242 if (opteron_erratum_100
)
1243 workaround_applied(100);
1245 #if defined(OPTERON_ERRATUM_108)
1246 if (opteron_erratum_108
)
1247 workaround_applied(108);
1249 #if defined(OPTERON_ERRATUM_109)
1250 if (opteron_erratum_109
) {
1252 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1253 " processor\nerratum 109 was not detected; updating your"
1254 " system's BIOS to a version\ncontaining this"
1255 " microcode patch is HIGHLY recommended or erroneous"
1256 " system\noperation may occur.\n");
1259 #if defined(OPTERON_ERRATUM_121)
1260 if (opteron_erratum_121
)
1261 workaround_applied(121);
1263 #if defined(OPTERON_ERRATUM_122)
1264 if (opteron_erratum_122
)
1265 workaround_applied(122);
1267 #if defined(OPTERON_ERRATUM_123)
1268 if (opteron_erratum_123
) {
1270 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1271 " processor\nerratum 123 was not detected; updating your"
1272 " system's BIOS to a version\ncontaining this"
1273 " microcode patch is HIGHLY recommended or erroneous"
1274 " system\noperation may occur.\n");
1277 #if defined(OPTERON_ERRATUM_131)
1278 if (opteron_erratum_131
) {
1280 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)"
1281 " processor\nerratum 131 was not detected; updating your"
1282 " system's BIOS to a version\ncontaining this"
1283 " microcode patch is HIGHLY recommended or erroneous"
1284 " system\noperation may occur.\n");
1287 #if defined(OPTERON_WORKAROUND_6336786)
1288 if (opteron_workaround_6336786
)
1289 workaround_applied(6336786);
1291 #if defined(OPTERON_WORKAROUND_6323525)
1292 if (opteron_workaround_6323525
)
1293 workaround_applied(6323525);
1295 #if defined(OPTERON_ERRATUM_298)
1296 if (opteron_erratum_298
) {
1298 "BIOS microcode patch for AMD 64/Opteron(tm)"
1299 " processor\nerratum 298 was not detected; updating your"
1300 " system's BIOS to a version\ncontaining this"
1301 " microcode patch is HIGHLY recommended or erroneous"
1302 " system\noperation may occur.\n");
1305 #if defined(OPTERON_ERRATUM_721)
1306 if (opteron_erratum_721
)
1307 workaround_applied(721);
1312 * The procset_slave and procset_master are used to synchronize
1313 * between the control CPU and the target CPU when starting CPUs.
1315 static cpuset_t procset_slave
, procset_master
;
1318 mp_startup_wait(cpuset_t
*sp
, processorid_t cpuid
)
1322 for (tempset
= *sp
; !CPU_IN_SET(tempset
, cpuid
);
1323 tempset
= *(volatile cpuset_t
*)sp
) {
1326 CPUSET_ATOMIC_DEL(*(cpuset_t
*)sp
, cpuid
);
1330 mp_startup_signal(cpuset_t
*sp
, processorid_t cpuid
)
1334 CPUSET_ATOMIC_ADD(*(cpuset_t
*)sp
, cpuid
);
1335 for (tempset
= *sp
; CPU_IN_SET(tempset
, cpuid
);
1336 tempset
= *(volatile cpuset_t
*)sp
) {
1342 mp_start_cpu_common(cpu_t
*cp
, boolean_t boot
)
1344 _NOTE(ARGUNUSED(boot
));
1350 processorid_t cpuid
;
1351 extern void cpupm_init(cpu_t
*);
1355 ctx
= mach_cpucontext_alloc(cp
);
1358 "cpu%d: failed to allocate context", cp
->cpu_id
);
1361 error
= mach_cpu_start(cp
, ctx
);
1364 "cpu%d: failed to start, error %d", cp
->cpu_id
, error
);
1365 mach_cpucontext_free(cp
, ctx
, error
);
1369 for (delays
= 0, tempset
= procset_slave
; !CPU_IN_SET(tempset
, cpuid
);
1371 if (delays
== 500) {
1373 * After five seconds, things are probably looking
1374 * a bit bleak - explain the hang.
1376 cmn_err(CE_NOTE
, "cpu%d: started, "
1377 "but not running in the kernel yet", cpuid
);
1378 } else if (delays
> 2000) {
1380 * We waited at least 20 seconds, bail ..
1383 cmn_err(CE_WARN
, "cpu%d: timed out", cpuid
);
1384 mach_cpucontext_free(cp
, ctx
, error
);
1389 * wait at least 10ms, then check again..
1391 delay(USEC_TO_TICK_ROUNDUP(10000));
1392 tempset
= *((volatile cpuset_t
*)&procset_slave
);
1394 CPUSET_ATOMIC_DEL(procset_slave
, cpuid
);
1396 mach_cpucontext_free(cp
, ctx
, 0);
1398 if (tsc_gethrtime_enable
)
1399 tsc_sync_master(cpuid
);
1401 if (dtrace_cpu_init
!= NULL
) {
1402 (*dtrace_cpu_init
)(cpuid
);
1406 * During CPU DR operations, the cpu_lock is held by current
1407 * (the control) thread. We can't release the cpu_lock here
1408 * because that will break the CPU DR logic.
1409 * On the other hand, CPUPM and processor group initialization
1410 * routines need to access the cpu_lock. So we invoke those
1411 * routines here on behalf of mp_startup_common().
1413 * CPUPM and processor group initialization routines depend
1414 * on the cpuid probing results. Wait for mp_startup_common()
1415 * to signal that cpuid probing is done.
1417 mp_startup_wait(&procset_slave
, cpuid
);
1419 (void) pg_cpu_init(cp
, B_FALSE
);
1421 mp_startup_signal(&procset_master
, cpuid
);
1427 * Start a single cpu, assuming that the kernel context is available
1428 * to successfully start another cpu.
1430 * (For example, real mode code is mapped into the right place
1431 * in memory and is ready to be run.)
1434 start_cpu(processorid_t who
)
1443 * Check if there's at least a Mbyte of kmem available
1444 * before attempting to start the cpu.
1446 if (kmem_avail() < 1024 * 1024) {
1448 * Kick off a reap in case that helps us with
1456 * First configure cpu.
1458 cp
= mp_cpu_configure_common(who
, B_TRUE
);
1464 error
= mp_start_cpu_common(cp
, B_TRUE
);
1466 mp_cpu_unconfigure_common(cp
, error
);
1470 mutex_exit(&cpu_lock
);
1471 tempset
= cpu_ready_set
;
1472 while (!CPU_IN_SET(tempset
, who
)) {
1474 tempset
= *((volatile cpuset_t
*)&cpu_ready_set
);
1476 mutex_enter(&cpu_lock
);
1482 start_other_cpus(int cprboot
)
1484 _NOTE(ARGUNUSED(cprboot
));
1487 uint_t bootcpuid
= 0;
1490 * Initialize our own cpu_info.
1494 init_cpu_id_gdt(CPU
);
1496 cmn_err(CE_CONT
, "?cpu%d: %s\n", CPU
->cpu_id
, CPU
->cpu_idstr
);
1497 cmn_err(CE_CONT
, "?cpu%d: %s\n", CPU
->cpu_id
, CPU
->cpu_brandstr
);
1500 * Initialize our syscall handlers
1502 init_cpu_syscall(CPU
);
1505 * Take the boot cpu out of the mp_cpus set because we know
1506 * it's already running. Add it to the cpu_ready_set for
1507 * precisely the same reason.
1509 CPUSET_DEL(mp_cpus
, bootcpuid
);
1510 CPUSET_ADD(cpu_ready_set
, bootcpuid
);
1513 * skip the rest of this if
1514 * . only 1 cpu dectected and system isn't hotplug-capable
1517 if ((CPUSET_ISNULL(mp_cpus
) && plat_dr_support_cpu() == 0) ||
1520 cmn_err(CE_CONT
, "?***** Not in MP mode\n");
1525 * perform such initialization as is needed
1526 * to be able to take CPUs on- and off-line.
1530 xc_init_cpu(CPU
); /* initialize processor crosscalls */
1532 if (mach_cpucontext_init() != 0)
1535 flushes_require_xcalls
= 1;
1538 * We lock our affinity to the master CPU to ensure that all slave CPUs
1539 * do their TSC syncs with the same CPU.
1541 affinity_set(CPU_CURRENT
);
1543 for (who
= 0; who
< NCPU
; who
++) {
1544 if (!CPU_IN_SET(mp_cpus
, who
))
1546 ASSERT(who
!= bootcpuid
);
1548 mutex_enter(&cpu_lock
);
1549 if (start_cpu(who
) != 0)
1550 CPUSET_DEL(mp_cpus
, who
);
1551 cpu_state_change_notify(who
, CPU_SETUP
);
1552 mutex_exit(&cpu_lock
);
1555 /* Free the space allocated to hold the microcode file */
1560 mach_cpucontext_fini();
1563 if (get_hwenv() == HW_NATIVE
)
1564 workaround_errata_end();
1565 cmi_post_mpstartup();
1567 if (use_mp
&& ncpus
!= boot_max_ncpus
) {
1569 "System detected %d cpus, but "
1570 "only %d cpu(s) were enabled during boot.",
1571 boot_max_ncpus
, ncpus
);
1573 "Use \"boot-ncpus\" parameter to enable more CPU(s). "
1579 mp_cpu_configure(int cpuid
)
1583 if (use_mp
== 0 || plat_dr_support_cpu() == 0) {
1587 cp
= cpu_get(cpuid
);
1593 * Check if there's at least a Mbyte of kmem available
1594 * before attempting to start the cpu.
1596 if (kmem_avail() < 1024 * 1024) {
1598 * Kick off a reap in case that helps us with
1605 cp
= mp_cpu_configure_common(cpuid
, B_FALSE
);
1606 ASSERT(cp
!= NULL
&& cpu_get(cpuid
) == cp
);
1608 return (cp
!= NULL
? 0 : EAGAIN
);
1612 mp_cpu_unconfigure(int cpuid
)
1616 if (use_mp
== 0 || plat_dr_support_cpu() == 0) {
1618 } else if (cpuid
< 0 || cpuid
>= max_ncpus
) {
1622 cp
= cpu_get(cpuid
);
1626 mp_cpu_unconfigure_common(cp
, 0);
1632 * Startup function for 'other' CPUs (besides boot cpu).
1633 * Called from real_mode_start.
1635 * WARNING: until CPU_READY is set, mp_startup_common and routines called by
1636 * mp_startup_common should not call routines (e.g. kmem_free) that could call
1637 * hat_unload which requires CPU_READY to be set.
1640 mp_startup_common(boolean_t boot
)
1643 uchar_t new_x86_featureset
[BT_SIZEOFMAP(NUM_X86_FEATURES
)];
1644 extern void cpu_event_init_cpu(cpu_t
*);
1647 * We need to get TSC on this proc synced (i.e., any delta
1648 * from cpu0 accounted for) as soon as we can, because many
1649 * many things use gethrtime/pc_gethrestime, including
1650 * interrupts, cmn_err, etc. Before we can do that, we want to
1651 * clear TSC if we're on a buggy Sandy/Ivy Bridge CPU, so do that
1654 bzero(new_x86_featureset
, BT_SIZEOFMAP(NUM_X86_FEATURES
));
1655 cpuid_pass1(cp
, new_x86_featureset
);
1657 if (boot
&& get_hwenv() == HW_NATIVE
&&
1658 cpuid_getvendor(CPU
) == X86_VENDOR_Intel
&&
1659 cpuid_getfamily(CPU
) == 6 &&
1660 (cpuid_getmodel(CPU
) == 0x2d || cpuid_getmodel(CPU
) == 0x3e) &&
1661 is_x86_feature(new_x86_featureset
, X86FSET_TSC
)) {
1662 (void) wrmsr(REG_TSC
, 0UL);
1665 /* Let the control CPU continue into tsc_sync_master() */
1666 mp_startup_signal(&procset_slave
, cp
->cpu_id
);
1668 if (tsc_gethrtime_enable
)
1672 * Once this was done from assembly, but it's safer here; if
1673 * it blocks, we need to be able to swtch() to and from, and
1674 * since we get here by calling t_pc, we need to do that call
1675 * before swtch() overwrites it.
1677 (void) (*ap_mlsetup
)();
1680 * Program this cpu's PAT
1685 * Set up TSC_AUX to contain the cpuid for this processor
1686 * for the rdtscp instruction.
1688 if (is_x86_feature(x86_featureset
, X86FSET_TSCP
))
1689 (void) wrmsr(MSR_AMD_TSCAUX
, cp
->cpu_id
);
1692 * Initialize this CPU's syscall handlers
1694 init_cpu_syscall(cp
);
1697 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the
1698 * highest level at which a routine is permitted to block on
1699 * an adaptive mutex (allows for cpu poke interrupt in case
1700 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks
1701 * device interrupts that may end up in the hat layer issuing cross
1702 * calls before CPU_READY is set.
1704 splx(ipltospl(LOCK_LEVEL
));
1708 * Do a sanity check to make sure this new CPU is a sane thing
1709 * to add to the collection of processors running this system.
1711 * XXX Clearly this needs to get more sophisticated, if x86
1712 * systems start to get built out of heterogenous CPUs; as is
1713 * likely to happen once the number of processors in a configuration
1714 * gets large enough.
1716 if (compare_x86_featureset(x86_featureset
, new_x86_featureset
) ==
1718 cmn_err(CE_CONT
, "cpu%d: featureset\n", cp
->cpu_id
);
1719 print_x86_featureset(new_x86_featureset
);
1720 cmn_err(CE_WARN
, "cpu%d feature mismatch", cp
->cpu_id
);
1724 * There exists a small subset of systems which expose differing
1725 * MWAIT/MONITOR support between CPUs. If MWAIT support is absent from
1726 * the boot CPU, but is found on a later CPU, the system continues to
1727 * operate as if no MWAIT support is available.
1729 * The reverse case, where MWAIT is available on the boot CPU but not
1730 * on a subsequently initialized CPU, is not presently allowed and will
1731 * result in a panic.
1733 if (is_x86_feature(x86_featureset
, X86FSET_MWAIT
) !=
1734 is_x86_feature(new_x86_featureset
, X86FSET_MWAIT
)) {
1735 if (!is_x86_feature(x86_featureset
, X86FSET_MWAIT
)) {
1736 remove_x86_feature(new_x86_featureset
, X86FSET_MWAIT
);
1738 panic("unsupported mixed cpu mwait support detected");
1743 * We could be more sophisticated here, and just mark the CPU
1744 * as "faulted" but at this point we'll opt for the easier
1745 * answer of dying horribly. Provided the boot cpu is ok,
1746 * the system can be recovered by booting with use_mp set to zero.
1748 if (workaround_errata(cp
) != 0)
1749 panic("critical workaround(s) missing for cpu%d", cp
->cpu_id
);
1752 * We can touch cpu_flags here without acquiring the cpu_lock here
1753 * because the cpu_lock is held by the control CPU which is running
1754 * mp_start_cpu_common().
1755 * Need to clear CPU_QUIESCED flag before calling any function which
1756 * may cause thread context switching, such as kmem_alloc() etc.
1757 * The idle thread checks for CPU_QUIESCED flag and loops for ever if
1758 * it's set. So the startup thread may have no chance to switch back
1759 * again if it's switched away with CPU_QUIESCED set.
1761 cp
->cpu_flags
&= ~(CPU_POWEROFF
| CPU_QUIESCED
);
1766 * Setup this processor for XSAVE.
1768 if (fp_save_mech
== FP_XSAVE
) {
1769 xsave_setup_msr(cp
);
1774 cpuid_pass4(cp
, NULL
);
1777 * Correct cpu_idstr and cpu_brandstr on target CPU after
1778 * cpuid_pass1() is done.
1780 (void) cpuid_getidstr(cp
, cp
->cpu_idstr
, CPU_IDSTRLEN
);
1781 (void) cpuid_getbrandstr(cp
, cp
->cpu_brandstr
, CPU_IDSTRLEN
);
1783 cp
->cpu_flags
|= CPU_RUNNING
| CPU_READY
| CPU_EXISTS
;
1785 post_startup_cpu_fixups();
1787 cpu_event_init_cpu(cp
);
1790 * Enable preemption here so that contention for any locks acquired
1791 * later in mp_startup_common may be preempted if the thread owning
1792 * those locks is continuously executing on other CPUs (for example,
1793 * this CPU must be preemptible to allow other CPUs to pause it during
1794 * their startup phases). It's safe to enable preemption here because
1795 * the CPU state is pretty-much fully constructed.
1797 curthread
->t_preempt
= 0;
1799 /* The base spl should still be at LOCK LEVEL here */
1800 ASSERT(cp
->cpu_base_spl
== ipltospl(LOCK_LEVEL
));
1801 set_base_spl(); /* Restore the spl to its proper value */
1803 pghw_physid_create(cp
);
1805 * Delegate initialization tasks, which need to access the cpu_lock,
1806 * to mp_start_cpu_common() because we can't acquire the cpu_lock here
1807 * during CPU DR operations.
1809 mp_startup_signal(&procset_slave
, cp
->cpu_id
);
1810 mp_startup_wait(&procset_master
, cp
->cpu_id
);
1811 pg_cmt_cpu_startup(cp
);
1814 mutex_enter(&cpu_lock
);
1815 cp
->cpu_flags
&= ~CPU_OFFLINE
;
1816 cpu_enable_intr(cp
);
1818 mutex_exit(&cpu_lock
);
1821 /* Enable interrupts */
1825 * Fill out cpu_ucode_info. Update microcode if necessary.
1831 * Set up the CPU module for this CPU. This can't be done
1832 * before this CPU is made CPU_READY, because we may (in
1833 * heterogeneous systems) need to go load another CPU module.
1834 * The act of attempting to load a module may trigger a
1835 * cross-call, which will ASSERT unless this cpu is CPU_READY.
1839 if ((hdl
= cmi_init(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(CPU
),
1840 cmi_ntv_hwcoreid(CPU
), cmi_ntv_hwstrandid(CPU
))) != NULL
) {
1841 if (is_x86_feature(x86_featureset
, X86FSET_MCA
))
1843 cp
->cpu_m
.mcpu_cmi_hdl
= hdl
;
1847 if (boothowto
& RB_DEBUG
)
1851 * Setting the bit in cpu_ready_set must be the last operation in
1852 * processor initialization; the boot CPU will continue to boot once
1853 * it sees this bit set for all active CPUs.
1855 CPUSET_ATOMIC_ADD(cpu_ready_set
, cp
->cpu_id
);
1857 (void) mach_cpu_create_device_node(cp
, NULL
);
1859 cmn_err(CE_CONT
, "?cpu%d: %s\n", cp
->cpu_id
, cp
->cpu_idstr
);
1860 cmn_err(CE_CONT
, "?cpu%d: %s\n", cp
->cpu_id
, cp
->cpu_brandstr
);
1861 cmn_err(CE_CONT
, "?cpu%d initialization complete - online\n",
1865 * Now we are done with the startup thread, so free it up.
1868 panic("mp_startup: cannot return");
1873 * Startup function for 'other' CPUs at boot time (besides boot cpu).
1876 mp_startup_boot(void)
1878 mp_startup_common(B_TRUE
);
1882 * Startup function for hotplug CPUs at runtime.
1885 mp_startup_hotplug(void)
1887 mp_startup_common(B_FALSE
);
1891 * Start CPU on user request.
1895 mp_cpu_start(struct cpu
*cp
)
1897 ASSERT(MUTEX_HELD(&cpu_lock
));
1902 * Stop CPU on user request.
1905 mp_cpu_stop(struct cpu
*cp
)
1907 extern int cbe_psm_timer_mode
;
1908 ASSERT(MUTEX_HELD(&cpu_lock
));
1912 * If TIMER_PERIODIC mode is used, CPU0 is the one running it;
1913 * can't stop it. (This is true only for machines with no TSC.)
1916 if ((cbe_psm_timer_mode
== TIMER_PERIODIC
) && (cp
->cpu_id
== 0))
1923 * Take the specified CPU out of participation in interrupts.
1926 cpu_disable_intr(struct cpu
*cp
)
1928 if (psm_disable_intr(cp
->cpu_id
) != DDI_SUCCESS
)
1931 cp
->cpu_flags
&= ~CPU_ENABLE
;
1936 * Allow the specified CPU to participate in interrupts.
1939 cpu_enable_intr(struct cpu
*cp
)
1941 ASSERT(MUTEX_HELD(&cpu_lock
));
1942 cp
->cpu_flags
|= CPU_ENABLE
;
1943 psm_enable_intr(cp
->cpu_id
);
1947 mp_cpu_faulted_enter(struct cpu
*cp
)
1949 cmi_hdl_t hdl
= cp
->cpu_m
.mcpu_cmi_hdl
;
1954 hdl
= cmi_hdl_lookup(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(cp
),
1955 cmi_ntv_hwcoreid(cp
), cmi_ntv_hwstrandid(cp
));
1958 cmi_faulted_enter(hdl
);
1964 mp_cpu_faulted_exit(struct cpu
*cp
)
1966 cmi_hdl_t hdl
= cp
->cpu_m
.mcpu_cmi_hdl
;
1971 hdl
= cmi_hdl_lookup(CMI_HDL_NATIVE
, cmi_ntv_hwchipid(cp
),
1972 cmi_ntv_hwcoreid(cp
), cmi_ntv_hwstrandid(cp
));
1975 cmi_faulted_exit(hdl
);
1981 * The following two routines are used as context operators on threads belonging
1982 * to processes with a private LDT (see sysi86). Due to the rarity of such
1983 * processes, these routines are currently written for best code readability and
1984 * organization rather than speed. We could avoid checking x86_featureset at
1985 * every context switch by installing different context ops, depending on
1986 * x86_featureset, at LDT creation time -- one for each combination of fast
1992 cpu_fast_syscall_disable(void *arg
)
1994 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
1995 is_x86_feature(x86_featureset
, X86FSET_SEP
))
1997 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
1998 is_x86_feature(x86_featureset
, X86FSET_ASYSC
))
1999 cpu_asysc_disable();
2004 cpu_fast_syscall_enable(void *arg
)
2006 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2007 is_x86_feature(x86_featureset
, X86FSET_SEP
))
2009 if (is_x86_feature(x86_featureset
, X86FSET_MSR
) &&
2010 is_x86_feature(x86_featureset
, X86FSET_ASYSC
))
2015 cpu_sep_enable(void)
2017 ASSERT(is_x86_feature(x86_featureset
, X86FSET_SEP
));
2018 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2020 wrmsr(MSR_INTC_SEP_CS
, (uint64_t)(uintptr_t)KCS_SEL
);
2024 cpu_sep_disable(void)
2026 ASSERT(is_x86_feature(x86_featureset
, X86FSET_SEP
));
2027 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2030 * Setting the SYSENTER_CS_MSR register to 0 causes software executing
2031 * the sysenter or sysexit instruction to trigger a #gp fault.
2033 wrmsr(MSR_INTC_SEP_CS
, 0);
2037 cpu_asysc_enable(void)
2039 ASSERT(is_x86_feature(x86_featureset
, X86FSET_ASYSC
));
2040 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2042 wrmsr(MSR_AMD_EFER
, rdmsr(MSR_AMD_EFER
) |
2043 (uint64_t)(uintptr_t)AMD_EFER_SCE
);
2047 cpu_asysc_disable(void)
2049 ASSERT(is_x86_feature(x86_featureset
, X86FSET_ASYSC
));
2050 ASSERT(curthread
->t_preempt
|| getpil() >= LOCK_LEVEL
);
2053 * Turn off the SCE (syscall enable) bit in the EFER register. Software
2054 * executing syscall or sysret with this bit off will incur a #ud trap.
2056 wrmsr(MSR_AMD_EFER
, rdmsr(MSR_AMD_EFER
) &
2057 ~((uint64_t)(uintptr_t)AMD_EFER_SCE
));