include/sys/nxge/nxge_mii.h

   1 /*
   2  * CDDL HEADER START
   3  *
   4  * The contents of this file are subject to the terms of the
   5  * Common Development and Distribution License (the "License").
   6  * You may not use this file except in compliance with the License.
   7  *
   8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
   9  * or http://www.opensolaris.org/os/licensing.
  10  * See the License for the specific language governing permissions
  11  * and limitations under the License.
  12  *
  13  * When distributing Covered Code, include this CDDL HEADER in each
  14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
  15  * If applicable, add the following below this CDDL HEADER, with the
  16  * fields enclosed by brackets "[]" replaced with your own identifying
  17  * information: Portions Copyright [yyyy] [name of copyright owner]
  18  *
  19  * CDDL HEADER END
  20  */
  21 /*
  22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
  23  * Use is subject to license terms.
  24  */
  25
  26 #ifndef _SYS_NXGE_NXGE_MII_H_
  27 #define _SYS_NXGE_NXGE_MII_H_
  28
  29 #pragma ident   "%Z%%M% %I%     %E% SMI"
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35 #include <sys/miiregs.h>
  36
  37 /*
  38  * Configuration Register space.
  39  */
  40
  41 #define NXGE_MII_LPRXNPR                8
  42 #define NXGE_MII_GCR                    9
  43 #define NXGE_MII_GSR                    10
  44 #define NXGE_MII_RES0                   11
  45 #define NXGE_MII_RES1                   12
  46 #define NXGE_MII_RES2                   13
  47 #define NXGE_MII_RES3                   14
  48 #define NXGE_MII_ESR                    15
  49
  50 #define NXGE_MII_SHADOW                 MII_VENDOR(0xc)
  51 /* Shadow register definition */
  52 #define NXGE_MII_MODE_CONTROL_REG       MII_VENDOR(0xf)
  53
  54 #define NXGE_MAX_MII_REGS               32
  55
  56 /*
  57  * Configuration Register space.
  58  */
  59 typedef struct _mii_regs {
  60         uchar_t bmcr;           /* Basic mode control register */
  61         uchar_t bmsr;           /* Basic mode status register */
  62         uchar_t idr1;           /* Phy identifier register 1 */
  63         uchar_t idr2;           /* Phy identifier register 2 */
  64         uchar_t anar;           /* Auto-Negotiation advertisement register */
  65         uchar_t anlpar;         /* Auto-Negotiation link Partner ability reg */
  66         uchar_t aner;           /* Auto-Negotiation expansion register */
  67         uchar_t nptxr;          /* Next page transmit register */
  68         uchar_t lprxnpr;        /* Link partner received next page register */
  69         uchar_t gcr;            /* Gigabit basic mode control register. */
  70         uchar_t gsr;            /* Gigabit basic mode status register */
  71         uchar_t mii_res1[4];    /* For future use by MII working group */
  72         uchar_t esr;            /* Extended status register. */
  73         uchar_t vendor_res[12]; /* For future use by Phy Vendors */
  74         uchar_t shadow;
  75         uchar_t vendor_res2[3]; /* For future use by Phy Vendors */
  76 } mii_regs_t, *p_mii_regs_t;
  77
  78 /*
  79  * MII Register 0: Basic mode control register.
  80  */
  81 typedef union _mii_bmcr {
  82         uint16_t value;
  83         struct {
  84 #if defined(_BIT_FIELDS_HTOL)
  85                 uint16_t reset:1;
  86                 uint16_t loopback:1;
  87                 uint16_t speed_sel:1;
  88                 uint16_t enable_autoneg:1;
  89                 uint16_t power_down:1;
  90                 uint16_t isolate:1;
  91                 uint16_t restart_autoneg:1;
  92                 uint16_t duplex_mode:1;
  93                 uint16_t col_test:1;
  94                 uint16_t speed_1000_sel:1;
  95                 uint16_t res1:6;
  96 #elif defined(_BIT_FIELDS_LTOH)
  97                 uint16_t res1:6;
  98                 uint16_t speed_1000_sel:1;
  99                 uint16_t col_test:1;
 100                 uint16_t duplex_mode:1;
 101                 uint16_t restart_autoneg:1;
 102                 uint16_t isolate:1;
 103                 uint16_t power_down:1;
 104                 uint16_t enable_autoneg:1;
 105                 uint16_t speed_sel:1;
 106                 uint16_t loopback:1;
 107                 uint16_t reset:1;
 108 #endif
 109         } bits;
 110 } mii_bmcr_t, *p_mii_bmcr_t;
 111
 112 /*
 113  * MII Register 1:  Basic mode status register.
 114  */
 115 typedef union _mii_bmsr {
 116         uint16_t value;
 117         struct {
 118 #if defined(_BIT_FIELDS_HTOL)
 119                 uint16_t link_100T4:1;
 120                 uint16_t link_100fdx:1;
 121                 uint16_t link_100hdx:1;
 122                 uint16_t link_10fdx:1;
 123                 uint16_t link_10hdx:1;
 124                 uint16_t res2:2;
 125                 uint16_t extend_status:1;
 126                 uint16_t res1:1;
 127                 uint16_t preamble_supress:1;
 128                 uint16_t auto_neg_complete:1;
 129                 uint16_t remote_fault:1;
 130                 uint16_t auto_neg_able:1;
 131                 uint16_t link_status:1;
 132                 uint16_t jabber_detect:1;
 133                 uint16_t ext_cap:1;
 134 #elif defined(_BIT_FIELDS_LTOH)
 135                 int16_t ext_cap:1;
 136                 uint16_t jabber_detect:1;
 137                 uint16_t link_status:1;
 138                 uint16_t auto_neg_able:1;
 139                 uint16_t remote_fault:1;
 140                 uint16_t auto_neg_complete:1;
 141                 uint16_t preamble_supress:1;
 142                 uint16_t res1:1;
 143                 uint16_t extend_status:1;
 144                 uint16_t res2:2;
 145                 uint16_t link_10hdx:1;
 146                 uint16_t link_10fdx:1;
 147                 uint16_t link_100hdx:1;
 148                 uint16_t link_100fdx:1;
 149                 uint16_t link_100T4:1;
 150 #endif
 151         } bits;
 152 } mii_bmsr_t, *p_mii_bmsr_t;
 153
 154 /*
 155  * MII Register 2: Physical Identifier 1.
 156  */
 157 /* contains BCM OUI bits [3:18] */
 158 typedef union _mii_idr1 {
 159         uint16_t value;
 160         struct {
 161                 uint16_t ieee_address:16;
 162         } bits;
 163 } mii_idr1_t, *p_mii_idr1_t;
 164
 165 /*
 166  * MII Register 3: Physical Identifier 2.
 167  */
 168 typedef union _mii_idr2 {
 169         uint16_t value;
 170         struct {
 171 #if defined(_BIT_FIELDS_HTOL)
 172                 uint16_t ieee_address:6;
 173                 uint16_t model_no:6;
 174                 uint16_t rev_no:4;
 175 #elif defined(_BIT_FIELDS_LTOH)
 176                 uint16_t rev_no:4;
 177                 uint16_t model_no:6;
 178                 uint16_t ieee_address:6;
 179 #endif
 180         } bits;
 181 } mii_idr2_t, *p_mii_idr2_t;
 182
 183 /*
 184  * MII Register 4: Auto-negotiation advertisement register.
 185  */
 186 typedef union _mii_anar {
 187         uint16_t value;
 188         struct {
 189 #if defined(_BIT_FIELDS_HTOL)
 190                 uint16_t np_indication:1;
 191                 uint16_t acknowledge:1;
 192                 uint16_t remote_fault:1;
 193                 uint16_t res1:1;
 194                 uint16_t cap_asmpause:1;
 195                 uint16_t cap_pause:1;
 196                 uint16_t cap_100T4:1;
 197                 uint16_t cap_100fdx:1;
 198                 uint16_t cap_100hdx:1;
 199                 uint16_t cap_10fdx:1;
 200                 uint16_t cap_10hdx:1;
 201                 uint16_t selector:5;
 202 #elif defined(_BIT_FIELDS_LTOH)
 203                 uint16_t selector:5;
 204                 uint16_t cap_10hdx:1;
 205                 uint16_t cap_10fdx:1;
 206                 uint16_t cap_100hdx:1;
 207                 uint16_t cap_100fdx:1;
 208                 uint16_t cap_100T4:1;
 209                 uint16_t cap_pause:1;
 210                 uint16_t cap_asmpause:1;
 211                 uint16_t res1:1;
 212                 uint16_t remote_fault:1;
 213                 uint16_t acknowledge:1;
 214                 uint16_t np_indication:1;
 215 #endif
 216         } bits;
 217 } mii_anar_t, *p_mii_anar_t;
 218
 219 /*
 220  * MII Register 5: Auto-negotiation link partner ability register.
 221  */
 222 typedef mii_anar_t mii_anlpar_t, *pmii_anlpar_t;
 223
 224 /*
 225  * MII Register 6: Auto-negotiation expansion register.
 226  */
 227 typedef union _mii_aner {
 228         uint16_t value;
 229         struct {
 230 #if defined(_BIT_FIELDS_HTOL)
 231                 uint16_t res:11;
 232                 uint16_t mlf:1;
 233                 uint16_t lp_np_able:1;
 234                 uint16_t np_able:1;
 235                 uint16_t page_rx:1;
 236                 uint16_t lp_an_able:1;
 237 #else
 238                 uint16_t lp_an_able:1;
 239                 uint16_t page_rx:1;
 240                 uint16_t np_able:1;
 241                 uint16_t lp_np_able:1;
 242                 uint16_t mlf:1;
 243                 uint16_t res:11;
 244 #endif
 245         } bits;
 246 } mii_aner_t, *p_mii_aner_t;
 247
 248 /*
 249  * MII Register 7: Next page transmit register.
 250  */
 251 typedef union _mii_nptxr {
 252         uint16_t value;
 253         struct {
 254 #if defined(_BIT_FIELDS_HTOL)
 255                 uint16_t np:1;
 256                 uint16_t res:1;
 257                 uint16_t msgp:1;
 258                 uint16_t ack2:1;
 259                 uint16_t toggle:1;
 260                 uint16_t res1:11;
 261 #else
 262                 uint16_t res1:11;
 263                 uint16_t toggle:1;
 264                 uint16_t ack2:1;
 265                 uint16_t msgp:1;
 266                 uint16_t res:1;
 267                 uint16_t np:1;
 268 #endif
 269         } bits;
 270 } mii_nptxr_t, *p_mii_nptxr_t;
 271
 272 /*
 273  * MII Register 8: Link partner received next page register.
 274  */
 275 typedef union _mii_lprxnpr {
 276         uint16_t value;
 277         struct {
 278 #if defined(_BIT_FIELDS_HTOL)
 279                 uint16_t np:1;
 280                         uint16_t ack:1;
 281                 uint16_t msgp:1;
 282                 uint16_t ack2:1;
 283                 uint16_t toggle:1;
 284                 uint16_t mcf:11;
 285 #else
 286                 uint16_t mcf:11;
 287                 uint16_t toggle:1;
 288                 uint16_t ack2:1;
 289                 uint16_t msgp:1;
 290                 uint16_t ack:1;
 291                 uint16_t np:1;
 292 #endif
 293         } bits;
 294 } mii_lprxnpr_t, *p_mii_lprxnpr_t;
 295
 296 /*
 297  * MII Register 9: 1000BaseT control register.
 298  */
 299 typedef union _mii_gcr {
 300         uint16_t value;
 301         struct {
 302 #if defined(_BIT_FIELDS_HTOL)
 303                 uint16_t test_mode:3;
 304                 uint16_t ms_mode_en:1;
 305                 uint16_t master:1;
 306                 uint16_t dte_or_repeater:1;
 307                 uint16_t link_1000fdx:1;
 308                 uint16_t link_1000hdx:1;
 309                 uint16_t res:8;
 310 #else
 311                 uint16_t res:8;
 312                 uint16_t link_1000hdx:1;
 313                 uint16_t link_1000fdx:1;
 314                 uint16_t dte_or_repeater:1;
 315                 uint16_t master:1;
 316                 uint16_t ms_mode_en:1;
 317                 uint16_t test_mode:3;
 318 #endif
 319         } bits;
 320 } mii_gcr_t, *p_mii_gcr_t;
 321
 322 /*
 323  * MII Register 10: 1000BaseT status register.
 324  */
 325 typedef union _mii_gsr {
 326         uint16_t value;
 327         struct {
 328 #if defined(_BIT_FIELDS_HTOL)
 329                 uint16_t ms_config_fault:1;
 330                 uint16_t ms_resolve:1;
 331                 uint16_t local_rx_status:1;
 332                 uint16_t remote_rx_status:1;
 333                 uint16_t link_1000fdx:1;
 334                 uint16_t link_1000hdx:1;
 335                 uint16_t res:2;
 336                 uint16_t idle_err_cnt:8;
 337 #else
 338                 uint16_t idle_err_cnt:8;
 339                 uint16_t res:2;
 340                 uint16_t link_1000hdx:1;
 341                 uint16_t link_1000fdx:1;
 342                 uint16_t remote_rx_status:1;
 343                 uint16_t local_rx_status:1;
 344                 uint16_t ms_resolve:1;
 345                 uint16_t ms_config_fault:1;
 346 #endif
 347         } bits;
 348 } mii_gsr_t, *p_mii_gsr_t;
 349
 350 /*
 351  * MII Register 15: Extended status register.
 352  */
 353 typedef union _mii_esr {
 354         uint16_t value;
 355         struct {
 356 #if defined(_BIT_FIELDS_HTOL)
 357                 uint16_t link_1000Xfdx:1;
 358                 uint16_t link_1000Xhdx:1;
 359                 uint16_t link_1000fdx:1;
 360                 uint16_t link_1000hdx:1;
 361                 uint16_t res:12;
 362 #else
 363                         uint16_t res:12;
 364                 uint16_t link_1000hdx:1;
 365                 uint16_t link_1000fdx:1;
 366                 uint16_t link_1000Xhdx:1;
 367                 uint16_t link_1000Xfdx:1;
 368 #endif
 369         } bits;
 370 } mii_esr_t, *p_mii_esr_t;
 371
 372 #define NXGE_MODE_SELECT_FIBER  0x01
 373 /* Shadow regiser 0x11111 */
 374 typedef union _mii_mode_control_stat {
 375         uint16_t value;
 376         struct {
 377 #if defined(_BIT_FIELDS_HTOL)
 378                 uint16_t write_enable:1;
 379                 uint16_t shadow:5;
 380                 uint16_t rsv:1;
 381                 uint16_t change:1;
 382                 uint16_t copper:1;
 383                 uint16_t fiber:1;
 384                 uint16_t copper_energy:1;
 385                 uint16_t fiber_signal:1;
 386                 uint16_t rsv1:1;
 387                 uint16_t mode:2;
 388                 uint16_t enable:1;
 389 #elif defined(_BIT_FIELDS_LTOH)
 390                 uint16_t enable:1;
 391                 uint16_t mode:2;
 392                 uint16_t rsv1:1;
 393                 uint16_t fiber_signal:1;
 394                 uint16_t copper_energy:1;
 395                 uint16_t fiber:1;
 396                 uint16_t copper:1;
 397                 uint16_t change:1;
 398                 uint16_t rsv:1;
 399                 uint16_t shadow:5;
 400                 uint16_t write_enable:1;
 401 #endif
 402         } bits;
 403 } mii_mode_control_stat_t, *p_mode_control_stat_t;
 404
 405 #ifdef __cplusplus
 406 }
 407 #endif
 408
 409 #endif /* _SYS_NXGE_NXGE_MII_H_ */