| commit | 2a2b1d2a3e97b4353eec5a40c0de4b932340b3fc | |
| author | Vineet Gupta <vgupta@synopsys.com> | |
| Thu, 19 Feb 2015 13:44:01 +0000 (19 19:14 +0530) | ||
| committer | Bernhard Reutner-Fischer <rep.dot.nop@gmail.com> | |
| Fri, 20 Feb 2015 10:34:55 +0000 (20 11:34 +0100) | ||
| tree | 6769818d75a1c3a8d6b155aa7b6e32c715dcfcd0 | treesnapshot (tar.gz zip) |
| parent | df273fedf4fef25983ef6ec7e42b03d54f44960d | commitdiff |
posix_fadvise: handle 2 variants for SYSCALL_ALIGN_64BIT
arm/powerpc/xtensa pass @advice as 2nd arg to syscall (vs. canonical 4th)
Current code however does this for UCLIBC_SYSCALL_ALIGN_64BIT which
powerpc/xtensa also happen to define.
This is not true for ARCv2 ISA and possibly other arch of future with
64-bit even register requirement, which uses the standard syscall
handler in kernel.
Fix that by providing 2 variants of SYSCALL_ALIGN_64BIT
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
arm/powerpc/xtensa pass @advice as 2nd arg to syscall (vs. canonical 4th)
Current code however does this for UCLIBC_SYSCALL_ALIGN_64BIT which
powerpc/xtensa also happen to define.
This is not true for ARCv2 ISA and possibly other arch of future with
64-bit even register requirement, which uses the standard syscall
handler in kernel.
Fix that by providing 2 variants of SYSCALL_ALIGN_64BIT
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Cc: Baruch Siach <baruch@tkos.co.il>
Cc: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Bernhard Reutner-Fischer <rep.dot.nop@gmail.com>
| libc/sysdeps/linux/common/posix_fadvise.c | diffblobblamehistory | |
| libc/sysdeps/linux/common/posix_fadvise64.c | diffblobblamehistory |