From 1c7edab599ccd359d27211fb3de53eda68ef5d4e Mon Sep 17 00:00:00 2001
From: Jeff Connelly <shellreef+git@gmail.com>
Date: Wed, 21 May 2008 22:50:19 -0700
Subject: [PATCH] Chip mapper: add support for MDP1403 7-resistor network.

---
 bb/bb.py     | 27 ++++++++++++++++++---------
 bb/rtest.net | 16 ++++++++++++++++
 2 files changed, 34 insertions(+), 9 deletions(-)
 create mode 100755 bb/rtest.net

diff --git a/bb/bb.py b/bb/bb.py
index 67a8037..f2f5b0d 100755
--- a/bb/bb.py
+++ b/bb/bb.py
@@ -28,15 +28,19 @@ SUBCIRCUITS_TO_MAP = ('tg', 'tinv', 'tnor', 'tnor3', 'tnand', 'tnand3', 'sp3t-1'
 SUBCIRCUITS_CAN_MAP = ('tg', 'tinv', 'tnor', 'tnand')        # subcircuits we actually can map to ICs, as of yet
 SUBCIRCUITS_PASS = ('sp3t-1', 'sp3t-2', 'sp3t-3')                 # pass unchanged to pads.py
 
+# If False, use discrete resistors
+# If True, use the MDP140 resistor network
+USE_RESISTOR_CHIP = os.environ.get("JC_USE_RESISTOR_CHIP", True)
+RESISTOR_CHIP = "MDP1403"   # Vishay isolated 7-resistor network
+
 KNOWN_CHIPS = (
         "CD4007",   # dual complementary MOSFETs + binary inverter
         "CD4016",   # quad transmission gates
-        "MDP1401"   # isolated 7-resistor network
+        RESISTOR_CHIP
         )
 
-# If False, use discrete resistors
-# If True, use the MDP1401 resistor network
-USE_RESISTOR_CHIP = os.environ.get("JC_USE_RESISTOR_CHIP", False)
+# Pairs of pins 
+RESISTOR_NETWORK_PINS = ((1, 14), (2, 13), (3, 12), (4, 11), (5, 10), (6, 9), (7,8))
 
 def combine_dicts(dict1, dict2):
     """Combine two dictionaries; dict2 takes priority over dict1."""
@@ -195,7 +199,7 @@ def find_chip_no_add(chips, model_needed, pins_needed_options):
     return None
 
 def find_pins_needed(pins):
-    """From a mod.pins[x] dict, return the pins needed for each model, for find_chip()"""
+    """From a mod.pins[x] dict, return the pins needed for each SPICE model, for find_chip()"""
     need = {}
     for x in pins.values():
         if type(x) == types.TupleType:
@@ -302,8 +306,7 @@ def assign_part(chips, subckt_defns, extra, model_name, external_nodes, refdesg)
                     "double-check the model definition for '%s', specifically, " +
                     "parts_consumed and parts_kept.\nAlso, check if the model was rewritten!") % (line, model_name, PROGRAM_NAME, model_name)
 
-        # TODO XXX: Allocate resistors to resistor network
-        
+       
         #name = "%s_%s_%s_%s" % (words[0], model_name, chip_num, refdesg)
         name = "%s%s$%s" % (words[0][0], refdesg, words[0])
 
@@ -332,7 +335,13 @@ def assign_part(chips, subckt_defns, extra, model_name, external_nodes, refdesg)
 
         new_words.append(model_name)
 
-        extra.append(" ".join(new_words))
+        if words[0][0] == "R" and USE_RESISTOR_CHIP:
+            chip_num, option_num = find_chip(chips, RESISTOR_CHIP, RESISTOR_NETWORK_PINS)
+            pins = RESISTOR_NETWORK_PINS[option_num]
+            chips[chip_num][1][pins[0]] = new_words[1]
+            chips[chip_num][1][pins[1]] = new_words[2]
+        else: 
+            extra.append(" ".join(new_words))
 
     return chips, extra
 
@@ -700,7 +709,7 @@ def main():
 
 if __name__ == "__main__":
     if len(sys.argv) > 1 and sys.argv[1] == "-t":
+        #test_assignment()
         test_flatten()
         raise SystemExit
-    #test_assignment()
     main()
diff --git a/bb/rtest.net b/bb/rtest.net
new file mode 100755
index 0000000..7687502
--- /dev/null
+++ b/bb/rtest.net
@@ -0,0 +1,16 @@
+* Based on Z:\trinary\code\circuits\tinv_test.asc
+V1 N001 0 -5V
+Xsti N001 STI_Out1 sti
+
+* block symbol definitions
+.subckt tinv Vin PTI_Out STI_Out NTI_Out
+RP PTI_Out STI_Out 12k
+RN STI_Out NTI_Out 12k
+MN NTI_Out Vin $G_Vss $G_Vss CD4007N
+MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P
+.ends tinv
+
+.subckt sti IN OUT
+XX1 IN NC_01 OUT NC_02 tinv
+.ends sti
+
-- 
2.11.4.GIT