Added comments to logicCpu.py.
[trinary.git] / asm / logicCpu.py
blob0fff9522399774eca2cd71182b947b174343f37f
2 trit_integer = {"i": -1, "0":0, "1":1}
4 def Decoder(tritstream):
5 """ Decode a single instruction.
6 tristream: stream of trits will only process the first 3 trits.
7 return: dictionary containing the operation
8 """
9 inst = {"op":trit_integer[tritstream[0]]}
11 # cmp and be
12 if inst["op"] == -1 or inst["op"] == 1:
13 inst["src1"] = trit_integer[tritstream[1]]
14 inst["src2"] = trit_integer[tritstream[2]]
16 # lwi
17 elif inst["op"] == 0:
18 print "hi"
19 inst["src1"] = trit_integer[tritstream[1]]
20 inst["src2"] = trit_integer[tritstream[2]]
21 inst["immed"] = 3*inst["src1"] + inst["src2"]
23 return inst
25 def Execute(memory, registers, pc):
26 """ Execute one instruction.
27 memory: were decoded instructions are stored
28 registers: contains registers and their values
29 pc: program counter
30 """
32 op = (memory[pc])["op"]
34 # cmp
35 if op == -1:
36 src1 = (memory[pc])["src1"]
37 src2 = (memory[pc])["src1"]
38 if (registers[src1] - registers[src2]) == 0:
39 registers["S"] = 0
40 else:
41 registers["S"] = 1
42 # lwi
43 elif op == 0:
44 registers[1] = (memory[pc])["immed"]
45 # be
46 elif op == 1:
47 if registers["S"] == 0:
48 op = (memory[pc])["src1"]
49 else:
50 op = (memory[pc])["src2"]