From 18a9e74e3291a97c8cbe40ac0f44d4ee84654c6c Mon Sep 17 00:00:00 2001 From: David Cohen Date: Sat, 12 Jan 2008 12:35:58 -0400 Subject: [PATCH] ARM: LPC2XXX: Removing PLL codes from asm startup file. This patch removes PLL codes from asm startup file. The PLL code will be moved to clock subsystem. Signed-off-by: David Cohen --- arch/arm7/mach-lpc21xx/start_lpc2148.S | 56 --------------------------- include/asm-arm7/arch-lpc2xxx/start_lpc2148.h | 7 ---- 2 files changed, 63 deletions(-) diff --git a/arch/arm7/mach-lpc21xx/start_lpc2148.S b/arch/arm7/mach-lpc21xx/start_lpc2148.S index b76d9b3..f97bd82 100644 --- a/arch/arm7/mach-lpc21xx/start_lpc2148.S +++ b/arch/arm7/mach-lpc21xx/start_lpc2148.S @@ -42,29 +42,6 @@ .equ sram_top, SRAM_TOP .equ stackTop, SRAM_TOP -#define VAL_PLLCFG_MSEL ((PLL_MSEL - 1) << 0) -#if (PLL_PSEL == 1) -#define PLL_PSEL_VALUE 0x00 -#elif (PLL_PSEL == 2) -#define PLL_PSEL_VALUE 0x01 -#elif (PLL_PSEL == 4) -#define PLL_PSEL_VALUE 0x10 -#elif (PLL_PSEL == 8) -#define PLL_PSEL_VALUE 0x11 -#endif -#define VAL_PLLCFG_PSEL (PLL_PSEL_VALUE << 5) -#define VAL_PLLCFG (VAL_PLLCFG_MSEL | VAL_PLLCFG_PSEL) - -# Phase Locked Loop (PLL) definitions - .equ PLL_BASE, 0xE01FC080 /* PLL Base Address */ - .equ PLLCON_OFS, 0x00 /* PLL Control Offset*/ - .equ PLLCFG_OFS, 0x04 /* PLL Configuration Offset */ - .equ PLLSTAT_OFS, 0x08 /* PLL Status Offset */ - .equ PLLFEED_OFS, 0x0C /* PLL Feed Offset */ - .equ PLLCON_PLLE, (1<<0) /* PLL Enable */ - .equ PLLCON_PLLC, (1<<1) /* PLL Connect */ - .equ PLLSTAT_PLOCK, (1<<10) /* PLL Lock Status */ - #define HANDLER(HandlerLabel,HandleLabel) \ HandlerLabel: ;\ sub sp, sp, #4 ;\ @@ -159,39 +136,6 @@ fiqHandlerAddress: # Reset Handler handleReset: -#if (USE_PLL == 1) - LDR R0, =PLL_BASE - MOV R1, #0xAA - MOV R2, #0x55 - -# Disable PLL before programming (in case it was enabled before) - MOV R3, #0 - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - -# Wait for -# Configure and Enable PLL - MOV R3, #VAL_PLLCFG - STR R3, [R0, #PLLCFG_OFS] - MOV R3, #PLLCON_PLLE - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] - -# Wait until PLL Locked -PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS] - ANDS R3, R3, #PLLSTAT_PLOCK - BEQ PLL_Loop - -# Switch to PLL Clock - MOV R3, #(PLLCON_PLLE | PLLCON_PLLC) - STR R3, [R0, #PLLCON_OFS] - STR R1, [R0, #PLLFEED_OFS] - STR R2, [R0, #PLLFEED_OFS] -#endif - - # Setup Stack for each mode LDR R0, =stackTop diff --git a/include/asm-arm7/arch-lpc2xxx/start_lpc2148.h b/include/asm-arm7/arch-lpc2xxx/start_lpc2148.h index 28f9e30..9e93f30 100644 --- a/include/asm-arm7/arch-lpc2xxx/start_lpc2148.h +++ b/include/asm-arm7/arch-lpc2xxx/start_lpc2148.h @@ -24,15 +24,8 @@ #define FOSC 12000000 -#define PLL_MSEL 5 -#define PLL_PSEL 2 #define VPB_DIV 4 -#define CCLK (FOSC * PLL_MSEL) -#define FCCO (CCLK * 2 * PLL_PSEL) -#define PCLK (CCLK / VPB_DIV) - -#define USE_PLL 1 #define MAM_MAP 1 /* setup stack sizes */ -- 2.11.4.GIT