| commit | c9940681750d581254492801893301717d80317a | |
| author | Ekaitz Zarraga <ekaitz@elenq.tech> | |
| Tue, 23 Apr 2024 10:05:05 +0000 (23 12:05 +0200) | ||
| committer | Ekaitz Zarraga <ekaitz@elenq.tech> | |
| Tue, 23 Apr 2024 10:05:05 +0000 (23 12:05 +0200) | ||
| tree | 98ed24fc0f7a173c7fc7bf021c95a6a1eaef9955 | treesnapshot (tar.gz zip) |
| parent | 0703df1a6a8215c74f4f4a20aa9270eff1397733 | commitdiff |
riscv: asm: Add load-reserved and store-conditional
Add Atomic instructions `ld` and `sc` in their 32 bit and 64 bit
versions.
Add Atomic instructions `ld` and `sc` in their 32 bit and 64 bit
versions.
| riscv64-asm.c | diffblobblamehistory | |
| riscv64-tok.h | diffblobblamehistory |