2020-02-28 | Richard Henderson | target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn ...off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200218190958.745-2-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Set MVFR0.FPSP for ARMv5 cpus ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200214181547.21408-5-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Use isar_feature_aa32_simd_r32 more places ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200214181547.21408-4-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Rename isar_feature_aa32_simd_r32 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200214181547.21408-3-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Convert PMULL.8 to gvec ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200216214232.4230-5-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Convert PMULL.64 to gvec ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200216214232.4230-4-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Convert PMUL.8 to gvec ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200216214232.4230-3-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Vectorize USHL and SSHL ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200216214232.4230-2-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Split out aa64_va_parameter_tbi, aa64_va_paramet... ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200216194343.21331-5-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Remove ttbr1_valid check from get_phys_addr_lpae ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200216194343.21331-4-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Fix select for aa64_va_parameters_both ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200216194343.21331-3-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Use bit 55 explicitly for pauth ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200216194343.21331-2-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Flush high bits of sve register after AdvSIMD INS ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200214194643.23317-5-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Flush high bits of sve register after AdvSIMD... ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200214194643.23317-4-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Flush high bits of sve register after AdvSIMD... ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200214194643.23317-3-richard.henderson@linaro.org |
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2020-02-21 | Richard Henderson | target/arm: Flush high bits of sve register after AdvSIMD EXT ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200214194643.23317-2-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Enable ARMv8.2-UAO in -cpu max ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-21-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Implement UAO semantics ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-20-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Update MSR access to UAO ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-19-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Add ID_AA64MMFR2_EL1 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-18-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Enable ARMv8.2-ATS1E1 in -cpu max ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-17-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Implement ATS1E1 system registers ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-16-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Set PAN bit as required on exception entry ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-15-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Enforce PAN semantics in get_S1prot ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-14-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Update arm_mmu_idx_el for PAN ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-13-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Update MSR access for PAN ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-12-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Introduce aarch64_pstate_valid_mask ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-11-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Remove CPSR_RESERVED ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-10-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Use aarch32_cpsr_valid_mask in helper_exception_... ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-9-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Replace CPSR_ERET_MASK with aarch32_cpsr_valid_mask ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-8-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Mask CPSR_J when Jazelle is not enabled ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-7-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Split out aarch32_cpsr_valid_mask ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-6-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Move LOR regdefs to file scope ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-5-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Add isar_feature tests for PAN + ATS1E1 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-4-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Add mmu_idx for EL1 and EL2 w/ PAN enabled ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-3-richard.henderson@linaro.org |
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2020-02-13 | Richard Henderson | target/arm: Add arm_mmu_idx_is_stage1_of_2 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200208125816.14954-2-richard.henderson@linaro.org |
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2020-02-12 | Richard Henderson | tcg: Add tcg_gen_gvec_5_ptr ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-02-07 | Richard Henderson | target/arm: Raise only one interrupt in arm_cpu_exec_interrupt ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-42-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Use bool for unmasked in arm_excp_unmasked ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-41-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Pass more cpu state to arm_excp_unmasked ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-40-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Move arm_excp_unmasked to cpu.c ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-39-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Enable ARMv8.1-VHE in -cpu max ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-38-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-37-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update get_a64_user_mem_index for VHE ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-36-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update {fp,sve}_exception_el for VHE ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-34-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update arm_phys_excp_target_el for TGE ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-33-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Flush tlbs for E2&0 translation regime ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-32-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Flush tlb for ASID changes in EL2&0 translation... ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-31-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Add VHE timer register redirection and... ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-30-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Add VHE system register redirection and... ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-29-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update define_one_arm_cp_reg_with_opaque... ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-28-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update timer access for VHE ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-27-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Add the hypervisor virtual counter ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-26-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update ctr_el0_access for EL2 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-25-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update aa64_zva_access for EL2 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-24-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update arm_sctlr for VHE ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-23-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update arm_mmu_idx for VHE ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-22-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Add regime_has_2_ranges ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-21-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Reorganize ARMMMUIdx ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-20-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Tidy ARMMMUIdx m-profile definitions ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-19-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Rearrange ARMMMUIdxBit ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-18-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Expand TBFLAG_ANY.MMUIDX to 4 bits ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-17-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Recover 4 bits from TBFLAGs ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-16-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Rename ARMMMUIdx_S1E2 to ARMMMUIdx_E2 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-15-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Rename ARMMMUIdx*_S1E3 to ARMMMUIdx*_SE3 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-14-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Rename ARMMMUIdx_S1SE[01] to ARMMMUIdx_SE10_[01] ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-13-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Rename ARMMMUIdx_S1NSE* to ARMMMUIdx_Stage1_E* ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-12-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Rename ARMMMUIdx_S2NS to ARMMMUIdx_Stage2 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-11-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Rename ARMMMUIdx*_S12NSE* to ARMMMUIdx... ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-10-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Simplify tlb_force_broadcast alternatives ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-9-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Split out alle1_tlbmask ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-8-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Split out vae1_tlbmask ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-7-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Update CNTVCT_EL0 for VHE ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-6-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Add TTBR1_EL2 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-5-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Add CONTEXTIDR_EL2 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-4-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Enable HCR_E2H for VHE ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-3-richard.henderson@linaro.org |
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2020-02-07 | Richard Henderson | target/arm: Define isar_feature_aa64_vh ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200206105448.4726-2-richard.henderson@linaro.org |
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2020-02-03 | Richard Henderson | target/ppc: Use probe_write for DCBZ ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200129235040.24022-5-richard.henderson@linaro.org> |
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2020-02-03 | Richard Henderson | target/ppc: Remove redundant mask in DCBZ ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200129235040.24022-4-richard.henderson@linaro.org> |
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2020-02-03 | Richard Henderson | target/ppc: Use probe_access for LMW, STMW ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200129235040.24022-3-richard.henderson@linaro.org> |
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2020-02-03 | Richard Henderson | target/ppc: Use probe_access for LSW, STSW ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200129235040.24022-2-richard.henderson@linaro.org> |
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2020-01-27 | Richard Henderson | target/hppa: Allow, but diagnose, LDCW aligned only... ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-01-27 | Richard Henderson | target/s390x: Remove DisasFields argument from extract_insn ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200123232248.1800-6-richard.henderson@linaro.org> |
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2020-01-27 | Richard Henderson | target/s390x: Move DisasFields into DisasContext ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200123232248.1800-5-richard.henderson@linaro.org> |
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2020-01-27 | Richard Henderson | target/s390x: Pass DisasContext to get_field and have_field ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200123232248.1800-4-richard.henderson@linaro.org> |
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2020-01-27 | Richard Henderson | target/s390x: Remove DisasFields argument from callbacks ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200123232248.1800-3-richard.henderson@linaro.org> |
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2020-01-27 | Richard Henderson | target/s390x: Move struct DisasFields definition earlier ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200123232248.1800-2-richard.henderson@linaro.org> |
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2020-01-23 | Richard Henderson | tests/tcg/aarch64: Add pauth-4 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200116230809.19078-5-richard.henderson@linaro.org |
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2020-01-23 | Richard Henderson | tests/tcg/aarch64: Add pauth-3 ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200116230809.19078-4-richard.henderson@linaro.org |
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2020-01-23 | Richard Henderson | tests/tcg/aarch64: Fix compilation parameters for pauth-% ...off-by: Richard Henderson <richard.henderson@linaro.org> ...id: 20200116230809.19078-3-richard.henderson@linaro.org |
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2020-01-22 | Richard Henderson | linux-user: Reserve space for brk ...off-by: Richard Henderson <richard.henderson@linaro.org> ...Id: <20200117230245.5040-1-richard.henderson@linaro.org> |
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2020-01-22 | Richard Henderson | cputlb: Hoist timestamp outside of loops over tlbs ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-01-22 | Richard Henderson | cputlb: Initialize tlbs as flushed ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-01-22 | Richard Henderson | cputlb: Partially merge tlb_dyn_init into tlb_init ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-01-22 | Richard Henderson | cputlb: Split out tlb_mmu_flush_locked ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-01-22 | Richard Henderson | cputlb: Hoist tlb portions in tlb_flush_one_mmuidx_locked ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-01-22 | Richard Henderson | cputlb: Hoist tlb portions in tlb_mmu_resize_locked ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-01-22 | Richard Henderson | cputlb: Pass CPUTLBDescFast to tlb_n_entries and sizeof_tlb ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-01-22 | Richard Henderson | cputlb: Make tlb_n_entries private to cputlb.c ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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2020-01-22 | Richard Henderson | cputlb: Merge tlb_table_flush_by_mmuidx into tlb_flush_one_m... ...off-by: Richard Henderson <richard.henderson@linaro.org> |
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