| commit | f93c3a8d0c0c1038dbe1e957eb8ab92671137975 | |
| author | Leon Alrae <leon.alrae@imgtec.com> | |
| Thu, 19 Nov 2015 19:15:35 +0000 (19 19:15 +0000) | ||
| committer | Leon Alrae <leon.alrae@imgtec.com> | |
| Tue, 24 Nov 2015 11:01:03 +0000 (24 11:01 +0000) | ||
| tree | 00969bbc0675fd9851c1678f8c829846221e192c | treesnapshot (tar.gz zip) |
| parent | 7871abb94c2f4adc39f2487f6edf5e69ba872a65 | commitdiff |
target-mips: flush QEMU TLB when disabling 64-bit addressing
CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit
Kernel/Supervisor/User Segments. If bit is cleared an access to
corresponding segment should generate Address Error Exception.
However, the guest may still be able to access some pages belonging to
the disabled 64-bit segment because we forget to flush QEMU TLB.
This patch fixes it.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
CP0.Status.KX/SX/UX bits are responsible for enabling access to 64-bit
Kernel/Supervisor/User Segments. If bit is cleared an access to
corresponding segment should generate Address Error Exception.
However, the guest may still be able to access some pages belonging to
the disabled 64-bit segment because we forget to flush QEMU TLB.
This patch fixes it.
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| target-mips/cpu.h | diffblobblamehistory | |
| target-mips/op_helper.c | diffblobblamehistory |