| commit | c74ccb5dd6955736907256aab8229f63385a5e2e | |
| author | Francisco Iglesias <francisco.iglesias@xilinx.com> | |
| Thu, 3 Feb 2022 15:17:42 +0000 (3 15:17 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Tue, 8 Feb 2022 10:56:27 +0000 (8 10:56 +0000) | ||
| tree | 525b1a7aa3cf558399a4ec71345a016da9bdccb0 | treesnapshot (tar.gz zip) |
| parent | a7b66ada6e88aa9a9f420f1116569b2df47fa1ab | commitdiff |
hw/arm/xlnx-zynqmp: 'Or' the QSPI / QSPI DMA IRQs
'Or' the IRQs coming from the QSPI and QSPI DMA models. This is done for
avoiding the situation where one of the models incorrectly deasserts an
interrupt asserted from the other model (which will result in that the IRQ
is lost and will not reach guest SW).
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220203151742.1457-1-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
'Or' the IRQs coming from the QSPI and QSPI DMA models. This is done for
avoiding the situation where one of the models incorrectly deasserts an
interrupt asserted from the other model (which will result in that the IRQ
is lost and will not reach guest SW).
Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20220203151742.1457-1-francisco.iglesias@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| hw/arm/xlnx-zynqmp.c | diffblobblamehistory | |
| include/hw/arm/xlnx-zynqmp.h | diffblobblamehistory |