| commit | b6d1df64824d554d1e48133fdb535dbe89bc7d69 | |
| author | Joel Stanley <joel@jms.id.au> | |
| Fri, 18 Feb 2022 08:18:12 +0000 (18 09:18 +0100) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Sat, 26 Feb 2022 17:40:51 +0000 (26 18:40 +0100) | ||
| tree | f7ff7e1e7aa35c40c2eb68694581ef5a9f33180f | treesnapshot (tar.gz zip) |
| parent | bcb122f8bbb270ff2ce847b8c41c3105dd4bee2f | commitdiff |
aspeed: rainier: Add strap values taken from hardware
When time permits, we should introduce defines for the HW strapping
registers to cleanly decode the values.
SCU500 = 0x00422016
Disable ARM JTAG trusted world debug: 0x1
Disable ARM JTAG debug: 0x1
VGA Memory Size: 0x1 [16MB]
Cortex M3: 0x1 [Disabled]
Boot device: 0x1 [eMMC]
Reserved: 0x1
SCU510 = 0x80000848
Secure Boot Enable: 0x1
Enable boot SPI or eMMC ABR (second boot): 0x1
Enable LPC mode: 0x1 [LPC]
Disable LPC SuperIO 0x2e/0x4e: 0x1
Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: rewrote the commit log ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
When time permits, we should introduce defines for the HW strapping
registers to cleanly decode the values.
SCU500 = 0x00422016
Disable ARM JTAG trusted world debug: 0x1
Disable ARM JTAG debug: 0x1
VGA Memory Size: 0x1 [16MB]
Cortex M3: 0x1 [Disabled]
Boot device: 0x1 [eMMC]
Reserved: 0x1
SCU510 = 0x80000848
Secure Boot Enable: 0x1
Enable boot SPI or eMMC ABR (second boot): 0x1
Enable LPC mode: 0x1 [LPC]
Disable LPC SuperIO 0x2e/0x4e: 0x1
Signed-off-by: Joel Stanley <joel@jms.id.au>
[ clg: rewrote the commit log ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| hw/arm/aspeed.c | diffblobblamehistory |