target-i386: Fix SMSW and LMSW from/to register
SMSW and LMSW accept register operands, but commit
1906b2a ("target-i386:
Rearrange processing of 0F 01", 2016-02-13) did not account for that.
Fixes:
1906b2af7c2345037d9b2fdf484b457b5acd09d1
Reported-by: Hervé Poussineau <hpoussin@reactos.org>
Tested-by: Hervé Poussineau <hpoussin@reactos.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <
1456845134-18812-1-git-send-email-pbonzini@redhat.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>