| commit | 7e5157696b97a5431ef8786e01bffe989c05493b | |
| author | Frederic Barrat <fbarrat@linux.ibm.com> | |
| Mon, 4 Apr 2022 06:49:06 +0000 (4 08:49 +0200) | ||
| committer | Cédric Le Goater <clg@kaod.org> | |
| Mon, 4 Apr 2022 06:49:06 +0000 (4 08:49 +0200) | ||
| tree | ccccaf2aaa5d475cb5994d98abeba60317a6c743 | treesnapshot (tar.gz zip) |
| parent | ef95a244949a15b831876fe2d4e1320784729819 | commitdiff |
ppc/pnv: Fix number of registers in the PCIe controller on POWER9
The spec defines 3 registers, even though only index 0 and 2 are valid
on POWER9. The same model is used on POWER10. Register 1 is defined
there but we currently don't use it in skiboot. So we can keep
reporting an error on write.
Reported by Coverity (CID 1487176).
Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge")
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220401091925.770803-1-fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
The spec defines 3 registers, even though only index 0 and 2 are valid
on POWER9. The same model is used on POWER10. Register 1 is defined
there but we currently don't use it in skiboot. So we can keep
reporting an error on write.
Reported by Coverity (CID 1487176).
Fixes: 4f9924c4d4cf ("ppc/pnv: Add models for POWER9 PHB4 PCIe Host bridge")
Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <20220401091925.770803-1-fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| include/hw/pci-host/pnv_phb4.h | diffblobblamehistory |