| commit | 5e0c126aada959f1474ab633931e22d92869c44f | |
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Mon, 13 Dec 2021 10:06:07 +0000 (13 11:06 +0100) | ||
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | |
| Mon, 7 Mar 2022 19:34:17 +0000 (7 20:34 +0100) | ||
| tree | 49f055afb40b8d33191bf0649730becb9768acdc | treesnapshot (tar.gz zip) |
| parent | c8aeab3a09b51f828eaa50b994434dbfb3f626b8 | commitdiff |
target/mips: Remove duplicated MIPSCPU::cp0_count_rate
Since the previous commit 9ea89876f9d ("target/mips: Fix cycle
counter timing calculations"), MIPSCPU::cp0_count_rate is not
used anymore. We don't need it since it is already expressed
as mips_def_t::CCRes. Remove the duplicate and clean.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <>20211213102340.1847248-1-f4bug@amsat.org>
Since the previous commit 9ea89876f9d ("target/mips: Fix cycle
counter timing calculations"), MIPSCPU::cp0_count_rate is not
used anymore. We don't need it since it is already expressed
as mips_def_t::CCRes. Remove the duplicate and clean.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <>20211213102340.1847248-1-f4bug@amsat.org>
| target/mips/cpu.c | diffblobblamehistory | |
| target/mips/cpu.h | diffblobblamehistory | |
| target/mips/internal.h | diffblobblamehistory |