| commit | 51b385db586dafa4cd1f23413f0cbbf5ec2a256c | |
| author | Fabiano Rosas <farosas@linux.ibm.com> | |
| Tue, 1 Jun 2021 21:46:47 +0000 (1 18:46 -0300) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Thu, 3 Jun 2021 08:10:31 +0000 (3 18:10 +1000) | ||
| tree | ec3347b2e03fb1e3a8a2f7cccfe827cd5771d2f6 | treesnapshot (tar.gz zip) |
| parent | 0c87018c7c171a8fe0ed44b9aa931b364eec85f7 | commitdiff |
target/ppc: powerpc_excp: Consolidade TLB miss code
The only difference in the code for Instruction fetch, Data load and
Data store TLB miss errors is that when called from an unsupported
processor (i.e. not one of 602, 603, 603e, G2, 7x5 or 74xx), they
abort with a message specific to the operation type (insn fetch, data
load/store).
If a processor does not support those interrupts we should not be
registering them in init_excp_<proc> to begin with, so that error
message would never be used.
I'm leaving the message in for completeness, but making it generic and
consolidating the three interrupts into the same case statement body.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210601214649.785647-4-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
The only difference in the code for Instruction fetch, Data load and
Data store TLB miss errors is that when called from an unsupported
processor (i.e. not one of 602, 603, 603e, G2, 7x5 or 74xx), they
abort with a message specific to the operation type (insn fetch, data
load/store).
If a processor does not support those interrupts we should not be
registering them in init_excp_<proc> to begin with, so that error
message would never be used.
I'm leaving the message in for completeness, but making it generic and
consolidating the three interrupts into the same case statement body.
Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20210601214649.785647-4-farosas@linux.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target/ppc/excp_helper.c | diffblobblamehistory |