| commit | 21b786f607b11d888f90bbb8c3414500515d11e7 | |
| author | Simon Guo <wei.guo.simon@gmail.com> | |
| Mon, 5 Mar 2018 10:53:48 +0000 (5 18:53 +0800) | ||
| committer | David Gibson <david@gibson.dropbear.id.au> | |
| Tue, 6 Mar 2018 02:16:29 +0000 (6 13:16 +1100) | ||
| tree | e245e0c71a0b7f7c5bc1f0de6d5ba05034666f07 | treesnapshot (tar.gz zip) |
| parent | 9d9769c2082bc0bdb88d0f138c5aae562b0c1826 | commitdiff |
PowerPC: Add TS bits into msr_mask
During migration, after MSR bits is synced, cpu_post_load() will use
msr_mask to determine which PPC MSR bits will be applied into the target
side. Hardware Transaction Memory(HTM) has been supported since Power8,
but TS0/TS1 bit was not in msr_mask yet. That will prevent target KVM
from loading TM checkpointed values.
This patch adds TS bits into msr_mask for Power8, so that transactional
application can be migrated across qemu.
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
During migration, after MSR bits is synced, cpu_post_load() will use
msr_mask to determine which PPC MSR bits will be applied into the target
side. Hardware Transaction Memory(HTM) has been supported since Power8,
but TS0/TS1 bit was not in msr_mask yet. That will prevent target KVM
from loading TM checkpointed values.
This patch adds TS bits into msr_mask for Power8, so that transactional
application can be migrated across qemu.
Signed-off-by: Simon Guo <wei.guo.simon@gmail.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
| target/ppc/translate_init.c | diffblobblamehistory |