2 * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
4 * Copyright (c) 2020 Western Digital
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef HW_OPENTITAN_H
20 #define HW_OPENTITAN_H
22 #include "hw/riscv/riscv_hart.h"
23 #include "hw/intc/sifive_plic.h"
24 #include "hw/char/ibex_uart.h"
25 #include "hw/timer/ibex_timer.h"
26 #include "hw/ssi/ibex_spi_host.h"
27 #include "qom/object.h"
29 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
30 OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState
, RISCV_IBEX_SOC
)
35 OPENTITAN_NUM_SPI_HOSTS
,
38 struct LowRISCIbexSoCState
{
40 SysBusDevice parent_obj
;
43 RISCVHartArrayState cpus
;
47 IbexSPIHostState spi_host
[OPENTITAN_NUM_SPI_HOSTS
];
49 MemoryRegion flash_mem
;
51 MemoryRegion flash_alias
;
54 typedef struct OpenTitanState
{
56 SysBusDevice parent_obj
;
59 LowRISCIbexSoCState soc
;
66 IBEX_DEV_FLASH_VIRTUAL
,
93 IBEX_DEV_ALERT_HANDLER
,
100 IBEX_UART0_TX_WATERMARK_IRQ
= 1,
101 IBEX_UART0_RX_WATERMARK_IRQ
= 2,
102 IBEX_UART0_TX_EMPTY_IRQ
= 3,
103 IBEX_UART0_RX_OVERFLOW_IRQ
= 4,
104 IBEX_UART0_RX_FRAME_ERR_IRQ
= 5,
105 IBEX_UART0_RX_BREAK_ERR_IRQ
= 6,
106 IBEX_UART0_RX_TIMEOUT_IRQ
= 7,
107 IBEX_UART0_RX_PARITY_ERR_IRQ
= 8,
108 IBEX_TIMER_TIMEREXPIRED0_0
= 126,
109 IBEX_SPI_HOST0_ERR_IRQ
= 150,
110 IBEX_SPI_HOST0_SPI_EVENT_IRQ
= 151,
111 IBEX_SPI_HOST1_ERR_IRQ
= 152,
112 IBEX_SPI_HOST1_SPI_EVENT_IRQ
= 153,