2 * QEMU PowerMac CUDA device support
4 * Copyright (c) 2004-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #include "hw/ppc/mac.h"
27 #include "hw/input/adb.h"
28 #include "qemu/timer.h"
29 #include "sysemu/sysemu.h"
31 /* XXX: implement all timer modes */
36 /* debug CUDA packets */
37 //#define DEBUG_CUDA_PACKET
40 #define CUDA_DPRINTF(fmt, ...) \
41 do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0)
43 #define CUDA_DPRINTF(fmt, ...)
46 /* Bits in B data register: all active low */
47 #define TREQ 0x08 /* Transfer request (input) */
48 #define TACK 0x10 /* Transfer acknowledge (output) */
49 #define TIP 0x20 /* Transfer in progress (output) */
52 #define SR_CTRL 0x1c /* Shift register control bits */
53 #define SR_EXT 0x0c /* Shift on external clock */
54 #define SR_OUT 0x10 /* Shift out if 1 */
56 /* Bits in IFR and IER */
57 #define IER_SET 0x80 /* set bits in IER */
58 #define IER_CLR 0 /* clear bits in IER */
59 #define SR_INT 0x04 /* Shift register full/empty */
60 #define SR_DATA_INT 0x08
61 #define SR_CLOCK_INT 0x10
62 #define T1_INT 0x40 /* Timer 1 interrupt */
63 #define T2_INT 0x20 /* Timer 2 interrupt */
66 #define T1MODE 0xc0 /* Timer 1 mode */
67 #define T1MODE_CONT 0x40 /* continuous interrupts */
69 /* commands (1st byte) */
72 #define ERROR_PACKET 2
73 #define TIMER_PACKET 3
74 #define POWER_PACKET 4
75 #define MACIIC_PACKET 5
79 /* CUDA commands (2nd byte) */
80 #define CUDA_WARM_START 0x0
81 #define CUDA_AUTOPOLL 0x1
82 #define CUDA_GET_6805_ADDR 0x2
83 #define CUDA_GET_TIME 0x3
84 #define CUDA_GET_PRAM 0x7
85 #define CUDA_SET_6805_ADDR 0x8
86 #define CUDA_SET_TIME 0x9
87 #define CUDA_POWERDOWN 0xa
88 #define CUDA_POWERUP_TIME 0xb
89 #define CUDA_SET_PRAM 0xc
90 #define CUDA_MS_RESET 0xd
91 #define CUDA_SEND_DFAC 0xe
92 #define CUDA_BATTERY_SWAP_SENSE 0x10
93 #define CUDA_RESET_SYSTEM 0x11
94 #define CUDA_SET_IPL 0x12
95 #define CUDA_FILE_SERVER_FLAG 0x13
96 #define CUDA_SET_AUTO_RATE 0x14
97 #define CUDA_GET_AUTO_RATE 0x16
98 #define CUDA_SET_DEVICE_LIST 0x19
99 #define CUDA_GET_DEVICE_LIST 0x1a
100 #define CUDA_SET_ONE_SECOND_MODE 0x1b
101 #define CUDA_SET_POWER_MESSAGES 0x21
102 #define CUDA_GET_SET_IIC 0x22
103 #define CUDA_WAKEUP 0x23
104 #define CUDA_TIMER_TICKLE 0x24
105 #define CUDA_COMBINED_FORMAT_IIC 0x25
107 #define CUDA_TIMER_FREQ (4700000 / 6)
108 #define CUDA_ADB_POLL_FREQ 50
110 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
111 #define RTC_OFFSET 2082844800
114 #define CUDA_REG_B 0x00
115 #define CUDA_REG_A 0x01
116 #define CUDA_REG_DIRB 0x02
117 #define CUDA_REG_DIRA 0x03
118 #define CUDA_REG_T1CL 0x04
119 #define CUDA_REG_T1CH 0x05
120 #define CUDA_REG_T1LL 0x06
121 #define CUDA_REG_T1LH 0x07
122 #define CUDA_REG_T2CL 0x08
123 #define CUDA_REG_T2CH 0x09
124 #define CUDA_REG_SR 0x0a
125 #define CUDA_REG_ACR 0x0b
126 #define CUDA_REG_PCR 0x0c
127 #define CUDA_REG_IFR 0x0d
128 #define CUDA_REG_IER 0x0e
129 #define CUDA_REG_ANH 0x0f
131 static void cuda_update(CUDAState
*s
);
132 static void cuda_receive_packet_from_host(CUDAState
*s
,
133 const uint8_t *data
, int len
);
134 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
135 int64_t current_time
);
137 static void cuda_update_irq(CUDAState
*s
)
139 if (s
->ifr
& s
->ier
& (SR_INT
| T1_INT
| T2_INT
)) {
140 qemu_irq_raise(s
->irq
);
142 qemu_irq_lower(s
->irq
);
146 static uint64_t get_tb(uint64_t time
, uint64_t freq
)
148 return muldiv64(time
, freq
, get_ticks_per_sec());
151 static unsigned int get_counter(CUDATimer
*ti
)
154 unsigned int counter
;
156 uint64_t current_time
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
158 /* Reverse of the tb calculation algorithm that Mac OS X uses on bootup. */
159 tb_diff
= get_tb(current_time
, ti
->frequency
) - ti
->load_time
;
160 d
= (tb_diff
* 0xBF401675E5DULL
) / (ti
->frequency
<< 24);
162 if (ti
->index
== 0) {
163 /* the timer goes down from latch to -1 (period of latch + 2) */
164 if (d
<= (ti
->counter_value
+ 1)) {
165 counter
= (ti
->counter_value
- d
) & 0xffff;
167 counter
= (d
- (ti
->counter_value
+ 1)) % (ti
->latch
+ 2);
168 counter
= (ti
->latch
- counter
) & 0xffff;
171 counter
= (ti
->counter_value
- d
) & 0xffff;
176 static void set_counter(CUDAState
*s
, CUDATimer
*ti
, unsigned int val
)
178 CUDA_DPRINTF("T%d.counter=%d\n", 1 + ti
->index
, val
);
179 ti
->load_time
= get_tb(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
),
181 ti
->counter_value
= val
;
182 cuda_timer_update(s
, ti
, ti
->load_time
);
185 static int64_t get_next_irq_time(CUDATimer
*s
, int64_t current_time
)
187 int64_t d
, next_time
;
188 unsigned int counter
;
190 /* current counter value */
191 d
= muldiv64(current_time
- s
->load_time
,
192 CUDA_TIMER_FREQ
, get_ticks_per_sec());
193 /* the timer goes down from latch to -1 (period of latch + 2) */
194 if (d
<= (s
->counter_value
+ 1)) {
195 counter
= (s
->counter_value
- d
) & 0xffff;
197 counter
= (d
- (s
->counter_value
+ 1)) % (s
->latch
+ 2);
198 counter
= (s
->latch
- counter
) & 0xffff;
201 /* Note: we consider the irq is raised on 0 */
202 if (counter
== 0xffff) {
203 next_time
= d
+ s
->latch
+ 1;
204 } else if (counter
== 0) {
205 next_time
= d
+ s
->latch
+ 2;
207 next_time
= d
+ counter
;
209 CUDA_DPRINTF("latch=%d counter=%" PRId64
" delta_next=%" PRId64
"\n",
210 s
->latch
, d
, next_time
- d
);
211 next_time
= muldiv64(next_time
, get_ticks_per_sec(), CUDA_TIMER_FREQ
) +
213 if (next_time
<= current_time
)
214 next_time
= current_time
+ 1;
218 static void cuda_timer_update(CUDAState
*s
, CUDATimer
*ti
,
219 int64_t current_time
)
223 if (ti
->index
== 0 && (s
->acr
& T1MODE
) != T1MODE_CONT
) {
224 timer_del(ti
->timer
);
226 ti
->next_irq_time
= get_next_irq_time(ti
, current_time
);
227 timer_mod(ti
->timer
, ti
->next_irq_time
);
231 static void cuda_timer1(void *opaque
)
233 CUDAState
*s
= opaque
;
234 CUDATimer
*ti
= &s
->timers
[0];
236 cuda_timer_update(s
, ti
, ti
->next_irq_time
);
241 static void cuda_timer2(void *opaque
)
243 CUDAState
*s
= opaque
;
244 CUDATimer
*ti
= &s
->timers
[1];
246 cuda_timer_update(s
, ti
, ti
->next_irq_time
);
251 static void cuda_set_sr_int(void *opaque
)
253 CUDAState
*s
= opaque
;
255 CUDA_DPRINTF("CUDA: %s:%d\n", __func__
, __LINE__
);
260 static void cuda_delay_set_sr_int(CUDAState
*s
)
264 if (s
->dirb
== 0xff) {
265 /* Not in Mac OS, fire the IRQ directly */
270 CUDA_DPRINTF("CUDA: %s:%d\n", __func__
, __LINE__
);
272 expire
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + 300 * SCALE_US
;
273 timer_mod(s
->sr_delay_timer
, expire
);
276 static uint32_t cuda_readb(void *opaque
, hwaddr addr
)
278 CUDAState
*s
= opaque
;
281 addr
= (addr
>> 9) & 0xf;
296 val
= get_counter(&s
->timers
[0]) & 0xff;
301 val
= get_counter(&s
->timers
[0]) >> 8;
305 val
= s
->timers
[0].latch
& 0xff;
308 /* XXX: check this */
309 val
= (s
->timers
[0].latch
>> 8) & 0xff;
312 val
= get_counter(&s
->timers
[1]) & 0xff;
317 val
= get_counter(&s
->timers
[1]) >> 8;
321 s
->ifr
&= ~(SR_INT
| SR_CLOCK_INT
| SR_DATA_INT
);
332 if (s
->ifr
& s
->ier
) {
344 if (addr
!= CUDA_REG_IFR
|| val
!= 0) {
345 CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr
, val
);
351 static void cuda_writeb(void *opaque
, hwaddr addr
, uint32_t val
)
353 CUDAState
*s
= opaque
;
355 addr
= (addr
>> 9) & 0xf;
356 CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr
, val
);
373 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff00) | val
;
374 cuda_timer_update(s
, &s
->timers
[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
377 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff) | (val
<< 8);
379 set_counter(s
, &s
->timers
[0], s
->timers
[0].latch
);
382 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff00) | val
;
383 cuda_timer_update(s
, &s
->timers
[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
386 s
->timers
[0].latch
= (s
->timers
[0].latch
& 0xff) | (val
<< 8);
388 cuda_timer_update(s
, &s
->timers
[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
391 s
->timers
[1].latch
= (s
->timers
[1].latch
& 0xff00) | val
;
394 /* To ensure T2 generates an interrupt on zero crossing with the
395 common timer code, write the value directly from the latch to
397 s
->timers
[1].latch
= (s
->timers
[1].latch
& 0xff) | (val
<< 8);
399 set_counter(s
, &s
->timers
[1], s
->timers
[1].latch
);
406 cuda_timer_update(s
, &s
->timers
[0], qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
420 s
->ier
|= val
& 0x7f;
434 /* NOTE: TIP and TREQ are negated */
435 static void cuda_update(CUDAState
*s
)
437 int packet_received
, len
;
441 /* transfer requested from host */
443 if (s
->acr
& SR_OUT
) {
445 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
446 if (s
->data_out_index
< sizeof(s
->data_out
)) {
447 CUDA_DPRINTF("send: %02x\n", s
->sr
);
448 s
->data_out
[s
->data_out_index
++] = s
->sr
;
449 cuda_delay_set_sr_int(s
);
453 if (s
->data_in_index
< s
->data_in_size
) {
455 if ((s
->b
& (TACK
| TIP
)) != (s
->last_b
& (TACK
| TIP
))) {
456 s
->sr
= s
->data_in
[s
->data_in_index
++];
457 CUDA_DPRINTF("recv: %02x\n", s
->sr
);
458 /* indicate end of transfer */
459 if (s
->data_in_index
>= s
->data_in_size
) {
460 s
->b
= (s
->b
| TREQ
);
462 cuda_delay_set_sr_int(s
);
467 /* no transfer requested: handle sync case */
468 if ((s
->last_b
& TIP
) && (s
->b
& TACK
) != (s
->last_b
& TACK
)) {
469 /* update TREQ state each time TACK change state */
471 s
->b
= (s
->b
| TREQ
);
473 s
->b
= (s
->b
& ~TREQ
);
474 cuda_delay_set_sr_int(s
);
476 if (!(s
->last_b
& TIP
)) {
477 /* handle end of host to cuda transfer */
478 packet_received
= (s
->data_out_index
> 0);
479 /* always an IRQ at the end of transfer */
480 cuda_delay_set_sr_int(s
);
482 /* signal if there is data to read */
483 if (s
->data_in_index
< s
->data_in_size
) {
484 s
->b
= (s
->b
& ~TREQ
);
489 s
->last_acr
= s
->acr
;
492 /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
494 if (packet_received
) {
495 len
= s
->data_out_index
;
496 s
->data_out_index
= 0;
497 cuda_receive_packet_from_host(s
, s
->data_out
, len
);
501 static void cuda_send_packet_to_host(CUDAState
*s
,
502 const uint8_t *data
, int len
)
504 #ifdef DEBUG_CUDA_PACKET
507 printf("cuda_send_packet_to_host:\n");
508 for(i
= 0; i
< len
; i
++)
509 printf(" %02x", data
[i
]);
513 memcpy(s
->data_in
, data
, len
);
514 s
->data_in_size
= len
;
515 s
->data_in_index
= 0;
517 cuda_delay_set_sr_int(s
);
520 static void cuda_adb_poll(void *opaque
)
522 CUDAState
*s
= opaque
;
523 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 2];
526 olen
= adb_poll(&s
->adb_bus
, obuf
+ 2);
528 obuf
[0] = ADB_PACKET
;
529 obuf
[1] = 0x40; /* polled data */
530 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
532 timer_mod(s
->adb_poll_timer
,
533 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
534 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ
));
537 static void cuda_receive_packet(CUDAState
*s
,
538 const uint8_t *data
, int len
)
540 uint8_t obuf
[16] = { CUDA_PACKET
, 0, data
[0] };
546 autopoll
= (data
[1] != 0);
547 if (autopoll
!= s
->autopoll
) {
548 s
->autopoll
= autopoll
;
550 timer_mod(s
->adb_poll_timer
,
551 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) +
552 (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ
));
554 timer_del(s
->adb_poll_timer
);
557 cuda_send_packet_to_host(s
, obuf
, 3);
559 case CUDA_GET_6805_ADDR
:
560 cuda_send_packet_to_host(s
, obuf
, 3);
563 ti
= (((uint32_t)data
[1]) << 24) + (((uint32_t)data
[2]) << 16) + (((uint32_t)data
[3]) << 8) + data
[4];
564 s
->tick_offset
= ti
- (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / get_ticks_per_sec());
565 cuda_send_packet_to_host(s
, obuf
, 3);
568 ti
= s
->tick_offset
+ (qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) / get_ticks_per_sec());
573 cuda_send_packet_to_host(s
, obuf
, 7);
575 case CUDA_FILE_SERVER_FLAG
:
576 case CUDA_SET_DEVICE_LIST
:
577 case CUDA_SET_AUTO_RATE
:
578 case CUDA_SET_POWER_MESSAGES
:
579 cuda_send_packet_to_host(s
, obuf
, 3);
582 cuda_send_packet_to_host(s
, obuf
, 3);
583 qemu_system_shutdown_request();
585 case CUDA_RESET_SYSTEM
:
586 cuda_send_packet_to_host(s
, obuf
, 3);
587 qemu_system_reset_request();
589 case CUDA_COMBINED_FORMAT_IIC
:
590 obuf
[0] = ERROR_PACKET
;
592 obuf
[2] = CUDA_PACKET
;
594 cuda_send_packet_to_host(s
, obuf
, 4);
596 case CUDA_GET_SET_IIC
:
598 cuda_send_packet_to_host(s
, obuf
, 3);
600 obuf
[0] = ERROR_PACKET
;
602 obuf
[2] = CUDA_PACKET
;
604 cuda_send_packet_to_host(s
, obuf
, 4);
612 static void cuda_receive_packet_from_host(CUDAState
*s
,
613 const uint8_t *data
, int len
)
615 #ifdef DEBUG_CUDA_PACKET
618 printf("cuda_receive_packet_from_host:\n");
619 for(i
= 0; i
< len
; i
++)
620 printf(" %02x", data
[i
]);
627 uint8_t obuf
[ADB_MAX_OUT_LEN
+ 3];
629 olen
= adb_request(&s
->adb_bus
, obuf
+ 2, data
+ 1, len
- 1);
631 obuf
[0] = ADB_PACKET
;
633 cuda_send_packet_to_host(s
, obuf
, olen
+ 2);
636 obuf
[0] = ADB_PACKET
;
640 cuda_send_packet_to_host(s
, obuf
, olen
+ 3);
645 cuda_receive_packet(s
, data
+ 1, len
- 1);
650 static void cuda_writew (void *opaque
, hwaddr addr
, uint32_t value
)
654 static void cuda_writel (void *opaque
, hwaddr addr
, uint32_t value
)
658 static uint32_t cuda_readw (void *opaque
, hwaddr addr
)
663 static uint32_t cuda_readl (void *opaque
, hwaddr addr
)
668 static const MemoryRegionOps cuda_ops
= {
681 .endianness
= DEVICE_NATIVE_ENDIAN
,
684 static bool cuda_timer_exist(void *opaque
, int version_id
)
686 CUDATimer
*s
= opaque
;
688 return s
->timer
!= NULL
;
691 static const VMStateDescription vmstate_cuda_timer
= {
692 .name
= "cuda_timer",
694 .minimum_version_id
= 0,
695 .fields
= (VMStateField
[]) {
696 VMSTATE_UINT16(latch
, CUDATimer
),
697 VMSTATE_UINT16(counter_value
, CUDATimer
),
698 VMSTATE_INT64(load_time
, CUDATimer
),
699 VMSTATE_INT64(next_irq_time
, CUDATimer
),
700 VMSTATE_TIMER_PTR_TEST(timer
, CUDATimer
, cuda_timer_exist
),
701 VMSTATE_END_OF_LIST()
705 static const VMStateDescription vmstate_cuda
= {
708 .minimum_version_id
= 2,
709 .fields
= (VMStateField
[]) {
710 VMSTATE_UINT8(a
, CUDAState
),
711 VMSTATE_UINT8(b
, CUDAState
),
712 VMSTATE_UINT8(dira
, CUDAState
),
713 VMSTATE_UINT8(dirb
, CUDAState
),
714 VMSTATE_UINT8(sr
, CUDAState
),
715 VMSTATE_UINT8(acr
, CUDAState
),
716 VMSTATE_UINT8(pcr
, CUDAState
),
717 VMSTATE_UINT8(ifr
, CUDAState
),
718 VMSTATE_UINT8(ier
, CUDAState
),
719 VMSTATE_UINT8(anh
, CUDAState
),
720 VMSTATE_INT32(data_in_size
, CUDAState
),
721 VMSTATE_INT32(data_in_index
, CUDAState
),
722 VMSTATE_INT32(data_out_index
, CUDAState
),
723 VMSTATE_UINT8(autopoll
, CUDAState
),
724 VMSTATE_BUFFER(data_in
, CUDAState
),
725 VMSTATE_BUFFER(data_out
, CUDAState
),
726 VMSTATE_UINT32(tick_offset
, CUDAState
),
727 VMSTATE_STRUCT_ARRAY(timers
, CUDAState
, 2, 1,
728 vmstate_cuda_timer
, CUDATimer
),
729 VMSTATE_TIMER_PTR(adb_poll_timer
, CUDAState
),
730 VMSTATE_END_OF_LIST()
734 static void cuda_reset(DeviceState
*dev
)
736 CUDAState
*s
= CUDA(dev
);
747 // s->ier = T1_INT | SR_INT;
750 s
->data_in_index
= 0;
751 s
->data_out_index
= 0;
754 s
->timers
[0].latch
= 0xffff;
755 set_counter(s
, &s
->timers
[0], 0xffff);
757 s
->timers
[1].latch
= 0xffff;
759 s
->sr_delay_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cuda_set_sr_int
, s
);
762 static void cuda_realizefn(DeviceState
*dev
, Error
**errp
)
764 CUDAState
*s
= CUDA(dev
);
767 s
->timers
[0].timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cuda_timer1
, s
);
768 s
->timers
[0].frequency
= s
->frequency
;
769 s
->timers
[1].timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cuda_timer2
, s
);
770 s
->timers
[1].frequency
= (SCALE_US
* 6000) / 4700;
772 qemu_get_timedate(&tm
, 0);
773 s
->tick_offset
= (uint32_t)mktimegm(&tm
) + RTC_OFFSET
;
775 s
->adb_poll_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, cuda_adb_poll
, s
);
778 static void cuda_initfn(Object
*obj
)
780 SysBusDevice
*d
= SYS_BUS_DEVICE(obj
);
781 CUDAState
*s
= CUDA(obj
);
784 memory_region_init_io(&s
->mem
, obj
, &cuda_ops
, s
, "cuda", 0x2000);
785 sysbus_init_mmio(d
, &s
->mem
);
786 sysbus_init_irq(d
, &s
->irq
);
788 for (i
= 0; i
< ARRAY_SIZE(s
->timers
); i
++) {
789 s
->timers
[i
].index
= i
;
792 qbus_create_inplace(&s
->adb_bus
, sizeof(s
->adb_bus
), TYPE_ADB_BUS
,
793 DEVICE(obj
), "adb.0");
796 static Property cuda_properties
[] = {
797 DEFINE_PROP_UINT64("frequency", CUDAState
, frequency
, 0),
798 DEFINE_PROP_END_OF_LIST()
801 static void cuda_class_init(ObjectClass
*oc
, void *data
)
803 DeviceClass
*dc
= DEVICE_CLASS(oc
);
805 dc
->realize
= cuda_realizefn
;
806 dc
->reset
= cuda_reset
;
807 dc
->vmsd
= &vmstate_cuda
;
808 dc
->props
= cuda_properties
;
809 set_bit(DEVICE_CATEGORY_BRIDGE
, dc
->categories
);
812 static const TypeInfo cuda_type_info
= {
814 .parent
= TYPE_SYS_BUS_DEVICE
,
815 .instance_size
= sizeof(CUDAState
),
816 .instance_init
= cuda_initfn
,
817 .class_init
= cuda_class_init
,
820 static void cuda_register_types(void)
822 type_register_static(&cuda_type_info
);
825 type_init(cuda_register_types
)