hw/arm/raspi.c

   1 /*
   2  * Raspberry Pi emulation (c) 2012 Gregory Estrade
   3  * Upstreaming code cleanup [including bcm2835_*] (c) 2013 Jan Petrous
   4  *
   5  * Rasperry Pi 2 emulation Copyright (c) 2015, Microsoft
   6  * Written by Andrew Baumann
   7  *
   8  * Raspberry Pi 3 emulation Copyright (c) 2018 Zoltán Baldaszti
   9  * Upstream code cleanup (c) 2018 Pekka Enberg
  10  *
  11  * This code is licensed under the GNU GPLv2 and later.
  12  */
  13
  14 #include "qemu/osdep.h"
  15 #include "qemu/units.h"
  16 #include "qemu/cutils.h"
  17 #include "qapi/error.h"
  18 #include "cpu.h"
  19 #include "hw/arm/bcm2836.h"
  20 #include "hw/registerfields.h"
  21 #include "qemu/error-report.h"
  22 #include "hw/boards.h"
  23 #include "hw/loader.h"
  24 #include "hw/arm/boot.h"
  25 #include "sysemu/sysemu.h"
  26
  27 #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
  28 #define MVBAR_ADDR      0x400 /* secure vectors */
  29 #define BOARDSETUP_ADDR (MVBAR_ADDR + 0x20) /* board setup code */
  30 #define FIRMWARE_ADDR_2 0x8000 /* Pi 2 loads kernel.img here by default */
  31 #define FIRMWARE_ADDR_3 0x80000 /* Pi 3 loads kernel.img here by default */
  32 #define SPINTABLE_ADDR  0xd8 /* Pi 3 bootloader spintable */
  33
  34 /* Registered machine type (matches RPi Foundation bootloader and U-Boot) */
  35 #define MACH_TYPE_BCM2708   3138
  36
  37 typedef struct RasPiState {
  38     BCM283XState soc;
  39     MemoryRegion ram;
  40 } RasPiState;
  41
  42 /*
  43  * Board revision codes:
  44  * www.raspberrypi.org/documentation/hardware/raspberrypi/revision-codes/
  45  */
  46 FIELD(REV_CODE, REVISION,           0, 4);
  47 FIELD(REV_CODE, TYPE,               4, 8);
  48 FIELD(REV_CODE, PROCESSOR,         12, 4);
  49 FIELD(REV_CODE, MANUFACTURER,      16, 4);
  50 FIELD(REV_CODE, MEMORY_SIZE,       20, 3);
  51 FIELD(REV_CODE, STYLE,             23, 1);
  52
  53 static uint64_t board_ram_size(uint32_t board_rev)
  54 {
  55     assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
  56     return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
  57 }
  58
  59 static int board_processor_id(uint32_t board_rev)
  60 {
  61     assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
  62     return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
  63 }
  64
  65 static int board_version(uint32_t board_rev)
  66 {
  67     return board_processor_id(board_rev) + 1;
  68 }
  69
  70 static const char *board_soc_type(uint32_t board_rev)
  71 {
  72     static const char *soc_types[] = {
  73         NULL, TYPE_BCM2836, TYPE_BCM2837,
  74     };
  75     int proc_id = board_processor_id(board_rev);
  76
  77     if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
  78         error_report("Unsupported processor id '%d' (board revision: 0x%x)",
  79                      proc_id, board_rev);
  80         exit(1);
  81     }
  82     return soc_types[proc_id];
  83 }
  84
  85 static void write_smpboot(ARMCPU *cpu, const struct arm_boot_info *info)
  86 {
  87     static const uint32_t smpboot[] = {
  88         0xe1a0e00f, /*    mov     lr, pc */
  89         0xe3a0fe00 + (BOARDSETUP_ADDR >> 4), /* mov pc, BOARDSETUP_ADDR */
  90         0xee100fb0, /*    mrc     p15, 0, r0, c0, c0, 5;get core ID */
  91         0xe7e10050, /*    ubfx    r0, r0, #0, #2       ;extract LSB */
  92         0xe59f5014, /*    ldr     r5, =0x400000CC      ;load mbox base */
  93         0xe320f001, /* 1: yield */
  94         0xe7953200, /*    ldr     r3, [r5, r0, lsl #4] ;read mbox for our core*/
  95         0xe3530000, /*    cmp     r3, #0               ;spin while zero */
  96         0x0afffffb, /*    beq     1b */
  97         0xe7853200, /*    str     r3, [r5, r0, lsl #4] ;clear mbox */
  98         0xe12fff13, /*    bx      r3                   ;jump to target */
  99         0x400000cc, /* (constant: mailbox 3 read/clear base) */
 100     };
 101
 102     /* check that we don't overrun board setup vectors */
 103     QEMU_BUILD_BUG_ON(SMPBOOT_ADDR + sizeof(smpboot) > MVBAR_ADDR);
 104     /* check that board setup address is correctly relocated */
 105     QEMU_BUILD_BUG_ON((BOARDSETUP_ADDR & 0xf) != 0
 106                       || (BOARDSETUP_ADDR >> 4) >= 0x100);
 107
 108     rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
 109                           info->smp_loader_start,
 110                           arm_boot_address_space(cpu, info));
 111 }
 112
 113 static void write_smpboot64(ARMCPU *cpu, const struct arm_boot_info *info)
 114 {
 115     AddressSpace *as = arm_boot_address_space(cpu, info);
 116     /* Unlike the AArch32 version we don't need to call the board setup hook.
 117      * The mechanism for doing the spin-table is also entirely different.
 118      * We must have four 64-bit fields at absolute addresses
 119      * 0xd8, 0xe0, 0xe8, 0xf0 in RAM, which are the flag variables for
 120      * our CPUs, and which we must ensure are zero initialized before
 121      * the primary CPU goes into the kernel. We put these variables inside
 122      * a rom blob, so that the reset for ROM contents zeroes them for us.
 123      */
 124     static const uint32_t smpboot[] = {
 125         0xd2801b05, /*        mov     x5, 0xd8 */
 126         0xd53800a6, /*        mrs     x6, mpidr_el1 */
 127         0x924004c6, /*        and     x6, x6, #0x3 */
 128         0xd503205f, /* spin:  wfe */
 129         0xf86678a4, /*        ldr     x4, [x5,x6,lsl #3] */
 130         0xb4ffffc4, /*        cbz     x4, spin */
 131         0xd2800000, /*        mov     x0, #0x0 */
 132         0xd2800001, /*        mov     x1, #0x0 */
 133         0xd2800002, /*        mov     x2, #0x0 */
 134         0xd2800003, /*        mov     x3, #0x0 */
 135         0xd61f0080, /*        br      x4 */
 136     };
 137
 138     static const uint64_t spintables[] = {
 139         0, 0, 0, 0
 140     };
 141
 142     rom_add_blob_fixed_as("raspi_smpboot", smpboot, sizeof(smpboot),
 143                           info->smp_loader_start, as);
 144     rom_add_blob_fixed_as("raspi_spintables", spintables, sizeof(spintables),
 145                           SPINTABLE_ADDR, as);
 146 }
 147
 148 static void write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info)
 149 {
 150     arm_write_secure_board_setup_dummy_smc(cpu, info, MVBAR_ADDR);
 151 }
 152
 153 static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
 154 {
 155     CPUState *cs = CPU(cpu);
 156     cpu_set_pc(cs, info->smp_loader_start);
 157 }
 158
 159 static void setup_boot(MachineState *machine, int version, size_t ram_size)
 160 {
 161     static struct arm_boot_info binfo;
 162     int r;
 163
 164     binfo.board_id = MACH_TYPE_BCM2708;
 165     binfo.ram_size = ram_size;
 166     binfo.nb_cpus = machine->smp.cpus;
 167
 168     if (version <= 2) {
 169         /* The rpi1 and 2 require some custom setup code to run in Secure
 170          * mode before booting a kernel (to set up the SMC vectors so
 171          * that we get a no-op SMC; this is used by Linux to call the
 172          * firmware for some cache maintenance operations.
 173          * The rpi3 doesn't need this.
 174          */
 175         binfo.board_setup_addr = BOARDSETUP_ADDR;
 176         binfo.write_board_setup = write_board_setup;
 177         binfo.secure_board_setup = true;
 178         binfo.secure_boot = true;
 179     }
 180
 181     /* Pi2 and Pi3 requires SMP setup */
 182     if (version >= 2) {
 183         binfo.smp_loader_start = SMPBOOT_ADDR;
 184         if (version == 2) {
 185             binfo.write_secondary_boot = write_smpboot;
 186         } else {
 187             binfo.write_secondary_boot = write_smpboot64;
 188         }
 189         binfo.secondary_cpu_reset_hook = reset_secondary;
 190     }
 191
 192     /* If the user specified a "firmware" image (e.g. UEFI), we bypass
 193      * the normal Linux boot process
 194      */
 195     if (machine->firmware) {
 196         hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
 197         /* load the firmware image (typically kernel.img) */
 198         r = load_image_targphys(machine->firmware, firmware_addr,
 199                                 ram_size - firmware_addr);
 200         if (r < 0) {
 201             error_report("Failed to load firmware from %s", machine->firmware);
 202             exit(1);
 203         }
 204
 205         binfo.entry = firmware_addr;
 206         binfo.firmware_loaded = true;
 207     }
 208
 209     arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
 210 }
 211
 212 static void raspi_init(MachineState *machine, uint32_t board_rev)
 213 {
 214     RasPiState *s = g_new0(RasPiState, 1);
 215     int version = board_version(board_rev);
 216     uint64_t ram_size = board_ram_size(board_rev);
 217     uint32_t vcram_size;
 218     DriveInfo *di;
 219     BlockBackend *blk;
 220     BusState *bus;
 221     DeviceState *carddev;
 222
 223     if (machine->ram_size != ram_size) {
 224         char *size_str = size_to_str(ram_size);
 225         error_report("Invalid RAM size, should be %s", size_str);
 226         g_free(size_str);
 227         exit(1);
 228     }
 229
 230     /* Allocate and map RAM */
 231     memory_region_allocate_system_memory(&s->ram, OBJECT(machine), "ram",
 232                                          machine->ram_size);
 233     /* FIXME: Remove when we have custom CPU address space support */
 234     memory_region_add_subregion_overlap(get_system_memory(), 0, &s->ram, 0);
 235
 236     /* Setup the SOC */
 237     object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc),
 238                             board_soc_type(board_rev), &error_abort, NULL);
 239     object_property_add_const_link(OBJECT(&s->soc), "ram", OBJECT(&s->ram),
 240                                    &error_abort);
 241     object_property_set_int(OBJECT(&s->soc), board_rev, "board-rev",
 242                             &error_abort);
 243     object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort);
 244
 245     /* Create and plug in the SD cards */
 246     di = drive_get_next(IF_SD);
 247     blk = di ? blk_by_legacy_dinfo(di) : NULL;
 248     bus = qdev_get_child_bus(DEVICE(&s->soc), "sd-bus");
 249     if (bus == NULL) {
 250         error_report("No SD bus found in SOC object");
 251         exit(1);
 252     }
 253     carddev = qdev_create(bus, TYPE_SD_CARD);
 254     qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
 255     object_property_set_bool(OBJECT(carddev), true, "realized", &error_fatal);
 256
 257     vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
 258                                           &error_abort);
 259     setup_boot(machine, version, machine->ram_size - vcram_size);
 260 }
 261
 262 static void raspi2_init(MachineState *machine)
 263 {
 264     raspi_init(machine, 0xa21041);
 265 }
 266
 267 static void raspi2_machine_init(MachineClass *mc)
 268 {
 269     mc->desc = "Raspberry Pi 2B";
 270     mc->init = raspi2_init;
 271     mc->block_default_type = IF_SD;
 272     mc->no_parallel = 1;
 273     mc->no_floppy = 1;
 274     mc->no_cdrom = 1;
 275     mc->max_cpus = BCM283X_NCPUS;
 276     mc->min_cpus = BCM283X_NCPUS;
 277     mc->default_cpus = BCM283X_NCPUS;
 278     mc->default_ram_size = 1 * GiB;
 279     mc->ignore_memory_transaction_failures = true;
 280 };
 281 DEFINE_MACHINE("raspi2", raspi2_machine_init)
 282
 283 #ifdef TARGET_AARCH64
 284 static void raspi3_init(MachineState *machine)
 285 {
 286     raspi_init(machine, 0xa02082);
 287 }
 288
 289 static void raspi3_machine_init(MachineClass *mc)
 290 {
 291     mc->desc = "Raspberry Pi 3B";
 292     mc->init = raspi3_init;
 293     mc->block_default_type = IF_SD;
 294     mc->no_parallel = 1;
 295     mc->no_floppy = 1;
 296     mc->no_cdrom = 1;
 297     mc->max_cpus = BCM283X_NCPUS;
 298     mc->min_cpus = BCM283X_NCPUS;
 299     mc->default_cpus = BCM283X_NCPUS;
 300     mc->default_ram_size = 1 * GiB;
 301 }
 302 DEFINE_MACHINE("raspi3", raspi3_machine_init)
 303 #endif