hw/pci-bridge/pci_expander_bridge.c

   1 /*
   2  * PCI Expander Bridge Device Emulation
   3  *
   4  * Copyright (C) 2015 Red Hat Inc
   5  *
   6  * Authors:
   7  *   Marcel Apfelbaum <marcel@redhat.com>
   8  *
   9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  10  * See the COPYING file in the top-level directory.
  11  */
  12
  13 #include "qemu/osdep.h"
  14 #include "qapi/error.h"
  15 #include "hw/pci/pci.h"
  16 #include "hw/pci/pci_bus.h"
  17 #include "hw/pci/pci_host.h"
  18 #include "hw/qdev-properties.h"
  19 #include "hw/pci/pci_bridge.h"
  20 #include "hw/pci-bridge/pci_expander_bridge.h"
  21 #include "hw/cxl/cxl.h"
  22 #include "qemu/range.h"
  23 #include "qemu/error-report.h"
  24 #include "qemu/module.h"
  25 #include "sysemu/numa.h"
  26 #include "hw/boards.h"
  27 #include "qom/object.h"
  28
  29 enum BusType { PCI, PCIE, CXL };
  30
  31 #define TYPE_PXB_BUS "pxb-bus"
  32 typedef struct PXBBus PXBBus;
  33 DECLARE_INSTANCE_CHECKER(PXBBus, PXB_BUS,
  34                          TYPE_PXB_BUS)
  35
  36 #define TYPE_PXB_PCIE_BUS "pxb-pcie-bus"
  37 DECLARE_INSTANCE_CHECKER(PXBBus, PXB_PCIE_BUS,
  38                          TYPE_PXB_PCIE_BUS)
  39
  40 #define TYPE_PXB_CXL_BUS "pxb-cxl-bus"
  41 DECLARE_INSTANCE_CHECKER(PXBBus, PXB_CXL_BUS,
  42                          TYPE_PXB_CXL_BUS)
  43
  44 struct PXBBus {
  45     /*< private >*/
  46     PCIBus parent_obj;
  47     /*< public >*/
  48
  49     char bus_path[8];
  50 };
  51
  52 #define TYPE_PXB_DEVICE "pxb"
  53 DECLARE_INSTANCE_CHECKER(PXBDev, PXB_DEV,
  54                          TYPE_PXB_DEVICE)
  55
  56 #define TYPE_PXB_PCIE_DEVICE "pxb-pcie"
  57 DECLARE_INSTANCE_CHECKER(PXBDev, PXB_PCIE_DEV,
  58                          TYPE_PXB_PCIE_DEVICE)
  59
  60 static PXBDev *convert_to_pxb(PCIDevice *dev)
  61 {
  62     /* A CXL PXB's parent bus is PCIe, so the normal check won't work */
  63     if (object_dynamic_cast(OBJECT(dev), TYPE_PXB_CXL_DEVICE)) {
  64         return PXB_CXL_DEV(dev);
  65     }
  66
  67     return pci_bus_is_express(pci_get_bus(dev))
  68         ? PXB_PCIE_DEV(dev) : PXB_DEV(dev);
  69 }
  70
  71 static GList *pxb_dev_list;
  72
  73 #define TYPE_PXB_HOST "pxb-host"
  74
  75 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb)
  76 {
  77     CXLHost *host = PXB_CXL_HOST(hb);
  78
  79     return &host->cxl_cstate;
  80 }
  81
  82 static int pxb_bus_num(PCIBus *bus)
  83 {
  84     PXBDev *pxb = convert_to_pxb(bus->parent_dev);
  85
  86     return pxb->bus_nr;
  87 }
  88
  89 static uint16_t pxb_bus_numa_node(PCIBus *bus)
  90 {
  91     PXBDev *pxb = convert_to_pxb(bus->parent_dev);
  92
  93     return pxb->numa_node;
  94 }
  95
  96 static void pxb_bus_class_init(ObjectClass *class, void *data)
  97 {
  98     PCIBusClass *pbc = PCI_BUS_CLASS(class);
  99
 100     pbc->bus_num = pxb_bus_num;
 101     pbc->numa_node = pxb_bus_numa_node;
 102 }
 103
 104 static const TypeInfo pxb_bus_info = {
 105     .name          = TYPE_PXB_BUS,
 106     .parent        = TYPE_PCI_BUS,
 107     .instance_size = sizeof(PXBBus),
 108     .class_init    = pxb_bus_class_init,
 109 };
 110
 111 static const TypeInfo pxb_pcie_bus_info = {
 112     .name          = TYPE_PXB_PCIE_BUS,
 113     .parent        = TYPE_PCIE_BUS,
 114     .instance_size = sizeof(PXBBus),
 115     .class_init    = pxb_bus_class_init,
 116 };
 117
 118 static const TypeInfo pxb_cxl_bus_info = {
 119     .name          = TYPE_PXB_CXL_BUS,
 120     .parent        = TYPE_CXL_BUS,
 121     .instance_size = sizeof(PXBBus),
 122     .class_init    = pxb_bus_class_init,
 123 };
 124
 125 static const char *pxb_host_root_bus_path(PCIHostState *host_bridge,
 126                                           PCIBus *rootbus)
 127 {
 128     PXBBus *bus = pci_bus_is_cxl(rootbus) ?
 129                       PXB_CXL_BUS(rootbus) :
 130                       pci_bus_is_express(rootbus) ? PXB_PCIE_BUS(rootbus) :
 131                                                     PXB_BUS(rootbus);
 132
 133     snprintf(bus->bus_path, 8, "0000:%02x", pxb_bus_num(rootbus));
 134     return bus->bus_path;
 135 }
 136
 137 static char *pxb_host_ofw_unit_address(const SysBusDevice *dev)
 138 {
 139     const PCIHostState *pxb_host;
 140     const PCIBus *pxb_bus;
 141     const PXBDev *pxb_dev;
 142     int position;
 143     const DeviceState *pxb_dev_base;
 144     const PCIHostState *main_host;
 145     const SysBusDevice *main_host_sbd;
 146
 147     pxb_host = PCI_HOST_BRIDGE(dev);
 148     pxb_bus = pxb_host->bus;
 149     pxb_dev = convert_to_pxb(pxb_bus->parent_dev);
 150     position = g_list_index(pxb_dev_list, pxb_dev);
 151     assert(position >= 0);
 152
 153     pxb_dev_base = DEVICE(pxb_dev);
 154     main_host = PCI_HOST_BRIDGE(pxb_dev_base->parent_bus->parent);
 155     main_host_sbd = SYS_BUS_DEVICE(main_host);
 156
 157     if (main_host_sbd->num_mmio > 0) {
 158         return g_strdup_printf(HWADDR_FMT_plx ",%x",
 159                                main_host_sbd->mmio[0].addr, position + 1);
 160     }
 161     if (main_host_sbd->num_pio > 0) {
 162         return g_strdup_printf("i%04x,%x",
 163                                main_host_sbd->pio[0], position + 1);
 164     }
 165     return NULL;
 166 }
 167
 168 static void pxb_host_class_init(ObjectClass *class, void *data)
 169 {
 170     DeviceClass *dc = DEVICE_CLASS(class);
 171     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(class);
 172     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class);
 173
 174     dc->fw_name = "pci";
 175     /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */
 176     dc->user_creatable = false;
 177     sbc->explicit_ofw_unit_address = pxb_host_ofw_unit_address;
 178     hc->root_bus_path = pxb_host_root_bus_path;
 179 }
 180
 181 static const TypeInfo pxb_host_info = {
 182     .name          = TYPE_PXB_HOST,
 183     .parent        = TYPE_PCI_HOST_BRIDGE,
 184     .class_init    = pxb_host_class_init,
 185 };
 186
 187 static void pxb_cxl_realize(DeviceState *dev, Error **errp)
 188 {
 189     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 190     CXLHost *cxl = PXB_CXL_HOST(dev);
 191     CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
 192     struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
 193
 194     cxl_component_register_block_init(OBJECT(dev), cxl_cstate,
 195                                       TYPE_PXB_CXL_HOST);
 196     sysbus_init_mmio(sbd, mr);
 197 }
 198
 199 /*
 200  * Host bridge realization has no means of knowning state associated
 201  * with a particular machine. As such, it is nececssary to delay
 202  * final setup of the host bridge register space until later in the
 203  * machine bring up.
 204  */
 205 void pxb_cxl_hook_up_registers(CXLState *cxl_state, PCIBus *bus, Error **errp)
 206 {
 207     PXBDev *pxb =  PXB_CXL_DEV(pci_bridge_get_device(bus));
 208     CXLHost *cxl = pxb->cxl.cxl_host_bridge;
 209     CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
 210     struct MemoryRegion *mr = &cxl_cstate->crb.component_registers;
 211     hwaddr offset;
 212
 213     offset = memory_region_size(mr) * cxl_state->next_mr_idx;
 214     if (offset > memory_region_size(&cxl_state->host_mr)) {
 215         error_setg(errp, "Insufficient space for pxb cxl host register space");
 216         return;
 217     }
 218
 219     memory_region_add_subregion(&cxl_state->host_mr, offset, mr);
 220     cxl_state->next_mr_idx++;
 221 }
 222
 223 static void pxb_cxl_host_class_init(ObjectClass *class, void *data)
 224 {
 225     DeviceClass *dc = DEVICE_CLASS(class);
 226     PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(class);
 227
 228     hc->root_bus_path = pxb_host_root_bus_path;
 229     dc->fw_name = "cxl";
 230     dc->realize = pxb_cxl_realize;
 231     /* Reason: Internal part of the pxb/pxb-pcie device, not usable by itself */
 232     dc->user_creatable = false;
 233 }
 234
 235 /*
 236  * This is a device to handle the MMIO for a CXL host bridge. It does nothing
 237  * else.
 238  */
 239 static const TypeInfo cxl_host_info = {
 240     .name          = TYPE_PXB_CXL_HOST,
 241     .parent        = TYPE_PCI_HOST_BRIDGE,
 242     .instance_size = sizeof(CXLHost),
 243     .class_init    = pxb_cxl_host_class_init,
 244 };
 245
 246 /*
 247  * Registers the PXB bus as a child of pci host root bus.
 248  */
 249 static void pxb_register_bus(PCIDevice *dev, PCIBus *pxb_bus, Error **errp)
 250 {
 251     PCIBus *bus = pci_get_bus(dev);
 252     int pxb_bus_num = pci_bus_num(pxb_bus);
 253
 254     if (bus->parent_dev) {
 255         error_setg(errp, "PXB devices can be attached only to root bus");
 256         return;
 257     }
 258
 259     QLIST_FOREACH(bus, &bus->child, sibling) {
 260         if (pci_bus_num(bus) == pxb_bus_num) {
 261             error_setg(errp, "Bus %d is already in use", pxb_bus_num);
 262             return;
 263         }
 264     }
 265     QLIST_INSERT_HEAD(&pci_get_bus(dev)->child, pxb_bus, sibling);
 266 }
 267
 268 static int pxb_map_irq_fn(PCIDevice *pci_dev, int pin)
 269 {
 270     PCIDevice *pxb = pci_get_bus(pci_dev)->parent_dev;
 271
 272     /*
 273      * First carry out normal swizzle to handle
 274      * multple root ports on a pxb instance.
 275      */
 276     pin = pci_swizzle_map_irq_fn(pci_dev, pin);
 277
 278     /*
 279      * The bios does not index the pxb slot number when
 280      * it computes the IRQ because it resides on bus 0
 281      * and not on the current bus.
 282      * However QEMU routes the irq through bus 0 and adds
 283      * the pxb slot to the IRQ computation of the PXB
 284      * device.
 285      *
 286      * Synchronize between bios and QEMU by canceling
 287      * pxb's effect.
 288      */
 289     return pin - PCI_SLOT(pxb->devfn);
 290 }
 291
 292 static void pxb_dev_reset(DeviceState *dev)
 293 {
 294     CXLHost *cxl = PXB_CXL_DEV(dev)->cxl.cxl_host_bridge;
 295     CXLComponentState *cxl_cstate = &cxl->cxl_cstate;
 296     uint32_t *reg_state = cxl_cstate->crb.cache_mem_registers;
 297     uint32_t *write_msk = cxl_cstate->crb.cache_mem_regs_write_mask;
 298
 299     cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT);
 300     ARRAY_FIELD_DP32(reg_state, CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 8);
 301 }
 302
 303 static gint pxb_compare(gconstpointer a, gconstpointer b)
 304 {
 305     const PXBDev *pxb_a = a, *pxb_b = b;
 306
 307     return pxb_a->bus_nr < pxb_b->bus_nr ? -1 :
 308            pxb_a->bus_nr > pxb_b->bus_nr ?  1 :
 309            0;
 310 }
 311
 312 static void pxb_dev_realize_common(PCIDevice *dev, enum BusType type,
 313                                    Error **errp)
 314 {
 315     PXBDev *pxb = convert_to_pxb(dev);
 316     DeviceState *ds, *bds = NULL;
 317     PCIBus *bus;
 318     const char *dev_name = NULL;
 319     Error *local_err = NULL;
 320     MachineState *ms = MACHINE(qdev_get_machine());
 321
 322     if (ms->numa_state == NULL) {
 323         error_setg(errp, "NUMA is not supported by this machine-type");
 324         return;
 325     }
 326
 327     if (pxb->numa_node != NUMA_NODE_UNASSIGNED &&
 328         pxb->numa_node >= ms->numa_state->num_nodes) {
 329         error_setg(errp, "Illegal numa node %d", pxb->numa_node);
 330         return;
 331     }
 332
 333     if (dev->qdev.id && *dev->qdev.id) {
 334         dev_name = dev->qdev.id;
 335     }
 336
 337     ds = qdev_new(type == CXL ? TYPE_PXB_CXL_HOST : TYPE_PXB_HOST);
 338     if (type == PCIE) {
 339         bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_PCIE_BUS);
 340     } else if (type == CXL) {
 341         bus = pci_root_bus_new(ds, dev_name, NULL, NULL, 0, TYPE_PXB_CXL_BUS);
 342         bus->flags |= PCI_BUS_CXL;
 343         PXB_CXL_DEV(dev)->cxl.cxl_host_bridge = PXB_CXL_HOST(ds);
 344     } else {
 345         bus = pci_root_bus_new(ds, "pxb-internal", NULL, NULL, 0, TYPE_PXB_BUS);
 346         bds = qdev_new("pci-bridge");
 347         bds->id = g_strdup(dev_name);
 348         qdev_prop_set_uint8(bds, PCI_BRIDGE_DEV_PROP_CHASSIS_NR, pxb->bus_nr);
 349         qdev_prop_set_bit(bds, PCI_BRIDGE_DEV_PROP_SHPC, false);
 350     }
 351
 352     bus->parent_dev = dev;
 353     bus->address_space_mem = pci_get_bus(dev)->address_space_mem;
 354     bus->address_space_io = pci_get_bus(dev)->address_space_io;
 355     bus->map_irq = pxb_map_irq_fn;
 356
 357     PCI_HOST_BRIDGE(ds)->bus = bus;
 358     PCI_HOST_BRIDGE(ds)->bypass_iommu = pxb->bypass_iommu;
 359
 360     pxb_register_bus(dev, bus, &local_err);
 361     if (local_err) {
 362         error_propagate(errp, local_err);
 363         goto err_register_bus;
 364     }
 365
 366     sysbus_realize_and_unref(SYS_BUS_DEVICE(ds), &error_fatal);
 367     if (bds) {
 368         qdev_realize_and_unref(bds, &bus->qbus, &error_fatal);
 369     }
 370
 371     pci_word_test_and_set_mask(dev->config + PCI_STATUS,
 372                                PCI_STATUS_66MHZ | PCI_STATUS_FAST_BACK);
 373     pci_config_set_class(dev->config, PCI_CLASS_BRIDGE_HOST);
 374
 375     pxb_dev_list = g_list_insert_sorted(pxb_dev_list, pxb, pxb_compare);
 376     return;
 377
 378 err_register_bus:
 379     object_unref(OBJECT(bds));
 380     object_unparent(OBJECT(bus));
 381     object_unref(OBJECT(ds));
 382 }
 383
 384 static void pxb_dev_realize(PCIDevice *dev, Error **errp)
 385 {
 386     if (pci_bus_is_express(pci_get_bus(dev))) {
 387         error_setg(errp, "pxb devices cannot reside on a PCIe bus");
 388         return;
 389     }
 390
 391     pxb_dev_realize_common(dev, PCI, errp);
 392 }
 393
 394 static void pxb_dev_exitfn(PCIDevice *pci_dev)
 395 {
 396     PXBDev *pxb = convert_to_pxb(pci_dev);
 397
 398     pxb_dev_list = g_list_remove(pxb_dev_list, pxb);
 399 }
 400
 401 static Property pxb_dev_properties[] = {
 402     /* Note: 0 is not a legal PXB bus number. */
 403     DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0),
 404     DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED),
 405     DEFINE_PROP_BOOL("bypass_iommu", PXBDev, bypass_iommu, false),
 406     DEFINE_PROP_END_OF_LIST(),
 407 };
 408
 409 static void pxb_dev_class_init(ObjectClass *klass, void *data)
 410 {
 411     DeviceClass *dc = DEVICE_CLASS(klass);
 412     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 413
 414     k->realize = pxb_dev_realize;
 415     k->exit = pxb_dev_exitfn;
 416     k->vendor_id = PCI_VENDOR_ID_REDHAT;
 417     k->device_id = PCI_DEVICE_ID_REDHAT_PXB;
 418     k->class_id = PCI_CLASS_BRIDGE_HOST;
 419
 420     dc->desc = "PCI Expander Bridge";
 421     device_class_set_props(dc, pxb_dev_properties);
 422     dc->hotpluggable = false;
 423     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 424 }
 425
 426 static const TypeInfo pxb_dev_info = {
 427     .name          = TYPE_PXB_DEVICE,
 428     .parent        = TYPE_PCI_DEVICE,
 429     .instance_size = sizeof(PXBDev),
 430     .class_init    = pxb_dev_class_init,
 431     .interfaces = (InterfaceInfo[]) {
 432         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 433         { },
 434     },
 435 };
 436
 437 static void pxb_pcie_dev_realize(PCIDevice *dev, Error **errp)
 438 {
 439     if (!pci_bus_is_express(pci_get_bus(dev))) {
 440         error_setg(errp, "pxb-pcie devices cannot reside on a PCI bus");
 441         return;
 442     }
 443
 444     pxb_dev_realize_common(dev, PCIE, errp);
 445 }
 446
 447 static void pxb_pcie_dev_class_init(ObjectClass *klass, void *data)
 448 {
 449     DeviceClass *dc = DEVICE_CLASS(klass);
 450     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 451
 452     k->realize = pxb_pcie_dev_realize;
 453     k->exit = pxb_dev_exitfn;
 454     k->vendor_id = PCI_VENDOR_ID_REDHAT;
 455     k->device_id = PCI_DEVICE_ID_REDHAT_PXB_PCIE;
 456     k->class_id = PCI_CLASS_BRIDGE_HOST;
 457
 458     dc->desc = "PCI Express Expander Bridge";
 459     device_class_set_props(dc, pxb_dev_properties);
 460     dc->hotpluggable = false;
 461     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 462 }
 463
 464 static const TypeInfo pxb_pcie_dev_info = {
 465     .name          = TYPE_PXB_PCIE_DEVICE,
 466     .parent        = TYPE_PCI_DEVICE,
 467     .instance_size = sizeof(PXBDev),
 468     .class_init    = pxb_pcie_dev_class_init,
 469     .interfaces = (InterfaceInfo[]) {
 470         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 471         { },
 472     },
 473 };
 474
 475 static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp)
 476 {
 477     /* A CXL PXB's parent bus is still PCIe */
 478     if (!pci_bus_is_express(pci_get_bus(dev))) {
 479         error_setg(errp, "pxb-cxl devices cannot reside on a PCI bus");
 480         return;
 481     }
 482
 483     pxb_dev_realize_common(dev, CXL, errp);
 484     pxb_dev_reset(DEVICE(dev));
 485 }
 486
 487 static void pxb_cxl_dev_class_init(ObjectClass *klass, void *data)
 488 {
 489     DeviceClass *dc   = DEVICE_CLASS(klass);
 490     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 491
 492     k->realize             = pxb_cxl_dev_realize;
 493     k->exit                = pxb_dev_exitfn;
 494     /*
 495      * XXX: These types of bridges don't actually show up in the hierarchy so
 496      * vendor, device, class, etc. ids are intentionally left out.
 497      */
 498
 499     dc->desc = "CXL Host Bridge";
 500     device_class_set_props(dc, pxb_dev_properties);
 501     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
 502
 503     /* Host bridges aren't hotpluggable. FIXME: spec reference */
 504     dc->hotpluggable = false;
 505     dc->reset = pxb_dev_reset;
 506 }
 507
 508 static const TypeInfo pxb_cxl_dev_info = {
 509     .name          = TYPE_PXB_CXL_DEVICE,
 510     .parent        = TYPE_PCI_DEVICE,
 511     .instance_size = sizeof(PXBDev),
 512     .class_init    = pxb_cxl_dev_class_init,
 513     .interfaces =
 514         (InterfaceInfo[]){
 515             { INTERFACE_CONVENTIONAL_PCI_DEVICE },
 516             {},
 517         },
 518 };
 519
 520 static void pxb_register_types(void)
 521 {
 522     type_register_static(&pxb_bus_info);
 523     type_register_static(&pxb_pcie_bus_info);
 524     type_register_static(&pxb_cxl_bus_info);
 525     type_register_static(&pxb_host_info);
 526     type_register_static(&cxl_host_info);
 527     type_register_static(&pxb_dev_info);
 528     type_register_static(&pxb_pcie_dev_info);
 529     type_register_static(&pxb_cxl_dev_info);
 530 }
 531
 532 type_init(pxb_register_types)