2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "sysemu/sysemu.h"
23 #include "sysemu/numa.h"
24 #include "sysemu/cpus.h"
26 #include "target/ppc/cpu.h"
28 #include "hw/ppc/fdt.h"
29 #include "hw/ppc/ppc.h"
30 #include "hw/ppc/pnv.h"
31 #include "hw/ppc/pnv_core.h"
32 #include "hw/loader.h"
33 #include "exec/address-spaces.h"
34 #include "qemu/cutils.h"
35 #include "qapi/visitor.h"
36 #include "monitor/monitor.h"
37 #include "hw/intc/intc.h"
38 #include "hw/ipmi/ipmi.h"
40 #include "hw/ppc/xics.h"
41 #include "hw/ppc/pnv_xscom.h"
43 #include "hw/isa/isa.h"
44 #include "hw/char/serial.h"
45 #include "hw/timer/mc146818rtc.h"
49 #define FDT_MAX_SIZE 0x00100000
51 #define FW_FILE_NAME "skiboot.lid"
52 #define FW_LOAD_ADDR 0x0
53 #define FW_MAX_SIZE 0x00400000
55 #define KERNEL_LOAD_ADDR 0x20000000
56 #define INITRD_LOAD_ADDR 0x40000000
59 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
60 * 4 * 4 sockets * 12 cores * 8 threads = 1536
66 * Memory nodes are created by hostboot, one for each range of memory
67 * that has a different "affinity". In practice, it means one range
70 static void powernv_populate_memory_node(void *fdt
, int chip_id
, hwaddr start
,
74 uint64_t mem_reg_property
[2];
77 mem_reg_property
[0] = cpu_to_be64(start
);
78 mem_reg_property
[1] = cpu_to_be64(size
);
80 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
81 off
= fdt_add_subnode(fdt
, 0, mem_name
);
84 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
85 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
86 sizeof(mem_reg_property
))));
87 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
90 static int get_cpus_node(void *fdt
)
92 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
94 if (cpus_offset
< 0) {
95 cpus_offset
= fdt_add_subnode(fdt
, fdt_path_offset(fdt
, "/"),
98 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
99 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
107 * The PowerNV cores (and threads) need to use real HW ids and not an
108 * incremental index like it has been done on other platforms. This HW
109 * id is stored in the CPU PIR, it is used to create cpu nodes in the
110 * device tree, used in XSCOM to address cores and in interrupt
113 static void powernv_create_core_node(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
115 CPUState
*cs
= CPU(DEVICE(pc
->threads
));
116 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
117 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
118 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
119 CPUPPCState
*env
= &cpu
->env
;
120 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
121 uint32_t servers_prop
[smt_threads
];
123 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
124 0xffffffff, 0xffffffff};
125 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
126 uint32_t cpufreq
= 1000000000;
127 uint32_t page_sizes_prop
[64];
128 size_t page_sizes_prop_size
;
129 const uint8_t pa_features
[] = { 24, 0,
130 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
131 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
132 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
133 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
136 int cpus_offset
= get_cpus_node(fdt
);
138 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
139 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
143 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
145 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
146 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
147 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
149 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
150 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
151 env
->dcache_line_size
)));
152 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
153 env
->dcache_line_size
)));
154 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
155 env
->icache_line_size
)));
156 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
157 env
->icache_line_size
)));
159 if (pcc
->l1_dcache_size
) {
160 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
161 pcc
->l1_dcache_size
)));
163 warn_report("Unknown L1 dcache size for cpu");
165 if (pcc
->l1_icache_size
) {
166 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
167 pcc
->l1_icache_size
)));
169 warn_report("Unknown L1 icache size for cpu");
172 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
173 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
174 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size", env
->slb_nr
)));
175 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
176 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
178 if (env
->spr_cb
[SPR_PURR
].oea_read
) {
179 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
182 if (env
->mmu_model
& POWERPC_MMU_1TSEG
) {
183 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
184 segs
, sizeof(segs
))));
187 /* Advertise VMX/VSX (vector extensions) if available
188 * 0 / no property == no vector extensions
189 * 1 == VMX / Altivec available
190 * 2 == VSX available */
191 if (env
->insns_flags
& PPC_ALTIVEC
) {
192 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
194 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
197 /* Advertise DFP (Decimal Floating Point) if available
198 * 0 / no property == no DFP
199 * 1 == DFP available */
200 if (env
->insns_flags2
& PPC2_DFP
) {
201 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
204 page_sizes_prop_size
= ppc_create_page_sizes_prop(env
, page_sizes_prop
,
205 sizeof(page_sizes_prop
));
206 if (page_sizes_prop_size
) {
207 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
208 page_sizes_prop
, page_sizes_prop_size
)));
211 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
212 pa_features
, sizeof(pa_features
))));
214 /* Build interrupt servers properties */
215 for (i
= 0; i
< smt_threads
; i
++) {
216 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
218 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
219 servers_prop
, sizeof(servers_prop
))));
222 static void powernv_populate_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
225 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
227 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
228 uint32_t irange
[2], i
, rsize
;
232 irange
[0] = cpu_to_be32(pir
);
233 irange
[1] = cpu_to_be32(nr_threads
);
235 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
236 reg
= g_malloc(rsize
);
237 for (i
= 0; i
< nr_threads
; i
++) {
238 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
239 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
242 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
243 offset
= fdt_add_subnode(fdt
, 0, name
);
247 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
248 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
249 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
250 "PowerPC-External-Interrupt-Presentation")));
251 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
252 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
253 irange
, sizeof(irange
))));
254 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
255 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
259 static int pnv_chip_lpc_offset(PnvChip
*chip
, void *fdt
)
264 name
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
265 (uint64_t) PNV_XSCOM_BASE(chip
), PNV_XSCOM_LPC_BASE
);
266 offset
= fdt_path_offset(fdt
, name
);
271 static void powernv_populate_chip(PnvChip
*chip
, void *fdt
)
273 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
274 char *typename
= pnv_core_typename(pcc
->cpu_model
);
275 size_t typesize
= object_type_get_instance_size(typename
);
278 pnv_xscom_populate(chip
, fdt
, 0);
280 /* The default LPC bus of a multichip system is on chip 0. It's
281 * recognized by the firmware (skiboot) using a "primary"
284 if (chip
->chip_id
== 0x0) {
285 int lpc_offset
= pnv_chip_lpc_offset(chip
, fdt
);
287 _FDT((fdt_setprop(fdt
, lpc_offset
, "primary", NULL
, 0)));
290 for (i
= 0; i
< chip
->nr_cores
; i
++) {
291 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
293 powernv_create_core_node(chip
, pnv_core
, fdt
);
295 /* Interrupt Control Presenters (ICP). One per core. */
296 powernv_populate_icp(chip
, fdt
, pnv_core
->pir
,
297 CPU_CORE(pnv_core
)->nr_threads
);
300 if (chip
->ram_size
) {
301 powernv_populate_memory_node(fdt
, chip
->chip_id
, chip
->ram_start
,
307 static void powernv_populate_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
309 uint32_t io_base
= d
->ioport_id
;
310 uint32_t io_regs
[] = {
312 cpu_to_be32(io_base
),
318 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
319 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
323 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
324 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
327 static void powernv_populate_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
329 const char compatible
[] = "ns16550\0pnpPNP,501";
330 uint32_t io_base
= d
->ioport_id
;
331 uint32_t io_regs
[] = {
333 cpu_to_be32(io_base
),
339 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
340 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
344 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
345 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
346 sizeof(compatible
))));
348 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
349 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
350 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", d
->isairq
[0])));
351 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
352 fdt_get_phandle(fdt
, lpc_off
))));
354 /* This is needed by Linux */
355 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
358 static void powernv_populate_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
360 const char compatible
[] = "bt\0ipmi-bt";
362 uint32_t io_regs
[] = {
364 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
371 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
372 io_regs
[1] = cpu_to_be32(io_base
);
374 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
376 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
377 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
381 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
382 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
383 sizeof(compatible
))));
385 /* Mark it as reserved to avoid Linux trying to claim it */
386 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
387 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
388 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
389 fdt_get_phandle(fdt
, lpc_off
))));
392 typedef struct ForeachPopulateArgs
{
395 } ForeachPopulateArgs
;
397 static int powernv_populate_isa_device(DeviceState
*dev
, void *opaque
)
399 ForeachPopulateArgs
*args
= opaque
;
400 ISADevice
*d
= ISA_DEVICE(dev
);
402 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
403 powernv_populate_rtc(d
, args
->fdt
, args
->offset
);
404 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
405 powernv_populate_serial(d
, args
->fdt
, args
->offset
);
406 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
407 powernv_populate_ipmi_bt(d
, args
->fdt
, args
->offset
);
409 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
416 static void powernv_populate_isa(ISABus
*bus
, void *fdt
, int lpc_offset
)
418 ForeachPopulateArgs args
= {
420 .offset
= lpc_offset
,
423 /* ISA devices are not necessarily parented to the ISA bus so we
424 * can not use object_child_foreach() */
425 qbus_walk_children(BUS(bus
), powernv_populate_isa_device
,
426 NULL
, NULL
, NULL
, &args
);
429 static void *powernv_create_fdt(MachineState
*machine
)
431 const char plat_compat
[] = "qemu,powernv\0ibm,powernv";
432 PnvMachineState
*pnv
= POWERNV_MACHINE(machine
);
439 fdt
= g_malloc0(FDT_MAX_SIZE
);
440 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
443 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
444 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
445 _FDT((fdt_setprop_string(fdt
, 0, "model",
446 "IBM PowerNV (emulated by qemu)")));
447 _FDT((fdt_setprop(fdt
, 0, "compatible", plat_compat
,
448 sizeof(plat_compat
))));
450 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
451 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
453 _FDT((fdt_property_string(fdt
, "system-id", buf
)));
457 off
= fdt_add_subnode(fdt
, 0, "chosen");
458 if (machine
->kernel_cmdline
) {
459 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
460 machine
->kernel_cmdline
)));
463 if (pnv
->initrd_size
) {
464 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
465 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
467 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
468 &start_prop
, sizeof(start_prop
))));
469 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
470 &end_prop
, sizeof(end_prop
))));
473 /* Populate device tree for each chip */
474 for (i
= 0; i
< pnv
->num_chips
; i
++) {
475 powernv_populate_chip(pnv
->chips
[i
], fdt
);
478 /* Populate ISA devices on chip 0 */
479 lpc_offset
= pnv_chip_lpc_offset(pnv
->chips
[0], fdt
);
480 powernv_populate_isa(pnv
->isa_bus
, fdt
, lpc_offset
);
483 pnv_bmc_populate_sensors(pnv
->bmc
, fdt
);
489 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
491 PnvMachineState
*pnv
= POWERNV_MACHINE(qdev_get_machine());
494 pnv_bmc_powerdown(pnv
->bmc
);
498 static void ppc_powernv_reset(void)
500 MachineState
*machine
= MACHINE(qdev_get_machine());
501 PnvMachineState
*pnv
= POWERNV_MACHINE(machine
);
505 qemu_devices_reset();
507 /* OpenPOWER systems have a BMC, which can be defined on the
510 * -device ipmi-bmc-sim,id=bmc0
512 * This is the internal simulator but it could also be an external
515 obj
= object_resolve_path_type("", "ipmi-bmc-sim", NULL
);
517 pnv
->bmc
= IPMI_BMC(obj
);
520 fdt
= powernv_create_fdt(machine
);
522 /* Pack resulting tree */
523 _FDT((fdt_pack(fdt
)));
525 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
528 static ISABus
*pnv_isa_create(PnvChip
*chip
)
530 PnvLpcController
*lpc
= &chip
->lpc
;
533 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
535 /* let isa_bus_new() create its own bridge on SysBus otherwise
536 * devices speficied on the command line won't find the bus and
537 * will fail to create.
539 isa_bus
= isa_bus_new(NULL
, &lpc
->isa_mem
, &lpc
->isa_io
,
542 irqs
= pnv_lpc_isa_irq_create(lpc
, pcc
->chip_type
, ISA_NUM_IRQS
);
544 isa_bus_irqs(isa_bus
, irqs
);
548 static void ppc_powernv_init(MachineState
*machine
)
550 PnvMachineState
*pnv
= POWERNV_MACHINE(machine
);
558 if (machine
->ram_size
< (1 * G_BYTE
)) {
559 warn_report("skiboot may not work with < 1GB of RAM");
562 ram
= g_new(MemoryRegion
, 1);
563 memory_region_allocate_system_memory(ram
, NULL
, "ppc_powernv.ram",
565 memory_region_add_subregion(get_system_memory(), 0, ram
);
567 /* load skiboot firmware */
568 if (bios_name
== NULL
) {
569 bios_name
= FW_FILE_NAME
;
572 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
574 error_report("Could not find OPAL firmware '%s'", bios_name
);
578 fw_size
= load_image_targphys(fw_filename
, FW_LOAD_ADDR
, FW_MAX_SIZE
);
580 error_report("Could not load OPAL firmware '%s'", fw_filename
);
586 if (machine
->kernel_filename
) {
589 kernel_size
= load_image_targphys(machine
->kernel_filename
,
590 KERNEL_LOAD_ADDR
, 0x2000000);
591 if (kernel_size
< 0) {
592 error_report("Could not load kernel '%s'",
593 machine
->kernel_filename
);
599 if (machine
->initrd_filename
) {
600 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
601 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
602 pnv
->initrd_base
, 0x10000000); /* 128MB max */
603 if (pnv
->initrd_size
< 0) {
604 error_report("Could not load initial ram disk '%s'",
605 machine
->initrd_filename
);
610 /* We need some cpu model to instantiate the PnvChip class */
611 if (machine
->cpu_model
== NULL
) {
612 machine
->cpu_model
= "POWER8";
615 /* Create the processor chips */
616 chip_typename
= g_strdup_printf(TYPE_PNV_CHIP
"-%s", machine
->cpu_model
);
617 if (!object_class_by_name(chip_typename
)) {
618 error_report("invalid CPU model '%s' for %s machine",
619 machine
->cpu_model
, MACHINE_GET_CLASS(machine
)->name
);
623 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
624 for (i
= 0; i
< pnv
->num_chips
; i
++) {
626 Object
*chip
= object_new(chip_typename
);
628 pnv
->chips
[i
] = PNV_CHIP(chip
);
630 /* TODO: put all the memory in one node on chip 0 until we find a
631 * way to specify different ranges for each chip
634 object_property_set_int(chip
, machine
->ram_size
, "ram-size",
638 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", PNV_CHIP_HWID(i
));
639 object_property_add_child(OBJECT(pnv
), chip_name
, chip
, &error_fatal
);
640 object_property_set_int(chip
, PNV_CHIP_HWID(i
), "chip-id",
642 object_property_set_int(chip
, smp_cores
, "nr-cores", &error_fatal
);
643 object_property_set_bool(chip
, true, "realized", &error_fatal
);
645 g_free(chip_typename
);
647 /* Instantiate ISA bus on chip 0 */
648 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0]);
650 /* Create serial port */
651 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_SERIAL_PORTS
);
653 /* Create an RTC ISA device too */
654 rtc_init(pnv
->isa_bus
, 2000, NULL
);
656 /* OpenPOWER systems use a IPMI SEL Event message to notify the
657 * host to powerdown */
658 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
659 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
663 * 0:21 Reserved - Read as zeros
668 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
670 return (chip
->chip_id
<< 7) | (core_id
<< 3);
674 * 0:48 Reserved - Read as zeroes
677 * 56 Reserved - Read as zero
681 * We only care about the lower bits. uint32_t is fine for the moment.
683 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
685 return (chip
->chip_id
<< 8) | (core_id
<< 2);
688 /* Allowed core identifiers on a POWER8 Processor Chip :
697 * <EX7,8 reserved> <reserved>
706 #define POWER8E_CORE_MASK (0x7070ull)
707 #define POWER8_CORE_MASK (0x7e7eull)
710 * POWER9 has 24 cores, ids starting at 0x20
712 #define POWER9_CORE_MASK (0xffffff00000000ull)
714 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
716 DeviceClass
*dc
= DEVICE_CLASS(klass
);
717 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
719 k
->cpu_model
= "POWER8E";
720 k
->chip_type
= PNV_CHIP_POWER8E
;
721 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
722 k
->cores_mask
= POWER8E_CORE_MASK
;
723 k
->core_pir
= pnv_chip_core_pir_p8
;
724 k
->xscom_base
= 0x003fc0000000000ull
;
725 k
->xscom_core_base
= 0x10000000ull
;
726 dc
->desc
= "PowerNV Chip POWER8E";
729 static const TypeInfo pnv_chip_power8e_info
= {
730 .name
= TYPE_PNV_CHIP_POWER8E
,
731 .parent
= TYPE_PNV_CHIP
,
732 .instance_size
= sizeof(PnvChip
),
733 .class_init
= pnv_chip_power8e_class_init
,
736 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
738 DeviceClass
*dc
= DEVICE_CLASS(klass
);
739 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
741 k
->cpu_model
= "POWER8";
742 k
->chip_type
= PNV_CHIP_POWER8
;
743 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
744 k
->cores_mask
= POWER8_CORE_MASK
;
745 k
->core_pir
= pnv_chip_core_pir_p8
;
746 k
->xscom_base
= 0x003fc0000000000ull
;
747 k
->xscom_core_base
= 0x10000000ull
;
748 dc
->desc
= "PowerNV Chip POWER8";
751 static const TypeInfo pnv_chip_power8_info
= {
752 .name
= TYPE_PNV_CHIP_POWER8
,
753 .parent
= TYPE_PNV_CHIP
,
754 .instance_size
= sizeof(PnvChip
),
755 .class_init
= pnv_chip_power8_class_init
,
758 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
760 DeviceClass
*dc
= DEVICE_CLASS(klass
);
761 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
763 k
->cpu_model
= "POWER8NVL";
764 k
->chip_type
= PNV_CHIP_POWER8NVL
;
765 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
766 k
->cores_mask
= POWER8_CORE_MASK
;
767 k
->core_pir
= pnv_chip_core_pir_p8
;
768 k
->xscom_base
= 0x003fc0000000000ull
;
769 k
->xscom_core_base
= 0x10000000ull
;
770 dc
->desc
= "PowerNV Chip POWER8NVL";
773 static const TypeInfo pnv_chip_power8nvl_info
= {
774 .name
= TYPE_PNV_CHIP_POWER8NVL
,
775 .parent
= TYPE_PNV_CHIP
,
776 .instance_size
= sizeof(PnvChip
),
777 .class_init
= pnv_chip_power8nvl_class_init
,
780 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
782 DeviceClass
*dc
= DEVICE_CLASS(klass
);
783 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
785 k
->cpu_model
= "POWER9";
786 k
->chip_type
= PNV_CHIP_POWER9
;
787 k
->chip_cfam_id
= 0x100d104980000000ull
; /* P9 Nimbus DD1.0 */
788 k
->cores_mask
= POWER9_CORE_MASK
;
789 k
->core_pir
= pnv_chip_core_pir_p9
;
790 k
->xscom_base
= 0x00603fc00000000ull
;
791 k
->xscom_core_base
= 0x0ull
;
792 dc
->desc
= "PowerNV Chip POWER9";
795 static const TypeInfo pnv_chip_power9_info
= {
796 .name
= TYPE_PNV_CHIP_POWER9
,
797 .parent
= TYPE_PNV_CHIP
,
798 .instance_size
= sizeof(PnvChip
),
799 .class_init
= pnv_chip_power9_class_init
,
802 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
804 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
808 * No custom mask for this chip, let's use the default one from *
811 if (!chip
->cores_mask
) {
812 chip
->cores_mask
= pcc
->cores_mask
;
815 /* filter alien core ids ! some are reserved */
816 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
817 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
821 chip
->cores_mask
&= pcc
->cores_mask
;
823 /* now that we have a sane layout, let check the number of cores */
824 cores_max
= ctpop64(chip
->cores_mask
);
825 if (chip
->nr_cores
> cores_max
) {
826 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
832 static void pnv_chip_init(Object
*obj
)
834 PnvChip
*chip
= PNV_CHIP(obj
);
835 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
837 chip
->xscom_base
= pcc
->xscom_base
;
839 object_initialize(&chip
->lpc
, sizeof(chip
->lpc
), TYPE_PNV_LPC
);
840 object_property_add_child(obj
, "lpc", OBJECT(&chip
->lpc
), NULL
);
842 object_initialize(&chip
->psi
, sizeof(chip
->psi
), TYPE_PNV_PSI
);
843 object_property_add_child(obj
, "psi", OBJECT(&chip
->psi
), NULL
);
844 object_property_add_const_link(OBJECT(&chip
->psi
), "xics",
845 OBJECT(qdev_get_machine()), &error_abort
);
847 object_initialize(&chip
->occ
, sizeof(chip
->occ
), TYPE_PNV_OCC
);
848 object_property_add_child(obj
, "occ", OBJECT(&chip
->occ
), NULL
);
849 object_property_add_const_link(OBJECT(&chip
->occ
), "psi",
850 OBJECT(&chip
->psi
), &error_abort
);
852 /* The LPC controller needs PSI to generate interrupts */
853 object_property_add_const_link(OBJECT(&chip
->lpc
), "psi",
854 OBJECT(&chip
->psi
), &error_abort
);
857 static void pnv_chip_icp_realize(PnvChip
*chip
, Error
**errp
)
859 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
860 char *typename
= pnv_core_typename(pcc
->cpu_model
);
861 size_t typesize
= object_type_get_instance_size(typename
);
864 XICSFabric
*xi
= XICS_FABRIC(qdev_get_machine());
866 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
867 memory_region_init(&chip
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
868 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip
->icp_mmio
);
871 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
873 /* Map the ICP registers for each thread */
874 for (i
= 0; i
< chip
->nr_cores
; i
++) {
875 PnvCore
*pnv_core
= PNV_CORE(chip
->cores
+ i
* typesize
);
876 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
878 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
879 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
880 PnvICPState
*icp
= PNV_ICP(xics_icp_get(xi
, pir
));
882 memory_region_add_subregion(&chip
->icp_mmio
, pir
<< 12, &icp
->mmio
);
889 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
891 PnvChip
*chip
= PNV_CHIP(dev
);
893 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
894 char *typename
= pnv_core_typename(pcc
->cpu_model
);
895 size_t typesize
= object_type_get_instance_size(typename
);
898 if (!object_class_by_name(typename
)) {
899 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
904 pnv_xscom_realize(chip
, &error
);
906 error_propagate(errp
, error
);
909 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
912 pnv_chip_core_sanitize(chip
, &error
);
914 error_propagate(errp
, error
);
918 chip
->cores
= g_malloc0(typesize
* chip
->nr_cores
);
920 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
921 && (i
< chip
->nr_cores
); core_hwid
++) {
923 void *pnv_core
= chip
->cores
+ i
* typesize
;
925 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
929 object_initialize(pnv_core
, typesize
, typename
);
930 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
931 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
),
933 object_property_set_int(OBJECT(pnv_core
), smp_threads
, "nr-threads",
935 object_property_set_int(OBJECT(pnv_core
), core_hwid
,
936 CPU_CORE_PROP_CORE_ID
, &error_fatal
);
937 object_property_set_int(OBJECT(pnv_core
),
938 pcc
->core_pir(chip
, core_hwid
),
939 "pir", &error_fatal
);
940 object_property_add_const_link(OBJECT(pnv_core
), "xics",
941 qdev_get_machine(), &error_fatal
);
942 object_property_set_bool(OBJECT(pnv_core
), true, "realized",
944 object_unref(OBJECT(pnv_core
));
946 /* Each core has an XSCOM MMIO region */
947 pnv_xscom_add_subregion(chip
,
948 PNV_XSCOM_EX_CORE_BASE(pcc
->xscom_core_base
,
950 &PNV_CORE(pnv_core
)->xscom_regs
);
955 /* Create LPC controller */
956 object_property_set_bool(OBJECT(&chip
->lpc
), true, "realized",
958 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip
->lpc
.xscom_regs
);
960 /* Interrupt Management Area. This is the memory region holding
961 * all the Interrupt Control Presenter (ICP) registers */
962 pnv_chip_icp_realize(chip
, &error
);
964 error_propagate(errp
, error
);
968 /* Processor Service Interface (PSI) Host Bridge */
969 object_property_set_int(OBJECT(&chip
->psi
), PNV_PSIHB_BASE(chip
),
970 "bar", &error_fatal
);
971 object_property_set_bool(OBJECT(&chip
->psi
), true, "realized", &error
);
973 error_propagate(errp
, error
);
976 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
, &chip
->psi
.xscom_regs
);
978 /* Create the simplified OCC model */
979 object_property_set_bool(OBJECT(&chip
->occ
), true, "realized", &error
);
981 error_propagate(errp
, error
);
984 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip
->occ
.xscom_regs
);
987 static Property pnv_chip_properties
[] = {
988 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
989 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
990 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
991 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
992 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
993 DEFINE_PROP_END_OF_LIST(),
996 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
998 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1000 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
1001 dc
->realize
= pnv_chip_realize
;
1002 dc
->props
= pnv_chip_properties
;
1003 dc
->desc
= "PowerNV Chip";
1006 static const TypeInfo pnv_chip_info
= {
1007 .name
= TYPE_PNV_CHIP
,
1008 .parent
= TYPE_SYS_BUS_DEVICE
,
1009 .class_init
= pnv_chip_class_init
,
1010 .instance_init
= pnv_chip_init
,
1011 .class_size
= sizeof(PnvChipClass
),
1015 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
1017 PnvMachineState
*pnv
= POWERNV_MACHINE(xi
);
1020 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1021 if (ics_valid_irq(&pnv
->chips
[i
]->psi
.ics
, irq
)) {
1022 return &pnv
->chips
[i
]->psi
.ics
;
1028 static void pnv_ics_resend(XICSFabric
*xi
)
1030 PnvMachineState
*pnv
= POWERNV_MACHINE(xi
);
1033 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1034 ics_resend(&pnv
->chips
[i
]->psi
.ics
);
1038 static PowerPCCPU
*ppc_get_vcpu_by_pir(int pir
)
1043 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1044 CPUPPCState
*env
= &cpu
->env
;
1046 if (env
->spr_cb
[SPR_PIR
].default_value
== pir
) {
1054 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
1056 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
1058 return cpu
? ICP(cpu
->intc
) : NULL
;
1061 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
1064 PnvMachineState
*pnv
= POWERNV_MACHINE(obj
);
1069 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
1071 icp_pic_print_info(ICP(cpu
->intc
), mon
);
1074 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1075 ics_pic_print_info(&pnv
->chips
[i
]->psi
.ics
, mon
);
1079 static void pnv_get_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1080 void *opaque
, Error
**errp
)
1082 visit_type_uint32(v
, name
, &POWERNV_MACHINE(obj
)->num_chips
, errp
);
1085 static void pnv_set_num_chips(Object
*obj
, Visitor
*v
, const char *name
,
1086 void *opaque
, Error
**errp
)
1088 PnvMachineState
*pnv
= POWERNV_MACHINE(obj
);
1090 Error
*local_err
= NULL
;
1092 visit_type_uint32(v
, name
, &num_chips
, &local_err
);
1094 error_propagate(errp
, local_err
);
1099 * TODO: should we decide on how many chips we can create based
1100 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
1102 if (!is_power_of_2(num_chips
) || num_chips
> 4) {
1103 error_setg(errp
, "invalid number of chips: '%d'", num_chips
);
1107 pnv
->num_chips
= num_chips
;
1110 static void powernv_machine_initfn(Object
*obj
)
1112 PnvMachineState
*pnv
= POWERNV_MACHINE(obj
);
1116 static void powernv_machine_class_props_init(ObjectClass
*oc
)
1118 object_class_property_add(oc
, "num-chips", "uint32",
1119 pnv_get_num_chips
, pnv_set_num_chips
,
1121 object_class_property_set_description(oc
, "num-chips",
1122 "Specifies the number of processor chips",
1126 static void powernv_machine_class_init(ObjectClass
*oc
, void *data
)
1128 MachineClass
*mc
= MACHINE_CLASS(oc
);
1129 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
1130 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
1132 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
1133 mc
->init
= ppc_powernv_init
;
1134 mc
->reset
= ppc_powernv_reset
;
1135 mc
->max_cpus
= MAX_CPUS
;
1136 mc
->block_default_type
= IF_IDE
; /* Pnv provides a AHCI device for
1138 mc
->no_parallel
= 1;
1139 mc
->default_boot_order
= NULL
;
1140 mc
->default_ram_size
= 1 * G_BYTE
;
1141 xic
->icp_get
= pnv_icp_get
;
1142 xic
->ics_get
= pnv_ics_get
;
1143 xic
->ics_resend
= pnv_ics_resend
;
1144 ispc
->print_info
= pnv_pic_print_info
;
1146 powernv_machine_class_props_init(oc
);
1149 static const TypeInfo powernv_machine_info
= {
1150 .name
= TYPE_POWERNV_MACHINE
,
1151 .parent
= TYPE_MACHINE
,
1152 .instance_size
= sizeof(PnvMachineState
),
1153 .instance_init
= powernv_machine_initfn
,
1154 .class_init
= powernv_machine_class_init
,
1155 .interfaces
= (InterfaceInfo
[]) {
1156 { TYPE_XICS_FABRIC
},
1157 { TYPE_INTERRUPT_STATS_PROVIDER
},
1162 static void powernv_machine_register_types(void)
1164 type_register_static(&powernv_machine_info
);
1165 type_register_static(&pnv_chip_info
);
1166 type_register_static(&pnv_chip_power8e_info
);
1167 type_register_static(&pnv_chip_power8_info
);
1168 type_register_static(&pnv_chip_power8nvl_info
);
1169 type_register_static(&pnv_chip_power9_info
);
1172 type_init(powernv_machine_register_types
)