2 * QEMU PowerPC PowerNV machine model
4 * Copyright (c) 2016, IBM Corporation.
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
40 #include "qapi/visitor.h"
41 #include "monitor/monitor.h"
42 #include "hw/intc/intc.h"
43 #include "hw/ipmi/ipmi.h"
44 #include "target/ppc/mmu-hash64.h"
45 #include "hw/pci/msi.h"
47 #include "hw/ppc/xics.h"
48 #include "hw/qdev-properties.h"
49 #include "hw/ppc/pnv_xscom.h"
50 #include "hw/ppc/pnv_pnor.h"
52 #include "hw/isa/isa.h"
53 #include "hw/char/serial.h"
54 #include "hw/rtc/mc146818rtc.h"
58 #define FDT_MAX_SIZE (1 * MiB)
60 #define FW_FILE_NAME "skiboot.lid"
61 #define FW_LOAD_ADDR 0x0
62 #define FW_MAX_SIZE (16 * MiB)
64 #define KERNEL_LOAD_ADDR 0x20000000
65 #define KERNEL_MAX_SIZE (128 * MiB)
66 #define INITRD_LOAD_ADDR 0x28000000
67 #define INITRD_MAX_SIZE (128 * MiB)
69 static const char *pnv_chip_core_typename(const PnvChip
*o
)
71 const char *chip_type
= object_class_get_name(object_get_class(OBJECT(o
)));
72 int len
= strlen(chip_type
) - strlen(PNV_CHIP_TYPE_SUFFIX
);
73 char *s
= g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len
, chip_type
);
74 const char *core_type
= object_class_get_name(object_class_by_name(s
));
80 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
81 * 4 * 4 sockets * 12 cores * 8 threads = 1536
87 * Memory nodes are created by hostboot, one for each range of memory
88 * that has a different "affinity". In practice, it means one range
91 static void pnv_dt_memory(void *fdt
, int chip_id
, hwaddr start
, hwaddr size
)
94 uint64_t mem_reg_property
[2];
97 mem_reg_property
[0] = cpu_to_be64(start
);
98 mem_reg_property
[1] = cpu_to_be64(size
);
100 mem_name
= g_strdup_printf("memory@%"HWADDR_PRIx
, start
);
101 off
= fdt_add_subnode(fdt
, 0, mem_name
);
104 _FDT((fdt_setprop_string(fdt
, off
, "device_type", "memory")));
105 _FDT((fdt_setprop(fdt
, off
, "reg", mem_reg_property
,
106 sizeof(mem_reg_property
))));
107 _FDT((fdt_setprop_cell(fdt
, off
, "ibm,chip-id", chip_id
)));
110 static int get_cpus_node(void *fdt
)
112 int cpus_offset
= fdt_path_offset(fdt
, "/cpus");
114 if (cpus_offset
< 0) {
115 cpus_offset
= fdt_add_subnode(fdt
, 0, "cpus");
117 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#address-cells", 0x1)));
118 _FDT((fdt_setprop_cell(fdt
, cpus_offset
, "#size-cells", 0x0)));
126 * The PowerNV cores (and threads) need to use real HW ids and not an
127 * incremental index like it has been done on other platforms. This HW
128 * id is stored in the CPU PIR, it is used to create cpu nodes in the
129 * device tree, used in XSCOM to address cores and in interrupt
132 static void pnv_dt_core(PnvChip
*chip
, PnvCore
*pc
, void *fdt
)
134 PowerPCCPU
*cpu
= pc
->threads
[0];
135 CPUState
*cs
= CPU(cpu
);
136 DeviceClass
*dc
= DEVICE_GET_CLASS(cs
);
137 int smt_threads
= CPU_CORE(pc
)->nr_threads
;
138 CPUPPCState
*env
= &cpu
->env
;
139 PowerPCCPUClass
*pcc
= POWERPC_CPU_GET_CLASS(cs
);
140 uint32_t servers_prop
[smt_threads
];
142 uint32_t segs
[] = {cpu_to_be32(28), cpu_to_be32(40),
143 0xffffffff, 0xffffffff};
144 uint32_t tbfreq
= PNV_TIMEBASE_FREQ
;
145 uint32_t cpufreq
= 1000000000;
146 uint32_t page_sizes_prop
[64];
147 size_t page_sizes_prop_size
;
148 const uint8_t pa_features
[] = { 24, 0,
149 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
150 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
151 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
152 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
155 int cpus_offset
= get_cpus_node(fdt
);
157 nodename
= g_strdup_printf("%s@%x", dc
->fw_name
, pc
->pir
);
158 offset
= fdt_add_subnode(fdt
, cpus_offset
, nodename
);
162 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,chip-id", chip
->chip_id
)));
164 _FDT((fdt_setprop_cell(fdt
, offset
, "reg", pc
->pir
)));
165 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,pir", pc
->pir
)));
166 _FDT((fdt_setprop_string(fdt
, offset
, "device_type", "cpu")));
168 _FDT((fdt_setprop_cell(fdt
, offset
, "cpu-version", env
->spr
[SPR_PVR
])));
169 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-block-size",
170 env
->dcache_line_size
)));
171 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-line-size",
172 env
->dcache_line_size
)));
173 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-block-size",
174 env
->icache_line_size
)));
175 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-line-size",
176 env
->icache_line_size
)));
178 if (pcc
->l1_dcache_size
) {
179 _FDT((fdt_setprop_cell(fdt
, offset
, "d-cache-size",
180 pcc
->l1_dcache_size
)));
182 warn_report("Unknown L1 dcache size for cpu");
184 if (pcc
->l1_icache_size
) {
185 _FDT((fdt_setprop_cell(fdt
, offset
, "i-cache-size",
186 pcc
->l1_icache_size
)));
188 warn_report("Unknown L1 icache size for cpu");
191 _FDT((fdt_setprop_cell(fdt
, offset
, "timebase-frequency", tbfreq
)));
192 _FDT((fdt_setprop_cell(fdt
, offset
, "clock-frequency", cpufreq
)));
193 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,slb-size",
194 cpu
->hash64_opts
->slb_size
)));
195 _FDT((fdt_setprop_string(fdt
, offset
, "status", "okay")));
196 _FDT((fdt_setprop(fdt
, offset
, "64-bit", NULL
, 0)));
198 if (ppc_has_spr(cpu
, SPR_PURR
)) {
199 _FDT((fdt_setprop(fdt
, offset
, "ibm,purr", NULL
, 0)));
202 if (ppc_hash64_has(cpu
, PPC_HASH64_1TSEG
)) {
203 _FDT((fdt_setprop(fdt
, offset
, "ibm,processor-segment-sizes",
204 segs
, sizeof(segs
))));
208 * Advertise VMX/VSX (vector extensions) if available
209 * 0 / no property == no vector extensions
210 * 1 == VMX / Altivec available
213 if (env
->insns_flags
& PPC_ALTIVEC
) {
214 uint32_t vmx
= (env
->insns_flags2
& PPC2_VSX
) ? 2 : 1;
216 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,vmx", vmx
)));
220 * Advertise DFP (Decimal Floating Point) if available
221 * 0 / no property == no DFP
224 if (env
->insns_flags2
& PPC2_DFP
) {
225 _FDT((fdt_setprop_cell(fdt
, offset
, "ibm,dfp", 1)));
228 page_sizes_prop_size
= ppc_create_page_sizes_prop(cpu
, page_sizes_prop
,
229 sizeof(page_sizes_prop
));
230 if (page_sizes_prop_size
) {
231 _FDT((fdt_setprop(fdt
, offset
, "ibm,segment-page-sizes",
232 page_sizes_prop
, page_sizes_prop_size
)));
235 _FDT((fdt_setprop(fdt
, offset
, "ibm,pa-features",
236 pa_features
, sizeof(pa_features
))));
238 /* Build interrupt servers properties */
239 for (i
= 0; i
< smt_threads
; i
++) {
240 servers_prop
[i
] = cpu_to_be32(pc
->pir
+ i
);
242 _FDT((fdt_setprop(fdt
, offset
, "ibm,ppc-interrupt-server#s",
243 servers_prop
, sizeof(servers_prop
))));
246 static void pnv_dt_icp(PnvChip
*chip
, void *fdt
, uint32_t pir
,
249 uint64_t addr
= PNV_ICP_BASE(chip
) | (pir
<< 12);
251 const char compat
[] = "IBM,power8-icp\0IBM,ppc-xicp";
252 uint32_t irange
[2], i
, rsize
;
256 irange
[0] = cpu_to_be32(pir
);
257 irange
[1] = cpu_to_be32(nr_threads
);
259 rsize
= sizeof(uint64_t) * 2 * nr_threads
;
260 reg
= g_malloc(rsize
);
261 for (i
= 0; i
< nr_threads
; i
++) {
262 reg
[i
* 2] = cpu_to_be64(addr
| ((pir
+ i
) * 0x1000));
263 reg
[i
* 2 + 1] = cpu_to_be64(0x1000);
266 name
= g_strdup_printf("interrupt-controller@%"PRIX64
, addr
);
267 offset
= fdt_add_subnode(fdt
, 0, name
);
271 _FDT((fdt_setprop(fdt
, offset
, "compatible", compat
, sizeof(compat
))));
272 _FDT((fdt_setprop(fdt
, offset
, "reg", reg
, rsize
)));
273 _FDT((fdt_setprop_string(fdt
, offset
, "device_type",
274 "PowerPC-External-Interrupt-Presentation")));
275 _FDT((fdt_setprop(fdt
, offset
, "interrupt-controller", NULL
, 0)));
276 _FDT((fdt_setprop(fdt
, offset
, "ibm,interrupt-server-ranges",
277 irange
, sizeof(irange
))));
278 _FDT((fdt_setprop_cell(fdt
, offset
, "#interrupt-cells", 1)));
279 _FDT((fdt_setprop_cell(fdt
, offset
, "#address-cells", 0)));
283 static void pnv_chip_power8_dt_populate(PnvChip
*chip
, void *fdt
)
285 static const char compat
[] = "ibm,power8-xscom\0ibm,xscom";
288 pnv_dt_xscom(chip
, fdt
, 0,
289 cpu_to_be64(PNV_XSCOM_BASE(chip
)),
290 cpu_to_be64(PNV_XSCOM_SIZE
),
291 compat
, sizeof(compat
));
293 for (i
= 0; i
< chip
->nr_cores
; i
++) {
294 PnvCore
*pnv_core
= chip
->cores
[i
];
296 pnv_dt_core(chip
, pnv_core
, fdt
);
298 /* Interrupt Control Presenters (ICP). One per core. */
299 pnv_dt_icp(chip
, fdt
, pnv_core
->pir
, CPU_CORE(pnv_core
)->nr_threads
);
302 if (chip
->ram_size
) {
303 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
307 static void pnv_chip_power9_dt_populate(PnvChip
*chip
, void *fdt
)
309 static const char compat
[] = "ibm,power9-xscom\0ibm,xscom";
312 pnv_dt_xscom(chip
, fdt
, 0,
313 cpu_to_be64(PNV9_XSCOM_BASE(chip
)),
314 cpu_to_be64(PNV9_XSCOM_SIZE
),
315 compat
, sizeof(compat
));
317 for (i
= 0; i
< chip
->nr_cores
; i
++) {
318 PnvCore
*pnv_core
= chip
->cores
[i
];
320 pnv_dt_core(chip
, pnv_core
, fdt
);
323 if (chip
->ram_size
) {
324 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
327 pnv_dt_lpc(chip
, fdt
, 0, PNV9_LPCM_BASE(chip
), PNV9_LPCM_SIZE
);
330 static void pnv_chip_power10_dt_populate(PnvChip
*chip
, void *fdt
)
332 static const char compat
[] = "ibm,power10-xscom\0ibm,xscom";
335 pnv_dt_xscom(chip
, fdt
, 0,
336 cpu_to_be64(PNV10_XSCOM_BASE(chip
)),
337 cpu_to_be64(PNV10_XSCOM_SIZE
),
338 compat
, sizeof(compat
));
340 for (i
= 0; i
< chip
->nr_cores
; i
++) {
341 PnvCore
*pnv_core
= chip
->cores
[i
];
343 pnv_dt_core(chip
, pnv_core
, fdt
);
346 if (chip
->ram_size
) {
347 pnv_dt_memory(fdt
, chip
->chip_id
, chip
->ram_start
, chip
->ram_size
);
350 pnv_dt_lpc(chip
, fdt
, 0, PNV10_LPCM_BASE(chip
), PNV10_LPCM_SIZE
);
353 static void pnv_dt_rtc(ISADevice
*d
, void *fdt
, int lpc_off
)
355 uint32_t io_base
= d
->ioport_id
;
356 uint32_t io_regs
[] = {
358 cpu_to_be32(io_base
),
364 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
365 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
369 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
370 _FDT((fdt_setprop_string(fdt
, node
, "compatible", "pnpPNP,b00")));
373 static void pnv_dt_serial(ISADevice
*d
, void *fdt
, int lpc_off
)
375 const char compatible
[] = "ns16550\0pnpPNP,501";
376 uint32_t io_base
= d
->ioport_id
;
377 uint32_t io_regs
[] = {
379 cpu_to_be32(io_base
),
386 irq
= object_property_get_uint(OBJECT(d
), "irq", &error_fatal
);
388 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
389 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
393 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
394 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
395 sizeof(compatible
))));
397 _FDT((fdt_setprop_cell(fdt
, node
, "clock-frequency", 1843200)));
398 _FDT((fdt_setprop_cell(fdt
, node
, "current-speed", 115200)));
399 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
400 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
401 fdt_get_phandle(fdt
, lpc_off
))));
403 /* This is needed by Linux */
404 _FDT((fdt_setprop_string(fdt
, node
, "device_type", "serial")));
407 static void pnv_dt_ipmi_bt(ISADevice
*d
, void *fdt
, int lpc_off
)
409 const char compatible
[] = "bt\0ipmi-bt";
411 uint32_t io_regs
[] = {
413 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
420 io_base
= object_property_get_int(OBJECT(d
), "ioport", &error_fatal
);
421 io_regs
[1] = cpu_to_be32(io_base
);
423 irq
= object_property_get_int(OBJECT(d
), "irq", &error_fatal
);
425 name
= g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d
)), io_base
);
426 node
= fdt_add_subnode(fdt
, lpc_off
, name
);
430 _FDT((fdt_setprop(fdt
, node
, "reg", io_regs
, sizeof(io_regs
))));
431 _FDT((fdt_setprop(fdt
, node
, "compatible", compatible
,
432 sizeof(compatible
))));
434 /* Mark it as reserved to avoid Linux trying to claim it */
435 _FDT((fdt_setprop_string(fdt
, node
, "status", "reserved")));
436 _FDT((fdt_setprop_cell(fdt
, node
, "interrupts", irq
)));
437 _FDT((fdt_setprop_cell(fdt
, node
, "interrupt-parent",
438 fdt_get_phandle(fdt
, lpc_off
))));
441 typedef struct ForeachPopulateArgs
{
444 } ForeachPopulateArgs
;
446 static int pnv_dt_isa_device(DeviceState
*dev
, void *opaque
)
448 ForeachPopulateArgs
*args
= opaque
;
449 ISADevice
*d
= ISA_DEVICE(dev
);
451 if (object_dynamic_cast(OBJECT(dev
), TYPE_MC146818_RTC
)) {
452 pnv_dt_rtc(d
, args
->fdt
, args
->offset
);
453 } else if (object_dynamic_cast(OBJECT(dev
), TYPE_ISA_SERIAL
)) {
454 pnv_dt_serial(d
, args
->fdt
, args
->offset
);
455 } else if (object_dynamic_cast(OBJECT(dev
), "isa-ipmi-bt")) {
456 pnv_dt_ipmi_bt(d
, args
->fdt
, args
->offset
);
458 error_report("unknown isa device %s@i%x", qdev_fw_name(dev
),
466 * The default LPC bus of a multichip system is on chip 0. It's
467 * recognized by the firmware (skiboot) using a "primary" property.
469 static void pnv_dt_isa(PnvMachineState
*pnv
, void *fdt
)
471 int isa_offset
= fdt_path_offset(fdt
, pnv
->chips
[0]->dt_isa_nodename
);
472 ForeachPopulateArgs args
= {
474 .offset
= isa_offset
,
478 _FDT((fdt_setprop(fdt
, isa_offset
, "primary", NULL
, 0)));
480 phandle
= qemu_fdt_alloc_phandle(fdt
);
482 _FDT((fdt_setprop_cell(fdt
, isa_offset
, "phandle", phandle
)));
485 * ISA devices are not necessarily parented to the ISA bus so we
486 * can not use object_child_foreach()
488 qbus_walk_children(BUS(pnv
->isa_bus
), pnv_dt_isa_device
, NULL
, NULL
, NULL
,
492 static void pnv_dt_power_mgt(PnvMachineState
*pnv
, void *fdt
)
496 off
= fdt_add_subnode(fdt
, 0, "ibm,opal");
497 off
= fdt_add_subnode(fdt
, off
, "power-mgt");
499 _FDT(fdt_setprop_cell(fdt
, off
, "ibm,enabled-stop-levels", 0xc0000000));
502 static void *pnv_dt_create(MachineState
*machine
)
504 PnvMachineClass
*pmc
= PNV_MACHINE_GET_CLASS(machine
);
505 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
511 fdt
= g_malloc0(FDT_MAX_SIZE
);
512 _FDT((fdt_create_empty_tree(fdt
, FDT_MAX_SIZE
)));
515 _FDT((fdt_add_subnode(fdt
, 0, "qemu")));
518 _FDT((fdt_setprop_cell(fdt
, 0, "#address-cells", 0x2)));
519 _FDT((fdt_setprop_cell(fdt
, 0, "#size-cells", 0x2)));
520 _FDT((fdt_setprop_string(fdt
, 0, "model",
521 "IBM PowerNV (emulated by qemu)")));
522 _FDT((fdt_setprop(fdt
, 0, "compatible", pmc
->compat
, pmc
->compat_size
)));
524 buf
= qemu_uuid_unparse_strdup(&qemu_uuid
);
525 _FDT((fdt_setprop_string(fdt
, 0, "vm,uuid", buf
)));
527 _FDT((fdt_setprop_string(fdt
, 0, "system-id", buf
)));
531 off
= fdt_add_subnode(fdt
, 0, "chosen");
532 if (machine
->kernel_cmdline
) {
533 _FDT((fdt_setprop_string(fdt
, off
, "bootargs",
534 machine
->kernel_cmdline
)));
537 if (pnv
->initrd_size
) {
538 uint32_t start_prop
= cpu_to_be32(pnv
->initrd_base
);
539 uint32_t end_prop
= cpu_to_be32(pnv
->initrd_base
+ pnv
->initrd_size
);
541 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-start",
542 &start_prop
, sizeof(start_prop
))));
543 _FDT((fdt_setprop(fdt
, off
, "linux,initrd-end",
544 &end_prop
, sizeof(end_prop
))));
547 /* Populate device tree for each chip */
548 for (i
= 0; i
< pnv
->num_chips
; i
++) {
549 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->dt_populate(pnv
->chips
[i
], fdt
);
552 /* Populate ISA devices on chip 0 */
553 pnv_dt_isa(pnv
, fdt
);
556 pnv_dt_bmc_sensors(pnv
->bmc
, fdt
);
559 /* Create an extra node for power management on machines that support it */
560 if (pmc
->dt_power_mgt
) {
561 pmc
->dt_power_mgt(pnv
, fdt
);
567 static void pnv_powerdown_notify(Notifier
*n
, void *opaque
)
569 PnvMachineState
*pnv
= container_of(n
, PnvMachineState
, powerdown_notifier
);
572 pnv_bmc_powerdown(pnv
->bmc
);
576 static void pnv_reset(MachineState
*machine
)
578 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
582 qemu_devices_reset();
585 * The machine should provide by default an internal BMC simulator.
586 * If not, try to use the BMC device that was provided on the command
589 bmc
= pnv_bmc_find(&error_fatal
);
592 if (!qtest_enabled()) {
593 warn_report("machine has no BMC device. Use '-device "
594 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
598 pnv_bmc_set_pnor(bmc
, pnv
->pnor
);
603 fdt
= pnv_dt_create(machine
);
605 /* Pack resulting tree */
606 _FDT((fdt_pack(fdt
)));
608 qemu_fdt_dumpdtb(fdt
, fdt_totalsize(fdt
));
609 cpu_physical_memory_write(PNV_FDT_ADDR
, fdt
, fdt_totalsize(fdt
));
614 static ISABus
*pnv_chip_power8_isa_create(PnvChip
*chip
, Error
**errp
)
616 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
617 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip8
->psi
), PSIHB_IRQ_EXTERNAL
);
619 qdev_connect_gpio_out(DEVICE(&chip8
->lpc
), 0, irq
);
620 return pnv_lpc_isa_create(&chip8
->lpc
, true, errp
);
623 static ISABus
*pnv_chip_power8nvl_isa_create(PnvChip
*chip
, Error
**errp
)
625 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
626 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip8
->psi
), PSIHB_IRQ_LPC_I2C
);
628 qdev_connect_gpio_out(DEVICE(&chip8
->lpc
), 0, irq
);
629 return pnv_lpc_isa_create(&chip8
->lpc
, false, errp
);
632 static ISABus
*pnv_chip_power9_isa_create(PnvChip
*chip
, Error
**errp
)
634 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
635 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip9
->psi
), PSIHB9_IRQ_LPCHC
);
637 qdev_connect_gpio_out(DEVICE(&chip9
->lpc
), 0, irq
);
638 return pnv_lpc_isa_create(&chip9
->lpc
, false, errp
);
641 static ISABus
*pnv_chip_power10_isa_create(PnvChip
*chip
, Error
**errp
)
643 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
644 qemu_irq irq
= qdev_get_gpio_in(DEVICE(&chip10
->psi
), PSIHB9_IRQ_LPCHC
);
646 qdev_connect_gpio_out(DEVICE(&chip10
->lpc
), 0, irq
);
647 return pnv_lpc_isa_create(&chip10
->lpc
, false, errp
);
650 static ISABus
*pnv_isa_create(PnvChip
*chip
, Error
**errp
)
652 return PNV_CHIP_GET_CLASS(chip
)->isa_create(chip
, errp
);
655 static int pnv_chip_power8_pic_print_info_child(Object
*child
, void *opaque
)
657 Monitor
*mon
= opaque
;
658 PnvPHB3
*phb3
= (PnvPHB3
*) object_dynamic_cast(child
, TYPE_PNV_PHB3
);
661 pnv_phb3_msi_pic_print_info(&phb3
->msis
, mon
);
662 ics_pic_print_info(&phb3
->lsis
, mon
);
667 static void pnv_chip_power8_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
669 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
671 ics_pic_print_info(&chip8
->psi
.ics
, mon
);
672 object_child_foreach(OBJECT(chip
),
673 pnv_chip_power8_pic_print_info_child
, mon
);
676 static int pnv_chip_power9_pic_print_info_child(Object
*child
, void *opaque
)
678 Monitor
*mon
= opaque
;
679 PnvPHB4
*phb4
= (PnvPHB4
*) object_dynamic_cast(child
, TYPE_PNV_PHB4
);
682 pnv_phb4_pic_print_info(phb4
, mon
);
687 static void pnv_chip_power9_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
689 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
691 pnv_xive_pic_print_info(&chip9
->xive
, mon
);
692 pnv_psi_pic_print_info(&chip9
->psi
, mon
);
694 object_child_foreach_recursive(OBJECT(chip
),
695 pnv_chip_power9_pic_print_info_child
, mon
);
698 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip
*chip
,
701 return PNV_XSCOM_EX_BASE(core_id
);
704 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip
*chip
,
707 return PNV9_XSCOM_EC_BASE(core_id
);
710 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip
*chip
,
713 return PNV10_XSCOM_EC_BASE(core_id
);
716 static bool pnv_match_cpu(const char *default_type
, const char *cpu_type
)
718 PowerPCCPUClass
*ppc_default
=
719 POWERPC_CPU_CLASS(object_class_by_name(default_type
));
720 PowerPCCPUClass
*ppc
=
721 POWERPC_CPU_CLASS(object_class_by_name(cpu_type
));
723 return ppc_default
->pvr_match(ppc_default
, ppc
->pvr
);
726 static void pnv_ipmi_bt_init(ISABus
*bus
, IPMIBmc
*bmc
, uint32_t irq
)
728 ISADevice
*dev
= isa_new("isa-ipmi-bt");
730 object_property_set_link(OBJECT(dev
), "bmc", OBJECT(bmc
), &error_fatal
);
731 object_property_set_int(OBJECT(dev
), "irq", irq
, &error_fatal
);
732 isa_realize_and_unref(dev
, bus
, &error_fatal
);
735 static void pnv_chip_power10_pic_print_info(PnvChip
*chip
, Monitor
*mon
)
737 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
739 pnv_xive2_pic_print_info(&chip10
->xive
, mon
);
740 pnv_psi_pic_print_info(&chip10
->psi
, mon
);
742 object_child_foreach_recursive(OBJECT(chip
),
743 pnv_chip_power9_pic_print_info_child
, mon
);
746 /* Always give the first 1GB to chip 0 else we won't boot */
747 static uint64_t pnv_chip_get_ram_size(PnvMachineState
*pnv
, int chip_id
)
749 MachineState
*machine
= MACHINE(pnv
);
750 uint64_t ram_per_chip
;
752 assert(machine
->ram_size
>= 1 * GiB
);
754 ram_per_chip
= machine
->ram_size
/ pnv
->num_chips
;
755 if (ram_per_chip
>= 1 * GiB
) {
756 return QEMU_ALIGN_DOWN(ram_per_chip
, 1 * MiB
);
759 assert(pnv
->num_chips
> 1);
761 ram_per_chip
= (machine
->ram_size
- 1 * GiB
) / (pnv
->num_chips
- 1);
762 return chip_id
== 0 ? 1 * GiB
: QEMU_ALIGN_DOWN(ram_per_chip
, 1 * MiB
);
765 static void pnv_init(MachineState
*machine
)
767 const char *bios_name
= machine
->firmware
?: FW_FILE_NAME
;
768 PnvMachineState
*pnv
= PNV_MACHINE(machine
);
769 MachineClass
*mc
= MACHINE_GET_CLASS(machine
);
772 uint64_t chip_ram_start
= 0;
775 DriveInfo
*pnor
= drive_get(IF_MTD
, 0, 0);
779 error_report("The powernv machine does not work with KVM acceleration");
784 if (machine
->ram_size
< mc
->default_ram_size
) {
785 char *sz
= size_to_str(mc
->default_ram_size
);
786 error_report("Invalid RAM size, should be bigger than %s", sz
);
790 memory_region_add_subregion(get_system_memory(), 0, machine
->ram
);
793 * Create our simple PNOR device
795 dev
= qdev_new(TYPE_PNV_PNOR
);
797 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(pnor
));
799 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev
), &error_fatal
);
800 pnv
->pnor
= PNV_PNOR(dev
);
802 /* load skiboot firmware */
803 fw_filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
805 error_report("Could not find OPAL firmware '%s'", bios_name
);
809 fw_size
= load_image_targphys(fw_filename
, pnv
->fw_load_addr
, FW_MAX_SIZE
);
811 error_report("Could not load OPAL firmware '%s'", fw_filename
);
817 if (machine
->kernel_filename
) {
820 kernel_size
= load_image_targphys(machine
->kernel_filename
,
821 KERNEL_LOAD_ADDR
, KERNEL_MAX_SIZE
);
822 if (kernel_size
< 0) {
823 error_report("Could not load kernel '%s'",
824 machine
->kernel_filename
);
830 if (machine
->initrd_filename
) {
831 pnv
->initrd_base
= INITRD_LOAD_ADDR
;
832 pnv
->initrd_size
= load_image_targphys(machine
->initrd_filename
,
833 pnv
->initrd_base
, INITRD_MAX_SIZE
);
834 if (pnv
->initrd_size
< 0) {
835 error_report("Could not load initial ram disk '%s'",
836 machine
->initrd_filename
);
841 /* MSIs are supported on this platform */
842 msi_nonbroken
= true;
845 * Check compatibility of the specified CPU with the machine
848 if (!pnv_match_cpu(mc
->default_cpu_type
, machine
->cpu_type
)) {
849 error_report("invalid CPU model '%s' for %s machine",
850 machine
->cpu_type
, mc
->name
);
854 /* Create the processor chips */
855 i
= strlen(machine
->cpu_type
) - strlen(POWERPC_CPU_TYPE_SUFFIX
);
856 chip_typename
= g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
857 i
, machine
->cpu_type
);
858 if (!object_class_by_name(chip_typename
)) {
859 error_report("invalid chip model '%.*s' for %s machine",
860 i
, machine
->cpu_type
, mc
->name
);
865 machine
->smp
.max_cpus
/ (machine
->smp
.cores
* machine
->smp
.threads
);
867 * TODO: should we decide on how many chips we can create based
868 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
870 if (!is_power_of_2(pnv
->num_chips
) || pnv
->num_chips
> 16) {
871 error_report("invalid number of chips: '%d'", pnv
->num_chips
);
873 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
877 pnv
->chips
= g_new0(PnvChip
*, pnv
->num_chips
);
878 for (i
= 0; i
< pnv
->num_chips
; i
++) {
880 Object
*chip
= OBJECT(qdev_new(chip_typename
));
881 uint64_t chip_ram_size
= pnv_chip_get_ram_size(pnv
, i
);
883 pnv
->chips
[i
] = PNV_CHIP(chip
);
885 /* Distribute RAM among the chips */
886 object_property_set_int(chip
, "ram-start", chip_ram_start
,
888 object_property_set_int(chip
, "ram-size", chip_ram_size
,
890 chip_ram_start
+= chip_ram_size
;
892 snprintf(chip_name
, sizeof(chip_name
), "chip[%d]", i
);
893 object_property_add_child(OBJECT(pnv
), chip_name
, chip
);
894 object_property_set_int(chip
, "chip-id", i
, &error_fatal
);
895 object_property_set_int(chip
, "nr-cores", machine
->smp
.cores
,
897 object_property_set_int(chip
, "nr-threads", machine
->smp
.threads
,
900 * The POWER8 machine use the XICS interrupt interface.
901 * Propagate the XICS fabric to the chip and its controllers.
903 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XICS_FABRIC
)) {
904 object_property_set_link(chip
, "xics", OBJECT(pnv
), &error_abort
);
906 if (object_dynamic_cast(OBJECT(pnv
), TYPE_XIVE_FABRIC
)) {
907 object_property_set_link(chip
, "xive-fabric", OBJECT(pnv
),
910 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip
), &error_fatal
);
912 g_free(chip_typename
);
914 /* Instantiate ISA bus on chip 0 */
915 pnv
->isa_bus
= pnv_isa_create(pnv
->chips
[0], &error_fatal
);
917 /* Create serial port */
918 serial_hds_isa_init(pnv
->isa_bus
, 0, MAX_ISA_SERIAL_PORTS
);
920 /* Create an RTC ISA device too */
921 mc146818_rtc_init(pnv
->isa_bus
, 2000, NULL
);
924 * Create the machine BMC simulator and the IPMI BT device for
925 * communication with the BMC
927 if (defaults_enabled()) {
928 pnv
->bmc
= pnv_bmc_create(pnv
->pnor
);
929 pnv_ipmi_bt_init(pnv
->isa_bus
, pnv
->bmc
, 10);
933 * The PNOR is mapped on the LPC FW address space by the BMC.
934 * Since we can not reach the remote BMC machine with LPC memops,
935 * map it always for now.
937 memory_region_add_subregion(pnv
->chips
[0]->fw_mr
, PNOR_SPI_OFFSET
,
941 * OpenPOWER systems use a IPMI SEL Event message to notify the
944 pnv
->powerdown_notifier
.notify
= pnv_powerdown_notify
;
945 qemu_register_powerdown_notifier(&pnv
->powerdown_notifier
);
949 * 0:21 Reserved - Read as zeros
954 static uint32_t pnv_chip_core_pir_p8(PnvChip
*chip
, uint32_t core_id
)
956 return (chip
->chip_id
<< 7) | (core_id
<< 3);
959 static void pnv_chip_power8_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
962 Pnv8Chip
*chip8
= PNV8_CHIP(chip
);
963 Error
*local_err
= NULL
;
965 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
967 obj
= icp_create(OBJECT(cpu
), TYPE_PNV_ICP
, chip8
->xics
, &local_err
);
969 error_propagate(errp
, local_err
);
977 static void pnv_chip_power8_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
979 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
981 icp_reset(ICP(pnv_cpu
->intc
));
984 static void pnv_chip_power8_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
986 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
988 icp_destroy(ICP(pnv_cpu
->intc
));
989 pnv_cpu
->intc
= NULL
;
992 static void pnv_chip_power8_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
995 icp_pic_print_info(ICP(pnv_cpu_state(cpu
)->intc
), mon
);
999 * 0:48 Reserved - Read as zeroes
1002 * 56 Reserved - Read as zero
1006 * We only care about the lower bits. uint32_t is fine for the moment.
1008 static uint32_t pnv_chip_core_pir_p9(PnvChip
*chip
, uint32_t core_id
)
1010 return (chip
->chip_id
<< 8) | (core_id
<< 2);
1013 static uint32_t pnv_chip_core_pir_p10(PnvChip
*chip
, uint32_t core_id
)
1015 return (chip
->chip_id
<< 8) | (core_id
<< 2);
1018 static void pnv_chip_power9_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1021 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
1022 Error
*local_err
= NULL
;
1024 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1027 * The core creates its interrupt presenter but the XIVE interrupt
1028 * controller object is initialized afterwards. Hopefully, it's
1029 * only used at runtime.
1031 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip9
->xive
),
1034 error_propagate(errp
, local_err
);
1038 pnv_cpu
->intc
= obj
;
1041 static void pnv_chip_power9_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1043 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1045 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
1048 static void pnv_chip_power9_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1050 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1052 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
1053 pnv_cpu
->intc
= NULL
;
1056 static void pnv_chip_power9_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1059 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1062 static void pnv_chip_power10_intc_create(PnvChip
*chip
, PowerPCCPU
*cpu
,
1065 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
1066 Error
*local_err
= NULL
;
1068 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1071 * The core creates its interrupt presenter but the XIVE2 interrupt
1072 * controller object is initialized afterwards. Hopefully, it's
1073 * only used at runtime.
1075 obj
= xive_tctx_create(OBJECT(cpu
), XIVE_PRESENTER(&chip10
->xive
),
1078 error_propagate(errp
, local_err
);
1082 pnv_cpu
->intc
= obj
;
1085 static void pnv_chip_power10_intc_reset(PnvChip
*chip
, PowerPCCPU
*cpu
)
1087 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1089 xive_tctx_reset(XIVE_TCTX(pnv_cpu
->intc
));
1092 static void pnv_chip_power10_intc_destroy(PnvChip
*chip
, PowerPCCPU
*cpu
)
1094 PnvCPUState
*pnv_cpu
= pnv_cpu_state(cpu
);
1096 xive_tctx_destroy(XIVE_TCTX(pnv_cpu
->intc
));
1097 pnv_cpu
->intc
= NULL
;
1100 static void pnv_chip_power10_intc_print_info(PnvChip
*chip
, PowerPCCPU
*cpu
,
1103 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu
)->intc
), mon
);
1107 * Allowed core identifiers on a POWER8 Processor Chip :
1116 * <EX7,8 reserved> <reserved>
1118 * EX10 - Venice only
1119 * EX11 - Venice only
1125 #define POWER8E_CORE_MASK (0x7070ull)
1126 #define POWER8_CORE_MASK (0x7e7eull)
1129 * POWER9 has 24 cores, ids starting at 0x0
1131 #define POWER9_CORE_MASK (0xffffffffffffffull)
1134 #define POWER10_CORE_MASK (0xffffffffffffffull)
1136 static void pnv_chip_power8_instance_init(Object
*obj
)
1138 Pnv8Chip
*chip8
= PNV8_CHIP(obj
);
1139 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1142 object_property_add_link(obj
, "xics", TYPE_XICS_FABRIC
,
1143 (Object
**)&chip8
->xics
,
1144 object_property_allow_set_link
,
1145 OBJ_PROP_LINK_STRONG
);
1147 object_initialize_child(obj
, "psi", &chip8
->psi
, TYPE_PNV8_PSI
);
1149 object_initialize_child(obj
, "lpc", &chip8
->lpc
, TYPE_PNV8_LPC
);
1151 object_initialize_child(obj
, "occ", &chip8
->occ
, TYPE_PNV8_OCC
);
1153 object_initialize_child(obj
, "homer", &chip8
->homer
, TYPE_PNV8_HOMER
);
1155 chip8
->num_phbs
= pcc
->num_phbs
;
1157 for (i
= 0; i
< chip8
->num_phbs
; i
++) {
1158 object_initialize_child(obj
, "phb[*]", &chip8
->phbs
[i
], TYPE_PNV_PHB3
);
1163 static void pnv_chip_icp_realize(Pnv8Chip
*chip8
, Error
**errp
)
1165 PnvChip
*chip
= PNV_CHIP(chip8
);
1166 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1170 name
= g_strdup_printf("icp-%x", chip
->chip_id
);
1171 memory_region_init(&chip8
->icp_mmio
, OBJECT(chip
), name
, PNV_ICP_SIZE
);
1172 sysbus_init_mmio(SYS_BUS_DEVICE(chip
), &chip8
->icp_mmio
);
1175 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 1, PNV_ICP_BASE(chip
));
1177 /* Map the ICP registers for each thread */
1178 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1179 PnvCore
*pnv_core
= chip
->cores
[i
];
1180 int core_hwid
= CPU_CORE(pnv_core
)->core_id
;
1182 for (j
= 0; j
< CPU_CORE(pnv_core
)->nr_threads
; j
++) {
1183 uint32_t pir
= pcc
->core_pir(chip
, core_hwid
) + j
;
1184 PnvICPState
*icp
= PNV_ICP(xics_icp_get(chip8
->xics
, pir
));
1186 memory_region_add_subregion(&chip8
->icp_mmio
, pir
<< 12,
1192 /* Attach a root port device */
1193 void pnv_phb_attach_root_port(PCIHostState
*pci
, const char *name
)
1195 PCIDevice
*root
= pci_new(PCI_DEVFN(0, 0), name
);
1197 pci_realize_and_unref(root
, pci
->bus
, &error_fatal
);
1200 static void pnv_chip_power8_realize(DeviceState
*dev
, Error
**errp
)
1202 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1203 PnvChip
*chip
= PNV_CHIP(dev
);
1204 Pnv8Chip
*chip8
= PNV8_CHIP(dev
);
1205 Pnv8Psi
*psi8
= &chip8
->psi
;
1206 Error
*local_err
= NULL
;
1209 assert(chip8
->xics
);
1211 /* XSCOM bridge is first */
1212 pnv_xscom_realize(chip
, PNV_XSCOM_SIZE
, &local_err
);
1214 error_propagate(errp
, local_err
);
1217 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV_XSCOM_BASE(chip
));
1219 pcc
->parent_realize(dev
, &local_err
);
1221 error_propagate(errp
, local_err
);
1225 /* Processor Service Interface (PSI) Host Bridge */
1226 object_property_set_int(OBJECT(&chip8
->psi
), "bar", PNV_PSIHB_BASE(chip
),
1228 object_property_set_link(OBJECT(&chip8
->psi
), ICS_PROP_XICS
,
1229 OBJECT(chip8
->xics
), &error_abort
);
1230 if (!qdev_realize(DEVICE(&chip8
->psi
), NULL
, errp
)) {
1233 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PSIHB_BASE
,
1234 &PNV_PSI(psi8
)->xscom_regs
);
1236 /* Create LPC controller */
1237 qdev_realize(DEVICE(&chip8
->lpc
), NULL
, &error_fatal
);
1238 pnv_xscom_add_subregion(chip
, PNV_XSCOM_LPC_BASE
, &chip8
->lpc
.xscom_regs
);
1240 chip
->fw_mr
= &chip8
->lpc
.isa_fw
;
1241 chip
->dt_isa_nodename
= g_strdup_printf("/xscom@%" PRIx64
"/isa@%x",
1242 (uint64_t) PNV_XSCOM_BASE(chip
),
1243 PNV_XSCOM_LPC_BASE
);
1246 * Interrupt Management Area. This is the memory region holding
1247 * all the Interrupt Control Presenter (ICP) registers
1249 pnv_chip_icp_realize(chip8
, &local_err
);
1251 error_propagate(errp
, local_err
);
1255 /* Create the simplified OCC model */
1256 if (!qdev_realize(DEVICE(&chip8
->occ
), NULL
, errp
)) {
1259 pnv_xscom_add_subregion(chip
, PNV_XSCOM_OCC_BASE
, &chip8
->occ
.xscom_regs
);
1260 qdev_connect_gpio_out(DEVICE(&chip8
->occ
), 0,
1261 qdev_get_gpio_in(DEVICE(&chip8
->psi
), PSIHB_IRQ_OCC
));
1263 /* OCC SRAM model */
1264 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip
),
1265 &chip8
->occ
.sram_regs
);
1268 object_property_set_link(OBJECT(&chip8
->homer
), "chip", OBJECT(chip
),
1270 if (!qdev_realize(DEVICE(&chip8
->homer
), NULL
, errp
)) {
1273 /* Homer Xscom region */
1274 pnv_xscom_add_subregion(chip
, PNV_XSCOM_PBA_BASE
, &chip8
->homer
.pba_regs
);
1276 /* Homer mmio region */
1277 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip
),
1278 &chip8
->homer
.regs
);
1280 /* PHB3 controllers */
1281 for (i
= 0; i
< chip8
->num_phbs
; i
++) {
1282 PnvPHB3
*phb
= &chip8
->phbs
[i
];
1284 object_property_set_int(OBJECT(phb
), "index", i
, &error_fatal
);
1285 object_property_set_int(OBJECT(phb
), "chip-id", chip
->chip_id
,
1287 object_property_set_link(OBJECT(phb
), "chip", OBJECT(chip
),
1289 if (!sysbus_realize(SYS_BUS_DEVICE(phb
), errp
)) {
1295 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1297 addr
&= (PNV_XSCOM_SIZE
- 1);
1298 return ((addr
>> 4) & ~0xfull
) | ((addr
>> 3) & 0xf);
1301 static void pnv_chip_power8e_class_init(ObjectClass
*klass
, void *data
)
1303 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1304 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1306 k
->chip_cfam_id
= 0x221ef04980000000ull
; /* P8 Murano DD2.1 */
1307 k
->cores_mask
= POWER8E_CORE_MASK
;
1309 k
->core_pir
= pnv_chip_core_pir_p8
;
1310 k
->intc_create
= pnv_chip_power8_intc_create
;
1311 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1312 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1313 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1314 k
->isa_create
= pnv_chip_power8_isa_create
;
1315 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1316 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1317 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1318 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1319 dc
->desc
= "PowerNV Chip POWER8E";
1321 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1322 &k
->parent_realize
);
1325 static void pnv_chip_power8_class_init(ObjectClass
*klass
, void *data
)
1327 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1328 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1330 k
->chip_cfam_id
= 0x220ea04980000000ull
; /* P8 Venice DD2.0 */
1331 k
->cores_mask
= POWER8_CORE_MASK
;
1333 k
->core_pir
= pnv_chip_core_pir_p8
;
1334 k
->intc_create
= pnv_chip_power8_intc_create
;
1335 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1336 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1337 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1338 k
->isa_create
= pnv_chip_power8_isa_create
;
1339 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1340 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1341 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1342 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1343 dc
->desc
= "PowerNV Chip POWER8";
1345 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1346 &k
->parent_realize
);
1349 static void pnv_chip_power8nvl_class_init(ObjectClass
*klass
, void *data
)
1351 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1352 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1354 k
->chip_cfam_id
= 0x120d304980000000ull
; /* P8 Naples DD1.0 */
1355 k
->cores_mask
= POWER8_CORE_MASK
;
1357 k
->core_pir
= pnv_chip_core_pir_p8
;
1358 k
->intc_create
= pnv_chip_power8_intc_create
;
1359 k
->intc_reset
= pnv_chip_power8_intc_reset
;
1360 k
->intc_destroy
= pnv_chip_power8_intc_destroy
;
1361 k
->intc_print_info
= pnv_chip_power8_intc_print_info
;
1362 k
->isa_create
= pnv_chip_power8nvl_isa_create
;
1363 k
->dt_populate
= pnv_chip_power8_dt_populate
;
1364 k
->pic_print_info
= pnv_chip_power8_pic_print_info
;
1365 k
->xscom_core_base
= pnv_chip_power8_xscom_core_base
;
1366 k
->xscom_pcba
= pnv_chip_power8_xscom_pcba
;
1367 dc
->desc
= "PowerNV Chip POWER8NVL";
1369 device_class_set_parent_realize(dc
, pnv_chip_power8_realize
,
1370 &k
->parent_realize
);
1373 static void pnv_chip_power9_instance_init(Object
*obj
)
1375 PnvChip
*chip
= PNV_CHIP(obj
);
1376 Pnv9Chip
*chip9
= PNV9_CHIP(obj
);
1377 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1380 object_initialize_child(obj
, "xive", &chip9
->xive
, TYPE_PNV_XIVE
);
1381 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip9
->xive
),
1384 object_initialize_child(obj
, "psi", &chip9
->psi
, TYPE_PNV9_PSI
);
1386 object_initialize_child(obj
, "lpc", &chip9
->lpc
, TYPE_PNV9_LPC
);
1388 object_initialize_child(obj
, "occ", &chip9
->occ
, TYPE_PNV9_OCC
);
1390 object_initialize_child(obj
, "homer", &chip9
->homer
, TYPE_PNV9_HOMER
);
1392 /* Number of PECs is the chip default */
1393 chip
->num_pecs
= pcc
->num_pecs
;
1395 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1396 object_initialize_child(obj
, "pec[*]", &chip9
->pecs
[i
],
1401 static void pnv_chip_quad_realize_one(PnvChip
*chip
, PnvQuad
*eq
,
1405 int core_id
= CPU_CORE(pnv_core
)->core_id
;
1407 snprintf(eq_name
, sizeof(eq_name
), "eq[%d]", core_id
);
1408 object_initialize_child_with_props(OBJECT(chip
), eq_name
, eq
,
1409 sizeof(*eq
), TYPE_PNV_QUAD
,
1410 &error_fatal
, NULL
);
1412 object_property_set_int(OBJECT(eq
), "quad-id", core_id
, &error_fatal
);
1413 qdev_realize(DEVICE(eq
), NULL
, &error_fatal
);
1416 static void pnv_chip_quad_realize(Pnv9Chip
*chip9
, Error
**errp
)
1418 PnvChip
*chip
= PNV_CHIP(chip9
);
1421 chip9
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1422 chip9
->quads
= g_new0(PnvQuad
, chip9
->nr_quads
);
1424 for (i
= 0; i
< chip9
->nr_quads
; i
++) {
1425 PnvQuad
*eq
= &chip9
->quads
[i
];
1427 pnv_chip_quad_realize_one(chip
, eq
, chip
->cores
[i
* 4]);
1429 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_EQ_BASE(eq
->quad_id
),
1434 static void pnv_chip_power9_pec_realize(PnvChip
*chip
, Error
**errp
)
1436 Pnv9Chip
*chip9
= PNV9_CHIP(chip
);
1439 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1440 PnvPhb4PecState
*pec
= &chip9
->pecs
[i
];
1441 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
1442 uint32_t pec_nest_base
;
1443 uint32_t pec_pci_base
;
1445 object_property_set_int(OBJECT(pec
), "index", i
, &error_fatal
);
1446 object_property_set_int(OBJECT(pec
), "chip-id", chip
->chip_id
,
1448 object_property_set_link(OBJECT(pec
), "chip", OBJECT(chip
),
1450 if (!qdev_realize(DEVICE(pec
), NULL
, errp
)) {
1454 pec_nest_base
= pecc
->xscom_nest_base(pec
);
1455 pec_pci_base
= pecc
->xscom_pci_base(pec
);
1457 pnv_xscom_add_subregion(chip
, pec_nest_base
, &pec
->nest_regs_mr
);
1458 pnv_xscom_add_subregion(chip
, pec_pci_base
, &pec
->pci_regs_mr
);
1462 static void pnv_chip_power9_realize(DeviceState
*dev
, Error
**errp
)
1464 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1465 Pnv9Chip
*chip9
= PNV9_CHIP(dev
);
1466 PnvChip
*chip
= PNV_CHIP(dev
);
1467 Pnv9Psi
*psi9
= &chip9
->psi
;
1468 Error
*local_err
= NULL
;
1470 /* XSCOM bridge is first */
1471 pnv_xscom_realize(chip
, PNV9_XSCOM_SIZE
, &local_err
);
1473 error_propagate(errp
, local_err
);
1476 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV9_XSCOM_BASE(chip
));
1478 pcc
->parent_realize(dev
, &local_err
);
1480 error_propagate(errp
, local_err
);
1484 pnv_chip_quad_realize(chip9
, &local_err
);
1486 error_propagate(errp
, local_err
);
1490 /* XIVE interrupt controller (POWER9) */
1491 object_property_set_int(OBJECT(&chip9
->xive
), "ic-bar",
1492 PNV9_XIVE_IC_BASE(chip
), &error_fatal
);
1493 object_property_set_int(OBJECT(&chip9
->xive
), "vc-bar",
1494 PNV9_XIVE_VC_BASE(chip
), &error_fatal
);
1495 object_property_set_int(OBJECT(&chip9
->xive
), "pc-bar",
1496 PNV9_XIVE_PC_BASE(chip
), &error_fatal
);
1497 object_property_set_int(OBJECT(&chip9
->xive
), "tm-bar",
1498 PNV9_XIVE_TM_BASE(chip
), &error_fatal
);
1499 object_property_set_link(OBJECT(&chip9
->xive
), "chip", OBJECT(chip
),
1501 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9
->xive
), errp
)) {
1504 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_XIVE_BASE
,
1505 &chip9
->xive
.xscom_regs
);
1507 /* Processor Service Interface (PSI) Host Bridge */
1508 object_property_set_int(OBJECT(&chip9
->psi
), "bar", PNV9_PSIHB_BASE(chip
),
1510 /* This is the only device with 4k ESB pages */
1511 object_property_set_int(OBJECT(&chip9
->psi
), "shift", XIVE_ESB_4K
,
1513 if (!qdev_realize(DEVICE(&chip9
->psi
), NULL
, errp
)) {
1516 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PSIHB_BASE
,
1517 &PNV_PSI(psi9
)->xscom_regs
);
1520 if (!qdev_realize(DEVICE(&chip9
->lpc
), NULL
, errp
)) {
1523 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip
),
1524 &chip9
->lpc
.xscom_regs
);
1526 chip
->fw_mr
= &chip9
->lpc
.isa_fw
;
1527 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1528 (uint64_t) PNV9_LPCM_BASE(chip
));
1530 /* Create the simplified OCC model */
1531 if (!qdev_realize(DEVICE(&chip9
->occ
), NULL
, errp
)) {
1534 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_OCC_BASE
, &chip9
->occ
.xscom_regs
);
1535 qdev_connect_gpio_out(DEVICE(&chip9
->occ
), 0, qdev_get_gpio_in(
1536 DEVICE(&chip9
->psi
), PSIHB9_IRQ_OCC
));
1538 /* OCC SRAM model */
1539 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip
),
1540 &chip9
->occ
.sram_regs
);
1543 object_property_set_link(OBJECT(&chip9
->homer
), "chip", OBJECT(chip
),
1545 if (!qdev_realize(DEVICE(&chip9
->homer
), NULL
, errp
)) {
1548 /* Homer Xscom region */
1549 pnv_xscom_add_subregion(chip
, PNV9_XSCOM_PBA_BASE
, &chip9
->homer
.pba_regs
);
1551 /* Homer mmio region */
1552 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip
),
1553 &chip9
->homer
.regs
);
1556 pnv_chip_power9_pec_realize(chip
, &local_err
);
1558 error_propagate(errp
, local_err
);
1563 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1565 addr
&= (PNV9_XSCOM_SIZE
- 1);
1569 static void pnv_chip_power9_class_init(ObjectClass
*klass
, void *data
)
1571 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1572 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1574 k
->chip_cfam_id
= 0x220d104900008000ull
; /* P9 Nimbus DD2.0 */
1575 k
->cores_mask
= POWER9_CORE_MASK
;
1576 k
->core_pir
= pnv_chip_core_pir_p9
;
1577 k
->intc_create
= pnv_chip_power9_intc_create
;
1578 k
->intc_reset
= pnv_chip_power9_intc_reset
;
1579 k
->intc_destroy
= pnv_chip_power9_intc_destroy
;
1580 k
->intc_print_info
= pnv_chip_power9_intc_print_info
;
1581 k
->isa_create
= pnv_chip_power9_isa_create
;
1582 k
->dt_populate
= pnv_chip_power9_dt_populate
;
1583 k
->pic_print_info
= pnv_chip_power9_pic_print_info
;
1584 k
->xscom_core_base
= pnv_chip_power9_xscom_core_base
;
1585 k
->xscom_pcba
= pnv_chip_power9_xscom_pcba
;
1586 dc
->desc
= "PowerNV Chip POWER9";
1587 k
->num_pecs
= PNV9_CHIP_MAX_PEC
;
1589 device_class_set_parent_realize(dc
, pnv_chip_power9_realize
,
1590 &k
->parent_realize
);
1593 static void pnv_chip_power10_instance_init(Object
*obj
)
1595 PnvChip
*chip
= PNV_CHIP(obj
);
1596 Pnv10Chip
*chip10
= PNV10_CHIP(obj
);
1597 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(obj
);
1600 object_initialize_child(obj
, "xive", &chip10
->xive
, TYPE_PNV_XIVE2
);
1601 object_property_add_alias(obj
, "xive-fabric", OBJECT(&chip10
->xive
),
1603 object_initialize_child(obj
, "psi", &chip10
->psi
, TYPE_PNV10_PSI
);
1604 object_initialize_child(obj
, "lpc", &chip10
->lpc
, TYPE_PNV10_LPC
);
1605 object_initialize_child(obj
, "occ", &chip10
->occ
, TYPE_PNV10_OCC
);
1606 object_initialize_child(obj
, "homer", &chip10
->homer
, TYPE_PNV10_HOMER
);
1608 chip
->num_pecs
= pcc
->num_pecs
;
1610 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1611 object_initialize_child(obj
, "pec[*]", &chip10
->pecs
[i
],
1616 static void pnv_chip_power10_quad_realize(Pnv10Chip
*chip10
, Error
**errp
)
1618 PnvChip
*chip
= PNV_CHIP(chip10
);
1621 chip10
->nr_quads
= DIV_ROUND_UP(chip
->nr_cores
, 4);
1622 chip10
->quads
= g_new0(PnvQuad
, chip10
->nr_quads
);
1624 for (i
= 0; i
< chip10
->nr_quads
; i
++) {
1625 PnvQuad
*eq
= &chip10
->quads
[i
];
1627 pnv_chip_quad_realize_one(chip
, eq
, chip
->cores
[i
* 4]);
1629 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_EQ_BASE(eq
->quad_id
),
1634 static void pnv_chip_power10_phb_realize(PnvChip
*chip
, Error
**errp
)
1636 Pnv10Chip
*chip10
= PNV10_CHIP(chip
);
1639 for (i
= 0; i
< chip
->num_pecs
; i
++) {
1640 PnvPhb4PecState
*pec
= &chip10
->pecs
[i
];
1641 PnvPhb4PecClass
*pecc
= PNV_PHB4_PEC_GET_CLASS(pec
);
1642 uint32_t pec_nest_base
;
1643 uint32_t pec_pci_base
;
1645 object_property_set_int(OBJECT(pec
), "index", i
, &error_fatal
);
1646 object_property_set_int(OBJECT(pec
), "chip-id", chip
->chip_id
,
1648 object_property_set_link(OBJECT(pec
), "chip", OBJECT(chip
),
1650 if (!qdev_realize(DEVICE(pec
), NULL
, errp
)) {
1654 pec_nest_base
= pecc
->xscom_nest_base(pec
);
1655 pec_pci_base
= pecc
->xscom_pci_base(pec
);
1657 pnv_xscom_add_subregion(chip
, pec_nest_base
, &pec
->nest_regs_mr
);
1658 pnv_xscom_add_subregion(chip
, pec_pci_base
, &pec
->pci_regs_mr
);
1662 static void pnv_chip_power10_realize(DeviceState
*dev
, Error
**errp
)
1664 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(dev
);
1665 PnvChip
*chip
= PNV_CHIP(dev
);
1666 Pnv10Chip
*chip10
= PNV10_CHIP(dev
);
1667 Error
*local_err
= NULL
;
1669 /* XSCOM bridge is first */
1670 pnv_xscom_realize(chip
, PNV10_XSCOM_SIZE
, &local_err
);
1672 error_propagate(errp
, local_err
);
1675 sysbus_mmio_map(SYS_BUS_DEVICE(chip
), 0, PNV10_XSCOM_BASE(chip
));
1677 pcc
->parent_realize(dev
, &local_err
);
1679 error_propagate(errp
, local_err
);
1683 pnv_chip_power10_quad_realize(chip10
, &local_err
);
1685 error_propagate(errp
, local_err
);
1689 /* XIVE2 interrupt controller (POWER10) */
1690 object_property_set_int(OBJECT(&chip10
->xive
), "ic-bar",
1691 PNV10_XIVE2_IC_BASE(chip
), &error_fatal
);
1692 object_property_set_int(OBJECT(&chip10
->xive
), "esb-bar",
1693 PNV10_XIVE2_ESB_BASE(chip
), &error_fatal
);
1694 object_property_set_int(OBJECT(&chip10
->xive
), "end-bar",
1695 PNV10_XIVE2_END_BASE(chip
), &error_fatal
);
1696 object_property_set_int(OBJECT(&chip10
->xive
), "nvpg-bar",
1697 PNV10_XIVE2_NVPG_BASE(chip
), &error_fatal
);
1698 object_property_set_int(OBJECT(&chip10
->xive
), "nvc-bar",
1699 PNV10_XIVE2_NVC_BASE(chip
), &error_fatal
);
1700 object_property_set_int(OBJECT(&chip10
->xive
), "tm-bar",
1701 PNV10_XIVE2_TM_BASE(chip
), &error_fatal
);
1702 object_property_set_link(OBJECT(&chip10
->xive
), "chip", OBJECT(chip
),
1704 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10
->xive
), errp
)) {
1707 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_XIVE2_BASE
,
1708 &chip10
->xive
.xscom_regs
);
1710 /* Processor Service Interface (PSI) Host Bridge */
1711 object_property_set_int(OBJECT(&chip10
->psi
), "bar",
1712 PNV10_PSIHB_BASE(chip
), &error_fatal
);
1713 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1714 object_property_set_int(OBJECT(&chip10
->psi
), "shift", XIVE_ESB_64K
,
1716 if (!qdev_realize(DEVICE(&chip10
->psi
), NULL
, errp
)) {
1719 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PSIHB_BASE
,
1720 &PNV_PSI(&chip10
->psi
)->xscom_regs
);
1723 if (!qdev_realize(DEVICE(&chip10
->lpc
), NULL
, errp
)) {
1726 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip
),
1727 &chip10
->lpc
.xscom_regs
);
1729 chip
->fw_mr
= &chip10
->lpc
.isa_fw
;
1730 chip
->dt_isa_nodename
= g_strdup_printf("/lpcm-opb@%" PRIx64
"/lpc@0",
1731 (uint64_t) PNV10_LPCM_BASE(chip
));
1733 /* Create the simplified OCC model */
1734 if (!qdev_realize(DEVICE(&chip10
->occ
), NULL
, errp
)) {
1737 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_OCC_BASE
,
1738 &chip10
->occ
.xscom_regs
);
1739 qdev_connect_gpio_out(DEVICE(&chip10
->occ
), 0, qdev_get_gpio_in(
1740 DEVICE(&chip10
->psi
), PSIHB9_IRQ_OCC
));
1742 /* OCC SRAM model */
1743 memory_region_add_subregion(get_system_memory(),
1744 PNV10_OCC_SENSOR_BASE(chip
),
1745 &chip10
->occ
.sram_regs
);
1748 object_property_set_link(OBJECT(&chip10
->homer
), "chip", OBJECT(chip
),
1750 if (!qdev_realize(DEVICE(&chip10
->homer
), NULL
, errp
)) {
1753 /* Homer Xscom region */
1754 pnv_xscom_add_subregion(chip
, PNV10_XSCOM_PBA_BASE
,
1755 &chip10
->homer
.pba_regs
);
1757 /* Homer mmio region */
1758 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip
),
1759 &chip10
->homer
.regs
);
1762 pnv_chip_power10_phb_realize(chip
, &local_err
);
1764 error_propagate(errp
, local_err
);
1769 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip
*chip
, uint64_t addr
)
1771 addr
&= (PNV10_XSCOM_SIZE
- 1);
1775 static void pnv_chip_power10_class_init(ObjectClass
*klass
, void *data
)
1777 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1778 PnvChipClass
*k
= PNV_CHIP_CLASS(klass
);
1780 k
->chip_cfam_id
= 0x120da04900008000ull
; /* P10 DD1.0 (with NX) */
1781 k
->cores_mask
= POWER10_CORE_MASK
;
1782 k
->core_pir
= pnv_chip_core_pir_p10
;
1783 k
->intc_create
= pnv_chip_power10_intc_create
;
1784 k
->intc_reset
= pnv_chip_power10_intc_reset
;
1785 k
->intc_destroy
= pnv_chip_power10_intc_destroy
;
1786 k
->intc_print_info
= pnv_chip_power10_intc_print_info
;
1787 k
->isa_create
= pnv_chip_power10_isa_create
;
1788 k
->dt_populate
= pnv_chip_power10_dt_populate
;
1789 k
->pic_print_info
= pnv_chip_power10_pic_print_info
;
1790 k
->xscom_core_base
= pnv_chip_power10_xscom_core_base
;
1791 k
->xscom_pcba
= pnv_chip_power10_xscom_pcba
;
1792 dc
->desc
= "PowerNV Chip POWER10";
1793 k
->num_pecs
= PNV10_CHIP_MAX_PEC
;
1795 device_class_set_parent_realize(dc
, pnv_chip_power10_realize
,
1796 &k
->parent_realize
);
1799 static void pnv_chip_core_sanitize(PnvChip
*chip
, Error
**errp
)
1801 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1805 * No custom mask for this chip, let's use the default one from *
1808 if (!chip
->cores_mask
) {
1809 chip
->cores_mask
= pcc
->cores_mask
;
1812 /* filter alien core ids ! some are reserved */
1813 if ((chip
->cores_mask
& pcc
->cores_mask
) != chip
->cores_mask
) {
1814 error_setg(errp
, "warning: invalid core mask for chip Ox%"PRIx64
" !",
1818 chip
->cores_mask
&= pcc
->cores_mask
;
1820 /* now that we have a sane layout, let check the number of cores */
1821 cores_max
= ctpop64(chip
->cores_mask
);
1822 if (chip
->nr_cores
> cores_max
) {
1823 error_setg(errp
, "warning: too many cores for chip ! Limit is %d",
1829 static void pnv_chip_core_realize(PnvChip
*chip
, Error
**errp
)
1831 Error
*error
= NULL
;
1832 PnvChipClass
*pcc
= PNV_CHIP_GET_CLASS(chip
);
1833 const char *typename
= pnv_chip_core_typename(chip
);
1835 PnvMachineState
*pnv
= PNV_MACHINE(qdev_get_machine());
1837 if (!object_class_by_name(typename
)) {
1838 error_setg(errp
, "Unable to find PowerNV CPU Core '%s'", typename
);
1843 pnv_chip_core_sanitize(chip
, &error
);
1845 error_propagate(errp
, error
);
1849 chip
->cores
= g_new0(PnvCore
*, chip
->nr_cores
);
1851 for (i
= 0, core_hwid
= 0; (core_hwid
< sizeof(chip
->cores_mask
) * 8)
1852 && (i
< chip
->nr_cores
); core_hwid
++) {
1855 uint64_t xscom_core_base
;
1857 if (!(chip
->cores_mask
& (1ull << core_hwid
))) {
1861 pnv_core
= PNV_CORE(object_new(typename
));
1863 snprintf(core_name
, sizeof(core_name
), "core[%d]", core_hwid
);
1864 object_property_add_child(OBJECT(chip
), core_name
, OBJECT(pnv_core
));
1865 chip
->cores
[i
] = pnv_core
;
1866 object_property_set_int(OBJECT(pnv_core
), "nr-threads",
1867 chip
->nr_threads
, &error_fatal
);
1868 object_property_set_int(OBJECT(pnv_core
), CPU_CORE_PROP_CORE_ID
,
1869 core_hwid
, &error_fatal
);
1870 object_property_set_int(OBJECT(pnv_core
), "pir",
1871 pcc
->core_pir(chip
, core_hwid
), &error_fatal
);
1872 object_property_set_int(OBJECT(pnv_core
), "hrmor", pnv
->fw_load_addr
,
1874 object_property_set_link(OBJECT(pnv_core
), "chip", OBJECT(chip
),
1876 qdev_realize(DEVICE(pnv_core
), NULL
, &error_fatal
);
1878 /* Each core has an XSCOM MMIO region */
1879 xscom_core_base
= pcc
->xscom_core_base(chip
, core_hwid
);
1881 pnv_xscom_add_subregion(chip
, xscom_core_base
,
1882 &pnv_core
->xscom_regs
);
1887 static void pnv_chip_realize(DeviceState
*dev
, Error
**errp
)
1889 PnvChip
*chip
= PNV_CHIP(dev
);
1890 Error
*error
= NULL
;
1893 pnv_chip_core_realize(chip
, &error
);
1895 error_propagate(errp
, error
);
1900 static Property pnv_chip_properties
[] = {
1901 DEFINE_PROP_UINT32("chip-id", PnvChip
, chip_id
, 0),
1902 DEFINE_PROP_UINT64("ram-start", PnvChip
, ram_start
, 0),
1903 DEFINE_PROP_UINT64("ram-size", PnvChip
, ram_size
, 0),
1904 DEFINE_PROP_UINT32("nr-cores", PnvChip
, nr_cores
, 1),
1905 DEFINE_PROP_UINT64("cores-mask", PnvChip
, cores_mask
, 0x0),
1906 DEFINE_PROP_UINT32("nr-threads", PnvChip
, nr_threads
, 1),
1907 DEFINE_PROP_END_OF_LIST(),
1910 static void pnv_chip_class_init(ObjectClass
*klass
, void *data
)
1912 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1914 set_bit(DEVICE_CATEGORY_CPU
, dc
->categories
);
1915 dc
->realize
= pnv_chip_realize
;
1916 device_class_set_props(dc
, pnv_chip_properties
);
1917 dc
->desc
= "PowerNV Chip";
1920 PowerPCCPU
*pnv_chip_find_cpu(PnvChip
*chip
, uint32_t pir
)
1924 for (i
= 0; i
< chip
->nr_cores
; i
++) {
1925 PnvCore
*pc
= chip
->cores
[i
];
1926 CPUCore
*cc
= CPU_CORE(pc
);
1928 for (j
= 0; j
< cc
->nr_threads
; j
++) {
1929 if (ppc_cpu_pir(pc
->threads
[j
]) == pir
) {
1930 return pc
->threads
[j
];
1937 typedef struct ForeachPhb3Args
{
1942 static int pnv_ics_get_child(Object
*child
, void *opaque
)
1944 ForeachPhb3Args
*args
= opaque
;
1945 PnvPHB3
*phb3
= (PnvPHB3
*) object_dynamic_cast(child
, TYPE_PNV_PHB3
);
1948 if (ics_valid_irq(&phb3
->lsis
, args
->irq
)) {
1949 args
->ics
= &phb3
->lsis
;
1951 if (ics_valid_irq(ICS(&phb3
->msis
), args
->irq
)) {
1952 args
->ics
= ICS(&phb3
->msis
);
1955 return args
->ics
? 1 : 0;
1958 static ICSState
*pnv_ics_get(XICSFabric
*xi
, int irq
)
1960 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
1961 ForeachPhb3Args args
= { irq
, NULL
};
1964 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1965 PnvChip
*chip
= pnv
->chips
[i
];
1966 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
1968 if (ics_valid_irq(&chip8
->psi
.ics
, irq
)) {
1969 return &chip8
->psi
.ics
;
1972 object_child_foreach(OBJECT(chip
), pnv_ics_get_child
, &args
);
1980 PnvChip
*pnv_get_chip(PnvMachineState
*pnv
, uint32_t chip_id
)
1984 for (i
= 0; i
< pnv
->num_chips
; i
++) {
1985 PnvChip
*chip
= pnv
->chips
[i
];
1986 if (chip
->chip_id
== chip_id
) {
1993 static int pnv_ics_resend_child(Object
*child
, void *opaque
)
1995 PnvPHB3
*phb3
= (PnvPHB3
*) object_dynamic_cast(child
, TYPE_PNV_PHB3
);
1998 ics_resend(&phb3
->lsis
);
1999 ics_resend(ICS(&phb3
->msis
));
2004 static void pnv_ics_resend(XICSFabric
*xi
)
2006 PnvMachineState
*pnv
= PNV_MACHINE(xi
);
2009 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2010 PnvChip
*chip
= pnv
->chips
[i
];
2011 Pnv8Chip
*chip8
= PNV8_CHIP(pnv
->chips
[i
]);
2013 ics_resend(&chip8
->psi
.ics
);
2014 object_child_foreach(OBJECT(chip
), pnv_ics_resend_child
, NULL
);
2018 static ICPState
*pnv_icp_get(XICSFabric
*xi
, int pir
)
2020 PowerPCCPU
*cpu
= ppc_get_vcpu_by_pir(pir
);
2022 return cpu
? ICP(pnv_cpu_state(cpu
)->intc
) : NULL
;
2025 static void pnv_pic_print_info(InterruptStatsProvider
*obj
,
2028 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
2033 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2035 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
2036 PNV_CHIP_GET_CLASS(pnv
->chips
[0])->intc_print_info(pnv
->chips
[0], cpu
,
2040 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2041 PNV_CHIP_GET_CLASS(pnv
->chips
[i
])->pic_print_info(pnv
->chips
[i
], mon
);
2045 static int pnv_match_nvt(XiveFabric
*xfb
, uint8_t format
,
2046 uint8_t nvt_blk
, uint32_t nvt_idx
,
2047 bool cam_ignore
, uint8_t priority
,
2048 uint32_t logic_serv
,
2049 XiveTCTXMatch
*match
)
2051 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
2052 int total_count
= 0;
2055 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2056 Pnv9Chip
*chip9
= PNV9_CHIP(pnv
->chips
[i
]);
2057 XivePresenter
*xptr
= XIVE_PRESENTER(&chip9
->xive
);
2058 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
2061 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
2062 priority
, logic_serv
, match
);
2068 total_count
+= count
;
2074 static int pnv10_xive_match_nvt(XiveFabric
*xfb
, uint8_t format
,
2075 uint8_t nvt_blk
, uint32_t nvt_idx
,
2076 bool cam_ignore
, uint8_t priority
,
2077 uint32_t logic_serv
,
2078 XiveTCTXMatch
*match
)
2080 PnvMachineState
*pnv
= PNV_MACHINE(xfb
);
2081 int total_count
= 0;
2084 for (i
= 0; i
< pnv
->num_chips
; i
++) {
2085 Pnv10Chip
*chip10
= PNV10_CHIP(pnv
->chips
[i
]);
2086 XivePresenter
*xptr
= XIVE_PRESENTER(&chip10
->xive
);
2087 XivePresenterClass
*xpc
= XIVE_PRESENTER_GET_CLASS(xptr
);
2090 count
= xpc
->match_nvt(xptr
, format
, nvt_blk
, nvt_idx
, cam_ignore
,
2091 priority
, logic_serv
, match
);
2097 total_count
+= count
;
2103 static void pnv_machine_power8_class_init(ObjectClass
*oc
, void *data
)
2105 MachineClass
*mc
= MACHINE_CLASS(oc
);
2106 XICSFabricClass
*xic
= XICS_FABRIC_CLASS(oc
);
2107 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2108 static const char compat
[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2110 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER8";
2111 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power8_v2.0");
2113 xic
->icp_get
= pnv_icp_get
;
2114 xic
->ics_get
= pnv_ics_get
;
2115 xic
->ics_resend
= pnv_ics_resend
;
2117 pmc
->compat
= compat
;
2118 pmc
->compat_size
= sizeof(compat
);
2121 static void pnv_machine_power9_class_init(ObjectClass
*oc
, void *data
)
2123 MachineClass
*mc
= MACHINE_CLASS(oc
);
2124 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
2125 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2126 static const char compat
[] = "qemu,powernv9\0ibm,powernv";
2128 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER9";
2129 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power9_v2.0");
2130 xfc
->match_nvt
= pnv_match_nvt
;
2132 mc
->alias
= "powernv";
2134 pmc
->compat
= compat
;
2135 pmc
->compat_size
= sizeof(compat
);
2136 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
2139 static void pnv_machine_power10_class_init(ObjectClass
*oc
, void *data
)
2141 MachineClass
*mc
= MACHINE_CLASS(oc
);
2142 PnvMachineClass
*pmc
= PNV_MACHINE_CLASS(oc
);
2143 XiveFabricClass
*xfc
= XIVE_FABRIC_CLASS(oc
);
2144 static const char compat
[] = "qemu,powernv10\0ibm,powernv";
2146 mc
->desc
= "IBM PowerNV (Non-Virtualized) POWER10";
2147 mc
->default_cpu_type
= POWERPC_CPU_TYPE_NAME("power10_v2.0");
2149 pmc
->compat
= compat
;
2150 pmc
->compat_size
= sizeof(compat
);
2151 pmc
->dt_power_mgt
= pnv_dt_power_mgt
;
2153 xfc
->match_nvt
= pnv10_xive_match_nvt
;
2156 static bool pnv_machine_get_hb(Object
*obj
, Error
**errp
)
2158 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
2160 return !!pnv
->fw_load_addr
;
2163 static void pnv_machine_set_hb(Object
*obj
, bool value
, Error
**errp
)
2165 PnvMachineState
*pnv
= PNV_MACHINE(obj
);
2168 pnv
->fw_load_addr
= 0x8000000;
2172 static void pnv_cpu_do_nmi_on_cpu(CPUState
*cs
, run_on_cpu_data arg
)
2174 PowerPCCPU
*cpu
= POWERPC_CPU(cs
);
2175 CPUPPCState
*env
= &cpu
->env
;
2177 cpu_synchronize_state(cs
);
2178 ppc_cpu_do_system_reset(cs
);
2179 if (env
->spr
[SPR_SRR1
] & SRR1_WAKESTATE
) {
2181 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2182 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2185 if (!(env
->spr
[SPR_SRR1
] & SRR1_WAKERESET
)) {
2186 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2187 env
->spr
[SPR_SRR1
] |= SRR1_WAKERESET
;
2191 * For non-powersave system resets, SRR1[42:45] are defined to be
2192 * implementation-dependent. The POWER9 User Manual specifies that
2193 * an external (SCOM driven, which may come from a BMC nmi command or
2194 * another CPU requesting a NMI IPI) system reset exception should be
2195 * 0b0010 (PPC_BIT(44)).
2197 env
->spr
[SPR_SRR1
] |= SRR1_WAKESCOM
;
2201 static void pnv_nmi(NMIState
*n
, int cpu_index
, Error
**errp
)
2206 async_run_on_cpu(cs
, pnv_cpu_do_nmi_on_cpu
, RUN_ON_CPU_NULL
);
2210 static void pnv_machine_class_init(ObjectClass
*oc
, void *data
)
2212 MachineClass
*mc
= MACHINE_CLASS(oc
);
2213 InterruptStatsProviderClass
*ispc
= INTERRUPT_STATS_PROVIDER_CLASS(oc
);
2214 NMIClass
*nc
= NMI_CLASS(oc
);
2216 mc
->desc
= "IBM PowerNV (Non-Virtualized)";
2217 mc
->init
= pnv_init
;
2218 mc
->reset
= pnv_reset
;
2219 mc
->max_cpus
= MAX_CPUS
;
2220 /* Pnv provides a AHCI device for storage */
2221 mc
->block_default_type
= IF_IDE
;
2222 mc
->no_parallel
= 1;
2223 mc
->default_boot_order
= NULL
;
2225 * RAM defaults to less than 2048 for 32-bit hosts, and large
2226 * enough to fit the maximum initrd size at it's load address
2228 mc
->default_ram_size
= 1 * GiB
;
2229 mc
->default_ram_id
= "pnv.ram";
2230 ispc
->print_info
= pnv_pic_print_info
;
2231 nc
->nmi_monitor_handler
= pnv_nmi
;
2233 object_class_property_add_bool(oc
, "hb-mode",
2234 pnv_machine_get_hb
, pnv_machine_set_hb
);
2235 object_class_property_set_description(oc
, "hb-mode",
2236 "Use a hostboot like boot loader");
2239 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2242 .class_init = class_initfn, \
2243 .parent = TYPE_PNV8_CHIP, \
2246 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2249 .class_init = class_initfn, \
2250 .parent = TYPE_PNV9_CHIP, \
2253 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2256 .class_init = class_initfn, \
2257 .parent = TYPE_PNV10_CHIP, \
2260 static const TypeInfo types
[] = {
2262 .name
= MACHINE_TYPE_NAME("powernv10"),
2263 .parent
= TYPE_PNV_MACHINE
,
2264 .class_init
= pnv_machine_power10_class_init
,
2265 .interfaces
= (InterfaceInfo
[]) {
2266 { TYPE_XIVE_FABRIC
},
2271 .name
= MACHINE_TYPE_NAME("powernv9"),
2272 .parent
= TYPE_PNV_MACHINE
,
2273 .class_init
= pnv_machine_power9_class_init
,
2274 .interfaces
= (InterfaceInfo
[]) {
2275 { TYPE_XIVE_FABRIC
},
2280 .name
= MACHINE_TYPE_NAME("powernv8"),
2281 .parent
= TYPE_PNV_MACHINE
,
2282 .class_init
= pnv_machine_power8_class_init
,
2283 .interfaces
= (InterfaceInfo
[]) {
2284 { TYPE_XICS_FABRIC
},
2289 .name
= TYPE_PNV_MACHINE
,
2290 .parent
= TYPE_MACHINE
,
2292 .instance_size
= sizeof(PnvMachineState
),
2293 .class_init
= pnv_machine_class_init
,
2294 .class_size
= sizeof(PnvMachineClass
),
2295 .interfaces
= (InterfaceInfo
[]) {
2296 { TYPE_INTERRUPT_STATS_PROVIDER
},
2302 .name
= TYPE_PNV_CHIP
,
2303 .parent
= TYPE_SYS_BUS_DEVICE
,
2304 .class_init
= pnv_chip_class_init
,
2305 .instance_size
= sizeof(PnvChip
),
2306 .class_size
= sizeof(PnvChipClass
),
2311 * P10 chip and variants
2314 .name
= TYPE_PNV10_CHIP
,
2315 .parent
= TYPE_PNV_CHIP
,
2316 .instance_init
= pnv_chip_power10_instance_init
,
2317 .instance_size
= sizeof(Pnv10Chip
),
2319 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10
, pnv_chip_power10_class_init
),
2322 * P9 chip and variants
2325 .name
= TYPE_PNV9_CHIP
,
2326 .parent
= TYPE_PNV_CHIP
,
2327 .instance_init
= pnv_chip_power9_instance_init
,
2328 .instance_size
= sizeof(Pnv9Chip
),
2330 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9
, pnv_chip_power9_class_init
),
2333 * P8 chip and variants
2336 .name
= TYPE_PNV8_CHIP
,
2337 .parent
= TYPE_PNV_CHIP
,
2338 .instance_init
= pnv_chip_power8_instance_init
,
2339 .instance_size
= sizeof(Pnv8Chip
),
2341 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8
, pnv_chip_power8_class_init
),
2342 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E
, pnv_chip_power8e_class_init
),
2343 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL
,
2344 pnv_chip_power8nvl_class_init
),