| commit | 34222fb8101298ead0e43766340843b469597580 | |
| author | Peter Maydell <peter.maydell@linaro.org> | |
| Wed, 26 Feb 2014 17:20:06 +0000 (26 17:20 +0000) | ||
| committer | Peter Maydell <peter.maydell@linaro.org> | |
| Wed, 26 Feb 2014 17:20:06 +0000 (26 17:20 +0000) | ||
| tree | 8af1e731cf56afb37c46b7236964b287a3924d23 | treesnapshot (tar.gz zip) |
| parent | 9cfa0b4e4c3076683b6c528a1a3b43d5a202a497 | commitdiff |
target-arm: Implement AArch64 view of CPACR
Implement the AArch64 view of the CPACR. The AArch64
CPACR is defined to have a lot of RES0 bits, but since
the architecture defines that RES0 bits may be implemented
as reads-as-written and we know that a v8 CPU will have
no registered coprocessors for cp0..cp13 we can safely
implement the whole register this way.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Implement the AArch64 view of the CPACR. The AArch64
CPACR is defined to have a lot of RES0 bits, but since
the architecture defines that RES0 bits may be implemented
as reads-as-written and we know that a v8 CPU will have
no registered coprocessors for cp0..cp13 we can safely
implement the whole register this way.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
| target-arm/cpu.h | diffblobblamehistory | |
| target-arm/helper.c | diffblobblamehistory |